+ date
Son Aug  4 16:24:30 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
+ make
make -C src/ clean
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
make -C testdata/ clean
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
rm -rf nf_sume_sdnet_ip/
rm -f ./nf_sume_sdnet_ip/SimpleSumeSwitch/xelab.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xvlog.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.jou ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsc.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk_27510.backup.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsimcrash.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsimkernel.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk_27510.backup.jou ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk.jou
rm -f sw/config_tables.c
make -C src/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
minip4_solution.p4(23): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when RealParser terminates
    out metadata meta,
                 ^^^^
minip4_solution.p4(20)
parser RealParser(
       ^^^^^^^^^^
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
make -C testdata/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
./gen_testdata.py
Applying pkt on nf2 at 1: 
Applying pkt on nf3 at 2: 
nf0_applied times:  []
nf1_applied times:  []
nf2_applied times:  [1]
nf3_applied times:  [2]
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
Xilinx SDNet Compiler version 2018.2, build 2342300

Compilation successful
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_externs.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ ./testdata/ ./sw/ --base_address 0x44020000
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_API.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_CLI.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API 
cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o libcam.so libcam.o CAM.o -lsumereg 
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
# The following command only applies if running P4_SWITCH Questa Simulation with Ubuntu
sed -i 's/vsim/vsim \-ldflags \"\-B\/usr\/lib\/x86\_64\-linux-gnu\"/g' nf_sume_sdnet_ip/SimpleSumeSwitch/questa.bash
# modify the P4_SWITCH_tb so that it writes the table configuration writes to a file
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/modify_P4_SWITCH_tb.py nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv
# Fix introduced for SDNet 2017.4
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
# Fix introduced for SDNet 2018.2
sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/
cp testdata/*.axi nf_sume_sdnet_ip/SimpleSumeSwitch/
+ date
Son Aug  4 16:24:43 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch
+ ./vivado_sim.bash
+ find -name '*.v' -o -name '*.vp' -o -name '*.sv'
+ xargs -I % /opt/Xilinx/Vivado/2018.2/bin/xvlog -sv %
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_Engine
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_31_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_31_sec_compute_TopPipe_fl_realmain_apply_v6networks_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_31_sec_compute_TopPipe_fl_realmain_apply_v4networks_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_31_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_31_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_24
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_24_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_24_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_TopPipe_fl_realmain_apply_v6networks_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_23
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_23_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_23_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_23_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_3
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_17_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_17_sec_compute_TopPipe_fl_realmain_apply_v4networks_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_17_sec_compute_realmain_nat46_0_req_lookup_request_key_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_17_sec_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_17_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_17_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_0_sec_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_4
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_5_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_5_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_5_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_5_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_5_sec_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_5_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_5_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_5_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_5_sec_compute_user_metadata_table_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_5_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_5_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_5_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_5_sec_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_5_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_5_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_TopPipe_fl_realmain_src_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_TopPipe_fl_realmain_dst_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_version
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_ihl
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_diff_serv
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_ecn
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_totalLen
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_identification
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_flags
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_fragOffset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_ttl
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_protocol
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_src_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_dst_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ethernet_ethertype
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_checksum
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv6_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_5
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_local_end
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_local_end_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_local_end_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v" into library work
INFO: [VRFC 10-311] analyzing module S_RESETTER_lookup
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v" into library work
INFO: [VRFC 10-311] analyzing module S_RESETTER_line
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v" into library work
INFO: [VRFC 10-311] analyzing module S_RESETTER_control
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopDeparser_t_Engine
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_remove
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_32_sec
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_32_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_32_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_dst_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_src_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_ethertype
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_task
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_ingress_port
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_ethertype
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_table_id
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_version
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ihl
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_diff_serv
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ecn
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_totalLen
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_identification
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_flags
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_fragOffset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ttl
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_protocol
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_checksum
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_src_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_dst_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_version
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_traffic_class
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_flow_label
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_payload_length
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_next_header
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_hop_limit
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_src_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_dst_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_hw_type
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_protocol
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_hw_size
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_protocol_size
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_opcode
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_src_mac_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_src_ipv4_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_dst_mac_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_dst_ipv4_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_src_port
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_dst_port
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_seqNo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ackNo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_data_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_res
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_cwr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ece
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_urg
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ack
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_psh
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_rst
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_syn
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_fin
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_window
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_checksum
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_urgentPtr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_src_port
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_dst_port
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_payload_length
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_checksum
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_type
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_code
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_checksum
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_type
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_code
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_checksum
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_router
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_solicitated
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_override
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_reserved
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_target_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_type
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_ll_length
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_mac_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataMux
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopDeparser_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopParser_t_Engine
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ExtractShifter
INFO: [VRFC 10-311] analyzing module TopParser_t_start
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ipv4_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ipv6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_tcp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_udp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_cpu_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_na_ns_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_arp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dma_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf3_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf2_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf1_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf0_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_send_dig_to_cpu
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_drop
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_pkt_len
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_icmp
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_icmp6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_icmp6_na_ns
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_ipv4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_udp_v6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_udp_v4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_tcp_v6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_tcp_v4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_v4sum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_v6sum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_headerdiff
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_digest_data_1_unused
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_ethertype
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_reject
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_TupleForward
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ExtractShifter
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_version
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_ihl
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_diff_serv
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_ecn
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_totalLen
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_identification
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_flags
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_fragOffset
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_ttl
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_protocol
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_meta_length_without_ip_header
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_version
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_traffic_class
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_flow_label
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_payload_length
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_next_header
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_hop_limit
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_meta_length_without_ip_header
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_hw_type
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_protocol
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_hw_size
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_protocol_size
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_opcode
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_src_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_src_ipv4_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_dst_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_dst_ipv4_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_TupleForward
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_ExtractShifter
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_TopParser_fl_hdr_1_icmp6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_TopParser_fl_hdr_1_icmp6_type
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_TopParser_fl_hdr_1_icmp6_code
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_TopParser_fl_hdr_1_icmp6_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_seqNo
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_ackNo
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_data_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_res
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_cwr
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_ece
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_urg
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_ack
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_psh
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_rst
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_syn
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_fin
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_window
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_urgentPtr
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_TopParser_fl_hdr_1_udp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_TopParser_fl_hdr_1_udp_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_TopParser_fl_hdr_1_udp_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_TopParser_fl_hdr_1_udp_payload_length
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_TopParser_fl_hdr_1_udp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_TopParser_fl_hdr_1_icmp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_TopParser_fl_hdr_1_icmp_type
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_TopParser_fl_hdr_1_icmp_code
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_TopParser_fl_hdr_1_icmp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_TupleForward
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_ExtractShifter
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_na_ns_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_na_ns_router
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_na_ns_solicitated
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_na_ns_override
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_na_ns_reserved
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_na_ns_target_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_type
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_ll_length
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_TupleForward
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_4
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_4_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ethernet_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ethernet_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ethernet_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ethernet_ethertype
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_version
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_ihl
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_diff_serv
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_ecn
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_totalLen
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_identification
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_flags
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_fragOffset
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_ttl
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_protocol
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_version
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_traffic_class
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_flow_label
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_payload_length
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_next_header
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_hop_limit
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_seqNo
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_ackNo
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_data_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_res
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_cwr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_ece
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_urg
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_ack
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_psh
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_rst
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_syn
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_fin
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_window
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_urgentPtr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_udp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_udp_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_udp_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_udp_payload_length
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_udp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp_type
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp_code
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_cpu_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_cpu_task
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_cpu_ingress_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_cpu_ethertype
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_cpu_table_id
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_type
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_code
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_na_ns_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_na_ns_router
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_na_ns_solicitated
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_na_ns_override
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_na_ns_reserved
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_na_ns_target_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_option_link_layer_addr_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_option_link_layer_addr_type
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_option_link_layer_addr_ll_length
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_option_link_layer_addr_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_hw_type
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_protocol
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_hw_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_protocol_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_opcode
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_src_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_src_ipv4_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_dst_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_dst_ipv4_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_switch_task
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_icmp6_na_ns
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_icmp6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_icmp
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_ipv4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_udp_v4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_udp_v6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_tcp_v4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_tcp_v6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_length_without_ip_header
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_cast_length
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_v4sum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_v6sum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_headerdiff
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_table_id
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_digest_data_unused
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_dma_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_nf3_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_nf2_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_nf1_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_nf0_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_send_dig_to_cpu
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_drop
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_pkt_len
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_5
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_5_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_accept
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopParser_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_nat46_0_tuple_in_request.v" into library work
INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_realmain_nat46_0_tuple_in_request
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request.v" into library work
INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_nat64_0_tuple_in_request.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_nat46_0_tuple_in_request.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_fifo_base
INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
INFO: [VRFC 10-311] analyzing module xpm_counter_updn
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
INFO: [VRFC 10-311] analyzing module xpm_fifo_async
INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v6_networks_0_tuple_in_request.v" into library work
INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_realmain_v6_networks_0_tuple_in_request
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_nat64_0_tuple_in_request.v" into library work
INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_realmain_nat64_0_tuple_in_request
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v6_networks_0_tuple_in_request.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_2_t.HDL/TopPipe_lvl_2_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_Engine
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_local_start_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_local_start_0_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_local_start_0_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_v4_networks_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_v4_networks_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_v4_networks_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_NoAction_5_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_NoAction_5_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_NoAction_5_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_debug_4_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_debug_4_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_debug_4_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_debug_4_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_debug_4_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_debug_4_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_debug_table_id_4_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_debug_table_id_4_sec_compute_user_metadata_table_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_debug_table_id_4_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_debug_table_id_4_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_debug_table_id_4_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_debug_table_id_4_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_debug_table_id_4_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_reply_2_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_reply_2_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_reply_2_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_reply_2_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_reply_2_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_controller_reply_2_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_set_egress_port_2_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_set_egress_port_2_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_set_egress_port_2_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_set_egress_port_2_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_set_egress_port_and_mac_2_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_set_egress_port_and_mac_2_sec_compute_p_ethernet_dst_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_set_egress_port_and_mac_2_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_set_egress_port_and_mac_2_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_realmain_set_egress_port_and_mac_2_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_EngineStage_3
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_condition_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_condition_sec_compute_realmain_v6_networks_0_req_lookup_request_key
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_condition_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_condition_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_EngineStage_4
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_interm_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_interm_1_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_interm_1_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_interm_1_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_interm_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_interm_2_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_interm_2_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_interm_2_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_EngineStage_5
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_local_end_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_local_end_1_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t_local_end_1_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_2_t.HDL/TopPipe_lvl_2_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_2_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp" into library work
ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.v" into library work
INFO: [VRFC 10-311] analyzing module S_CONTROLLER_SimpleSumeSwitch
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v6_networks_0_t.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v6_networks_0_t.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v6_networks_0_t.HDL/realmain_v6_networks_0_t.v" into library work
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v6_networks_0_t.HDL/realmain_v6_networks_0_t.vp" into library work
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Wrap
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_IntTop
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Lookup
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Hash_Lookup
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_RamR1RW1
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Cam
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Update
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Hash_Update
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Randmod4
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Randmod4_Rnd
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Randmod5
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Randmod5_Rnd
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_csr
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_Engine
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_realmain_nat64_0_req_lookup_request_key_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" into library work
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch_tb
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v" into library work
INFO: [VRFC 10-311] analyzing module TB_System_Stim
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" into library work
INFO: [VRFC 10-311] analyzing module Check
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_1_t.HDL/TopPipe_lvl_1_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_1_t.HDL/TopPipe_lvl_1_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_Engine
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_start
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_start_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_start_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_NoAction_6_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_NoAction_6_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_NoAction_6_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_NoAction_7_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_NoAction_7_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_NoAction_7_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_11
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_11_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_11_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_6_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_6_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_6_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_6_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_6_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_6_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_6_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_6_sec_compute_user_metadata_table_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_6_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_6_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_6_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_6_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_6_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_TopPipe_fl_realmain_src_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_TopPipe_fl_realmain_dst_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_p_ipv6_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_p_ipv4_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_p_ethernet_ethertype
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_p_ipv6_dst_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_p_ipv6_src_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_p_ipv6_version
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_p_ipv6_traffic_class
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_p_ipv6_flow_label
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_p_ipv6_payload_length
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_p_ipv6_next_header
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_p_ipv6_hop_limit
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_static_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_3
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_0_sec_compute_TopPipe_fl_realmain_tmp_7
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_sec_compute_TopPipe_fl_realmain_tmp_7
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_22
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_22_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_22_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_4
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_15_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_15_sec_compute_TopPipe_fl_realmain_tmp_8
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_15_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_15_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_16_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_16_sec_compute_TopPipe_fl_realmain_tmp_8
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_16_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_16_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_10
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_10_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_10_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_5
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_21
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_21_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_21_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_9
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_9_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_9_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_6
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_20
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_20_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_20_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat64_icmp6_generic_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat64_icmp6_generic_sec_compute_p_icmp_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat64_icmp6_generic_sec_compute_p_ipv4_protocol
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat64_icmp6_generic_sec_compute_user_metadata_switch_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat64_icmp6_generic_sec_compute_user_metadata_chk_icmp
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat64_icmp6_generic_sec_compute_p_icmp6_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat64_icmp6_generic_sec_compute_p_icmp6_na_ns_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat64_icmp6_generic_sec_compute_p_icmp6_option_link_layer_addr_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat64_icmp6_generic_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat64_icmp6_generic_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_7
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_8
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_8_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_8_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_icmp_generic_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_icmp_generic_sec_compute_p_icmp6_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_icmp_generic_sec_compute_p_ipv6_next_header
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_icmp_generic_sec_compute_user_metadata_chk_icmp6
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_icmp_generic_sec_compute_user_metadata_cast_length
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_icmp_generic_sec_compute_p_icmp_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_icmp_generic_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_nat46_icmp_generic_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_8
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_2_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_2_sec_compute_p_icmp_type
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_2_sec_compute_p_icmp_code
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_2_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_2_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_19
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_19_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_19_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_9
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_18_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_18_sec_compute_p_icmp6_type
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_18_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_18_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_7
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_7_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_7_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_10
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_3_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_3_sec_compute_p_icmp_type
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_3_sec_compute_p_icmp_code
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_3_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_3_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_18
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_18_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_18_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_11
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_19_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_19_sec_compute_p_icmp6_type
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_19_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_19_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_6
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_6_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_6_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_12
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_17
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_17_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_17_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_sec_compute_user_metadata_v4sum
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_sec_compute_user_metadata_v6sum
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_13
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_5_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_5_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_5_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_5_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_5_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_5_sec_compute_user_metadata_v4sum
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_5_sec_compute_user_metadata_v6sum
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_5_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_5_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_14
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_21_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_21_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_21_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_21_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_5
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_5_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_5_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_15
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_4_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_4_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_4_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_4_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_16
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_16_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_16_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_16
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_20_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_20_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_20_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_20_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_7_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_7_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_7_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_7_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_17
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_23_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_23_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_23_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_23_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_4
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_4_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_4_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_18
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_6_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_6_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_6_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_6_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_15
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_15_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_15_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_19
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_22_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_22_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_22_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_22_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_8_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_8_sec_compute_p_udp_checksum
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_8_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_8_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_20
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_24_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_24_sec_compute_p_udp_checksum
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_24_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_24_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_3
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_3_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_3_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_21
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_14
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_14_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_14_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_4_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_4_sec_compute_user_metadata_v4sum
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_4_sec_compute_user_metadata_v6sum
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_4_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_4_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_22
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_10_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_10_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_10_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_10_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_6_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_6_sec_compute_user_metadata_v4sum
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_6_sec_compute_user_metadata_v6sum
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_6_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_delta_prepare_6_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_23
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_26_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_26_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_26_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_26_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_2_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_2_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_24
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_9_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_9_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_9_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_9_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_13
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_13_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_13_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_25
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_12_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_12_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_12_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_12_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_25_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_25_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_25_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_25_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_26
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_28_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_28_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_28_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_28_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_1_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_1_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_27
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_11_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_11_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_11_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_11_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_12
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_12_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_12_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_28
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_13_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_13_sec_compute_p_tcp_checksum
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_13_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_13_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_27_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_27_sec_compute_TopPipe_fl_realmain_tmp17_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_27_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_27_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_29
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_14_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_14_sec_compute_TopPipe_fl_realmain_apply_v4networks_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_14_sec_compute_TopPipe_fl_realmain_apply_v6networks_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_14_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_14_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_29_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_29_sec_compute_p_tcp_checksum
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_29_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_29_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_30
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_30_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_30_sec_compute_TopPipe_fl_realmain_apply_v4networks_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_30_sec_compute_TopPipe_fl_realmain_apply_v6networks_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_30_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_act_30_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_31
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_0_compute_realmain_v4_networks_0_req_lookup_request_key_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_0_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_condition_sec_0_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_32
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_interm
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_interm_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_interm_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_interm_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_interm_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_interm_0_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_interm_0_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_interm_0_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_33
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_end_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_end_0_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_end_0_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/realmain_v4_networks_0_t.vp" into library work
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Wrap
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_IntTop
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Lookup
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Hash_Lookup
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_RamR1RW1
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Cam
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Update
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Hash_Update
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Randmod4
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Randmod4_Rnd
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Randmod5
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Randmod5_Rnd
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_csr
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/realmain_v4_networks_0_t.v" into library work
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v" into library work
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_INGRESS
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v" into library work
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_EGRESS
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v" into library work
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat46_0_t.HDL/realmain_nat46_0_t.v" into library work
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat46_0_t.HDL/realmain_nat46_0_t.vp" into library work
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t_Wrap
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t_IntTop
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t_Lookup
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t_Hash_Lookup
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t_RamR1RW1
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t_Cam
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t_Update
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t_Hash_Update
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t_Randmod4
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t_Randmod4_Rnd
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t_Randmod5
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t_Randmod5_Rnd
INFO: [VRFC 10-311] analyzing module realmain_nat46_0_t_csr
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat46_0_t.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat46_0_t.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/realmain_nat64_0_t.v" into library work
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/realmain_nat64_0_t.vp" into library work
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Wrap
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_IntTop
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Lookup
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Hash_Lookup
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_RamR1RW1
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Cam
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Update
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Hash_Update
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Randmod4
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Randmod4_Rnd
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Randmod5
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Randmod5_Rnd
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_csr
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for__OUT_
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_fifo.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_fifo_base
INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
INFO: [VRFC 10-311] analyzing module xpm_counter_updn
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
INFO: [VRFC 10-311] analyzing module xpm_fifo_async
INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopParser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_3_t.HDL/TopPipe_lvl_3_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_3_t.HDL/TopPipe_lvl_3_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_Engine
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_local_start_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_local_start_1_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_local_start_1_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_v6_networks_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_v6_networks_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_v6_networks_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_NoAction_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_NoAction_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_NoAction_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_debug_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_debug_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_debug_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_debug_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_debug_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_debug_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_debug_table_id_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_debug_table_id_sec_compute_user_metadata_table_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_debug_table_id_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_debug_table_id_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_debug_table_id_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_debug_table_id_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_debug_table_id_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_reply_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_reply_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_reply_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_reply_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_reply_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_controller_reply_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_set_egress_port_and_mac_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_set_egress_port_and_mac_sec_compute_p_ethernet_dst_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_set_egress_port_and_mac_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_set_egress_port_and_mac_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_set_egress_port_and_mac_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_set_egress_port_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_set_egress_port_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_set_egress_port_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_realmain_set_egress_port_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_EngineStage_3
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_sink
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_sink_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_3_t_sink_compute_control_increment_offset
+ true
+ mkdir -p xsim.dir/xsc
+ find -name '*.c'
+ xargs /opt/Xilinx/Vivado/2018.2/bin/xsc -mt off -v 1
Turned off multi-threading.
Running compilation flow
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc  -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/    -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/CAM.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" -DXILINX_SIMULATOR
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc  -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/    -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/user.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -DXILINX_SIMULATOR
./Testbench/user.c: In function ‘register_write_control’:
./Testbench/user.c:43:5: warning: implicit declaration of function ‘SV_write_control’ [-Wimplicit-function-declaration]
     SV_write_control(&sv_addr, &sv_data);
     ^~~~~~~~~~~~~~~~
./Testbench/user.c: In function ‘register_read_control’:
./Testbench/user.c:57:5: warning: implicit declaration of function ‘SV_read_control’ [-Wimplicit-function-declaration]
     SV_read_control(&sv_addr, &sv_data);
     ^~~~~~~~~~~~~~~
./Testbench/user.c: In function ‘CAM_Init’:
./Testbench/user.c:117:76: warning: passing argument 9 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
     if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
                                                                            ^~~~~~~~~~~~~~
In file included from ./Testbench/user.c:7:0:
./Testbench/CAM.h:169:5: note: expected ‘void (*)(addr_t,  uint32_t) {aka void (*)(long long unsigned int,  unsigned int)}’ but argument is of type ‘void (*)(uint32_t,  uint32_t) {aka void (*)(unsigned int,  unsigned int)}’
 int CAM_Init_ValidateContext(
     ^~~~~~~~~~~~~~~~~~~~~~~~
./Testbench/user.c:117:92: warning: passing argument 10 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
     if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
                                                                                            ^~~~~~~~~~~~~
In file included from ./Testbench/user.c:7:0:
./Testbench/CAM.h:169:5: note: expected ‘uint32_t (*)(addr_t) {aka unsigned int (*)(long long unsigned int)}’ but argument is of type ‘uint32_t (*)(uint32_t) {aka unsigned int (*)(unsigned int)}’
 int CAM_Init_ValidateContext(
     ^~~~~~~~~~~~~~~~~~~~~~~~
Done compilation
Linking with command:
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W  -O -fPIC  -m64  -shared  -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o"     -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel  -lrdi_xsim_systemc  -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ 

Running command : /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W  -O -fPIC  -m64  -shared  -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o"     -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel  -lrdi_xsim_systemc  -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ 
Done linking: "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so"
+ /opt/Xilinx/Vivado/2018.2/bin/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl 
Multi-threading is on. Using 6 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module work.S_RESETTER_line
Compiling module work.S_RESETTER_lookup
Compiling module work.S_RESETTER_control
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Compiling module work.TopParser_t_start_compute_contro...
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Compiling module work.TopParser_t_start
Compiling module work.TopParser_t_reject_compute_contr...
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Compiling module work.TopParser_t_reject
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Compiling module work.TopParser_t_EngineStage_0
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Compiling module work.TopParser_t_RealParser_ipv4
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Compiling module work.TopParser_t_RealParser_arp
Compiling module work.TopParser_t_EngineStage_1_TupleF...
Compiling module work.TopParser_t_EngineStage_1
Compiling module work.TopParser_t_EngineStage_2_ErrorC...
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Compiling module work.TopParser_t_RealParser_icmp6
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Compiling module work.TopParser_t_RealParser_icmp
Compiling module work.TopParser_t_EngineStage_2_TupleF...
Compiling module work.TopParser_t_EngineStage_2
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Compiling module work.TopParser_t_EngineStage_3
Compiling module work.TopParser_t_EngineStage_4_ErrorC...
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Compiling module work.TopParser_t_start_0
Compiling module work.TopParser_t_EngineStage_4
Compiling module work.TopParser_t_EngineStage_5_ErrorC...
Compiling module work.TopParser_t_accept_compute_contr...
Compiling module work.TopParser_t_accept_compute_contr...
Compiling module work.TopParser_t_accept
Compiling module work.TopParser_t_EngineStage_5
Compiling module work.TopParser_t_Engine
Compiling module work.TopParser_t
Compiling module work.TopPipe_lvl_t_setup_compute_real...
Compiling module work.TopPipe_lvl_t_setup_compute_cont...
Compiling module work.TopPipe_lvl_t_setup_compute_cont...
Compiling module work.TopPipe_lvl_t_setup
Compiling module work.TopPipe_lvl_t_EngineStage_0
Compiling module work.TopPipe_lvl_t_Engine
Compiling module work.TopPipe_lvl_t
Compiling module work.realmain_nat64_0_t_Hash_Lookup
Compiling module work.xpm_memory_base(MEMORY_SIZE=7024...
Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=70...
Compiling module work.realmain_nat64_0_t_RamR1RW1
Compiling module work.realmain_nat64_0_t_Cam
Compiling module work.realmain_nat64_0_t_Lookup
Compiling module work.realmain_nat64_0_t_Hash_Update
Compiling module work.realmain_nat64_0_t_Randmod4_Rnd
Compiling module work.realmain_nat64_0_t_Randmod4
Compiling module work.realmain_nat64_0_t_Randmod5_Rnd
Compiling module work.realmain_nat64_0_t_Randmod5
Compiling module work.realmain_nat64_0_t_Update
Compiling module work.realmain_nat64_0_t_IntTop
Compiling module work.realmain_nat64_0_t_Wrap
Compiling module work.realmain_nat64_0_t_csr
Compiling module work.realmain_nat64_0_t
Compiling module work.TopPipe_lvl_0_t_act_31_sec_compu...
Compiling module work.TopPipe_lvl_0_t_act_31_sec_compu...
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Compiling module work.TopPipe_lvl_0_t_act_31_sec_compu...
Compiling module work.TopPipe_lvl_0_t_act_31_sec
Compiling module work.TopPipe_lvl_0_t_EngineStage_0
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Compiling module work.TopPipe_lvl_0_t_condition_sec_24...
Compiling module work.TopPipe_lvl_0_t_condition_sec_24
Compiling module work.TopPipe_lvl_0_t_EngineStage_1
Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_1_sec
Compiling module work.TopPipe_lvl_0_t_condition_sec_23...
Compiling module work.TopPipe_lvl_0_t_condition_sec_23...
Compiling module work.TopPipe_lvl_0_t_condition_sec_23...
Compiling module work.TopPipe_lvl_0_t_condition_sec_23
Compiling module work.TopPipe_lvl_0_t_EngineStage_2
Compiling module work.TopPipe_lvl_0_t_act_17_sec_compu...
Compiling module work.TopPipe_lvl_0_t_act_17_sec_compu...
Compiling module work.TopPipe_lvl_0_t_act_17_sec_compu...
Compiling module work.TopPipe_lvl_0_t_act_17_sec_compu...
Compiling module work.TopPipe_lvl_0_t_act_17_sec_compu...
Compiling module work.TopPipe_lvl_0_t_act_17_sec
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_0...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_0...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_0...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_0...
Compiling module work.TopPipe_lvl_0_t_EngineStage_3
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_EngineStage_4
Compiling module work.TopPipe_lvl_0_t_local_end_comput...
Compiling module work.TopPipe_lvl_0_t_local_end_comput...
Compiling module work.TopPipe_lvl_0_t_local_end
Compiling module work.TopPipe_lvl_0_t_EngineStage_5
Compiling module work.TopPipe_lvl_0_t_Engine
Compiling module work.TopPipe_lvl_0_t
Compiling module work.realmain_nat46_0_t_Hash_Lookup
Compiling module work.xpm_memory_base(MEMORY_SIZE=5488...
Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=54...
Compiling module work.realmain_nat46_0_t_RamR1RW1
Compiling module work.realmain_nat46_0_t_Cam
Compiling module work.realmain_nat46_0_t_Lookup
Compiling module work.realmain_nat46_0_t_Hash_Update
Compiling module work.realmain_nat46_0_t_Randmod4_Rnd
Compiling module work.realmain_nat46_0_t_Randmod4
Compiling module work.realmain_nat46_0_t_Randmod5_Rnd
Compiling module work.realmain_nat46_0_t_Randmod5
Compiling module work.realmain_nat46_0_t_Update
Compiling module work.realmain_nat46_0_t_IntTop
Compiling module work.realmain_nat46_0_t_Wrap
Compiling module work.realmain_nat46_0_t_csr
Compiling module work.realmain_nat46_0_t
Compiling module work.TopPipe_lvl_1_t_local_start_comp...
Compiling module work.TopPipe_lvl_1_t_local_start_comp...
Compiling module work.TopPipe_lvl_1_t_local_start
Compiling module work.TopPipe_lvl_1_t_EngineStage_0
Compiling module work.TopPipe_lvl_1_t_NoAction_6_sec_c...
Compiling module work.TopPipe_lvl_1_t_NoAction_6_sec_c...
Compiling module work.TopPipe_lvl_1_t_NoAction_6_sec
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_0...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_0...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_0...
Compiling module work.TopPipe_lvl_1_t_EngineStage_1
Compiling module work.TopPipe_lvl_1_t_NoAction_7_sec_c...
Compiling module work.TopPipe_lvl_1_t_NoAction_7_sec_c...
Compiling module work.TopPipe_lvl_1_t_NoAction_7_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_11...
Compiling module work.TopPipe_lvl_1_t_condition_sec_11...
Compiling module work.TopPipe_lvl_1_t_condition_sec_11
Compiling module work.TopPipe_lvl_1_t_realmain_control...
Compiling module work.TopPipe_lvl_1_t_realmain_control...
Compiling module work.TopPipe_lvl_1_t_realmain_control...
Compiling module work.TopPipe_lvl_1_t_realmain_control...
Compiling module work.TopPipe_lvl_1_t_realmain_control...
Compiling module work.TopPipe_lvl_1_t_realmain_control...
Compiling module work.TopPipe_lvl_1_t_realmain_control...
Compiling module work.TopPipe_lvl_1_t_realmain_control...
Compiling module work.TopPipe_lvl_1_t_realmain_control...
Compiling module work.TopPipe_lvl_1_t_realmain_control...
Compiling module work.TopPipe_lvl_1_t_realmain_control...
Compiling module work.TopPipe_lvl_1_t_realmain_control...
Compiling module work.TopPipe_lvl_1_t_realmain_control...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_s...
Compiling module work.TopPipe_lvl_1_t_EngineStage_2
Compiling module work.TopPipe_lvl_1_t_act_0_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_0_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_0_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_0_sec
Compiling module work.TopPipe_lvl_1_t_act_sec_compute_...
Compiling module work.TopPipe_lvl_1_t_act_sec_compute_...
Compiling module work.TopPipe_lvl_1_t_act_sec_compute_...
Compiling module work.TopPipe_lvl_1_t_act_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_22...
Compiling module work.TopPipe_lvl_1_t_condition_sec_22...
Compiling module work.TopPipe_lvl_1_t_condition_sec_22
Compiling module work.TopPipe_lvl_1_t_EngineStage_3
Compiling module work.TopPipe_lvl_1_t_act_15_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_15_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_15_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_15_sec
Compiling module work.TopPipe_lvl_1_t_act_16_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_16_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_16_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_16_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_10...
Compiling module work.TopPipe_lvl_1_t_condition_sec_10...
Compiling module work.TopPipe_lvl_1_t_condition_sec_10
Compiling module work.TopPipe_lvl_1_t_EngineStage_4
Compiling module work.TopPipe_lvl_1_t_condition_sec_21...
Compiling module work.TopPipe_lvl_1_t_condition_sec_21...
Compiling module work.TopPipe_lvl_1_t_condition_sec_21
Compiling module work.TopPipe_lvl_1_t_condition_sec_9_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_9_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_9
Compiling module work.TopPipe_lvl_1_t_EngineStage_5
Compiling module work.TopPipe_lvl_1_t_condition_sec_20...
Compiling module work.TopPipe_lvl_1_t_condition_sec_20...
Compiling module work.TopPipe_lvl_1_t_condition_sec_20
Compiling module work.TopPipe_lvl_1_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_1_t_EngineStage_6
Compiling module work.TopPipe_lvl_1_t_condition_sec_8_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_8_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_8
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_i...
Compiling module work.TopPipe_lvl_1_t_realmain_nat46_i...
Compiling module work.TopPipe_lvl_1_t_EngineStage_7
Compiling module work.TopPipe_lvl_1_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_2_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_19...
Compiling module work.TopPipe_lvl_1_t_condition_sec_19...
Compiling module work.TopPipe_lvl_1_t_condition_sec_19
Compiling module work.TopPipe_lvl_1_t_EngineStage_8
Compiling module work.TopPipe_lvl_1_t_act_18_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_18_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_18_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_18_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_7_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_7_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_7
Compiling module work.TopPipe_lvl_1_t_EngineStage_9
Compiling module work.TopPipe_lvl_1_t_act_3_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_3_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_3_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_3_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_3_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_18...
Compiling module work.TopPipe_lvl_1_t_condition_sec_18...
Compiling module work.TopPipe_lvl_1_t_condition_sec_18
Compiling module work.TopPipe_lvl_1_t_EngineStage_10
Compiling module work.TopPipe_lvl_1_t_act_19_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_19_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_19_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_19_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_6_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_6_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_6
Compiling module work.TopPipe_lvl_1_t_EngineStage_11
Compiling module work.TopPipe_lvl_1_t_condition_sec_17...
Compiling module work.TopPipe_lvl_1_t_condition_sec_17...
Compiling module work.TopPipe_lvl_1_t_condition_sec_17
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_EngineStage_12
Compiling module work.TopPipe_lvl_1_t_act_5_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_5_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_5_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_5_sec
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_EngineStage_13
Compiling module work.TopPipe_lvl_1_t_act_21_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_21_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_21_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_21_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_5_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_5_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_5
Compiling module work.TopPipe_lvl_1_t_EngineStage_14
Compiling module work.TopPipe_lvl_1_t_act_4_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_4_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_4_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_4_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_16...
Compiling module work.TopPipe_lvl_1_t_condition_sec_16...
Compiling module work.TopPipe_lvl_1_t_condition_sec_16
Compiling module work.TopPipe_lvl_1_t_EngineStage_15
Compiling module work.TopPipe_lvl_1_t_act_20_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_20_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_20_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_20_sec
Compiling module work.TopPipe_lvl_1_t_act_7_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_7_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_7_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_7_sec
Compiling module work.TopPipe_lvl_1_t_EngineStage_16
Compiling module work.TopPipe_lvl_1_t_act_23_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_23_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_23_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_23_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_4_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_4_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_4
Compiling module work.TopPipe_lvl_1_t_EngineStage_17
Compiling module work.TopPipe_lvl_1_t_act_6_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_6_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_6_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_6_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_15...
Compiling module work.TopPipe_lvl_1_t_condition_sec_15...
Compiling module work.TopPipe_lvl_1_t_condition_sec_15
Compiling module work.TopPipe_lvl_1_t_EngineStage_18
Compiling module work.TopPipe_lvl_1_t_act_22_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_22_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_22_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_22_sec
Compiling module work.TopPipe_lvl_1_t_act_8_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_8_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_8_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_8_sec
Compiling module work.TopPipe_lvl_1_t_EngineStage_19
Compiling module work.TopPipe_lvl_1_t_act_24_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_24_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_24_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_24_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_3_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_3_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_3
Compiling module work.TopPipe_lvl_1_t_EngineStage_20
Compiling module work.TopPipe_lvl_1_t_condition_sec_14...
Compiling module work.TopPipe_lvl_1_t_condition_sec_14...
Compiling module work.TopPipe_lvl_1_t_condition_sec_14
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_EngineStage_21
Compiling module work.TopPipe_lvl_1_t_act_10_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_10_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_10_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_10_sec
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_realmain_delta_p...
Compiling module work.TopPipe_lvl_1_t_EngineStage_22
Compiling module work.TopPipe_lvl_1_t_act_26_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_26_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_26_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_26_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_2_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_2_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_2
Compiling module work.TopPipe_lvl_1_t_EngineStage_23
Compiling module work.TopPipe_lvl_1_t_act_9_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_9_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_9_sec_comput...
Compiling module work.TopPipe_lvl_1_t_act_9_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_13...
Compiling module work.TopPipe_lvl_1_t_condition_sec_13...
Compiling module work.TopPipe_lvl_1_t_condition_sec_13
Compiling module work.TopPipe_lvl_1_t_EngineStage_24
Compiling module work.TopPipe_lvl_1_t_act_12_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_12_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_12_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_12_sec
Compiling module work.TopPipe_lvl_1_t_act_25_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_25_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_25_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_25_sec
Compiling module work.TopPipe_lvl_1_t_EngineStage_25
Compiling module work.TopPipe_lvl_1_t_act_28_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_28_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_28_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_28_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_1_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_1_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_1
Compiling module work.TopPipe_lvl_1_t_EngineStage_26
Compiling module work.TopPipe_lvl_1_t_act_11_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_11_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_11_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_11_sec
Compiling module work.TopPipe_lvl_1_t_condition_sec_12...
Compiling module work.TopPipe_lvl_1_t_condition_sec_12...
Compiling module work.TopPipe_lvl_1_t_condition_sec_12
Compiling module work.TopPipe_lvl_1_t_EngineStage_27
Compiling module work.TopPipe_lvl_1_t_act_13_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_13_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_13_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_13_sec
Compiling module work.TopPipe_lvl_1_t_act_27_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_27_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_27_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_27_sec
Compiling module work.TopPipe_lvl_1_t_EngineStage_28
Compiling module work.TopPipe_lvl_1_t_act_14_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_14_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_14_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_14_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_14_sec
Compiling module work.TopPipe_lvl_1_t_act_29_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_29_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_29_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_29_sec
Compiling module work.TopPipe_lvl_1_t_EngineStage_29
Compiling module work.TopPipe_lvl_1_t_act_30_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_30_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_30_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_30_sec_compu...
Compiling module work.TopPipe_lvl_1_t_act_30_sec
Compiling module work.TopPipe_lvl_1_t_EngineStage_30
Compiling module work.TopPipe_lvl_1_t_condition_sec_0_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_0_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_0_...
Compiling module work.TopPipe_lvl_1_t_condition_sec_0
Compiling module work.TopPipe_lvl_1_t_EngineStage_31
Compiling module work.TopPipe_lvl_1_t_interm_compute_l...
Compiling module work.TopPipe_lvl_1_t_interm_compute_c...
Compiling module work.TopPipe_lvl_1_t_interm_compute_c...
Compiling module work.TopPipe_lvl_1_t_interm
Compiling module work.TopPipe_lvl_1_t_interm_0_compute...
Compiling module work.TopPipe_lvl_1_t_interm_0_compute...
Compiling module work.TopPipe_lvl_1_t_interm_0_compute...
Compiling module work.TopPipe_lvl_1_t_interm_0
Compiling module work.TopPipe_lvl_1_t_EngineStage_32
Compiling module work.TopPipe_lvl_1_t_local_end_0_comp...
Compiling module work.TopPipe_lvl_1_t_local_end_0_comp...
Compiling module work.TopPipe_lvl_1_t_local_end_0
Compiling module work.TopPipe_lvl_1_t_EngineStage_33
Compiling module work.TopPipe_lvl_1_t_Engine
Compiling module work.TopPipe_lvl_1_t
Compiling module work.realmain_v4_networks_0_t_Hash_Lo...
Compiling module work.xpm_memory_base(MEMORY_SIZE=2160...
Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=21...
Compiling module work.realmain_v4_networks_0_t_RamR1RW...
Compiling module work.realmain_v4_networks_0_t_Cam
Compiling module work.realmain_v4_networks_0_t_Lookup
Compiling module work.realmain_v4_networks_0_t_Hash_Up...
Compiling module work.realmain_v4_networks_0_t_Randmod...
Compiling module work.realmain_v4_networks_0_t_Randmod...
Compiling module work.realmain_v4_networks_0_t_Randmod...
Compiling module work.realmain_v4_networks_0_t_Randmod...
Compiling module work.realmain_v4_networks_0_t_Update
Compiling module work.realmain_v4_networks_0_t_IntTop
Compiling module work.realmain_v4_networks_0_t_Wrap
Compiling module work.realmain_v4_networks_0_t_csr
Compiling module work.realmain_v4_networks_0_t
Compiling module work.TopPipe_lvl_2_t_local_start_0_co...
Compiling module work.TopPipe_lvl_2_t_local_start_0_co...
Compiling module work.TopPipe_lvl_2_t_local_start_0
Compiling module work.TopPipe_lvl_2_t_EngineStage_0
Compiling module work.TopPipe_lvl_2_t_realmain_v4_netw...
Compiling module work.TopPipe_lvl_2_t_realmain_v4_netw...
Compiling module work.TopPipe_lvl_2_t_realmain_v4_netw...
Compiling module work.TopPipe_lvl_2_t_EngineStage_1
Compiling module work.TopPipe_lvl_2_t_NoAction_5_sec_c...
Compiling module work.TopPipe_lvl_2_t_NoAction_5_sec_c...
Compiling module work.TopPipe_lvl_2_t_NoAction_5_sec
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_control...
Compiling module work.TopPipe_lvl_2_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_2_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_2_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_2_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_2_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_2_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_2_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_2_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_2_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_2_t_EngineStage_2
Compiling module work.TopPipe_lvl_2_t_condition_sec_co...
Compiling module work.TopPipe_lvl_2_t_condition_sec_co...
Compiling module work.TopPipe_lvl_2_t_condition_sec_co...
Compiling module work.TopPipe_lvl_2_t_condition_sec
Compiling module work.TopPipe_lvl_2_t_EngineStage_3
Compiling module work.TopPipe_lvl_2_t_interm_1_compute...
Compiling module work.TopPipe_lvl_2_t_interm_1_compute...
Compiling module work.TopPipe_lvl_2_t_interm_1_compute...
Compiling module work.TopPipe_lvl_2_t_interm_1
Compiling module work.TopPipe_lvl_2_t_interm_2_compute...
Compiling module work.TopPipe_lvl_2_t_interm_2_compute...
Compiling module work.TopPipe_lvl_2_t_interm_2_compute...
Compiling module work.TopPipe_lvl_2_t_interm_2
Compiling module work.TopPipe_lvl_2_t_EngineStage_4
Compiling module work.TopPipe_lvl_2_t_local_end_1_comp...
Compiling module work.TopPipe_lvl_2_t_local_end_1_comp...
Compiling module work.TopPipe_lvl_2_t_local_end_1
Compiling module work.TopPipe_lvl_2_t_EngineStage_5
Compiling module work.TopPipe_lvl_2_t_Engine
Compiling module work.TopPipe_lvl_2_t
Compiling module work.realmain_v6_networks_0_t_Hash_Lo...
Compiling module work.xpm_memory_base(MEMORY_SIZE=3696...
Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=36...
Compiling module work.realmain_v6_networks_0_t_RamR1RW...
Compiling module work.realmain_v6_networks_0_t_Cam
Compiling module work.realmain_v6_networks_0_t_Lookup
Compiling module work.realmain_v6_networks_0_t_Hash_Up...
Compiling module work.realmain_v6_networks_0_t_Randmod...
Compiling module work.realmain_v6_networks_0_t_Randmod...
Compiling module work.realmain_v6_networks_0_t_Randmod...
Compiling module work.realmain_v6_networks_0_t_Randmod...
Compiling module work.realmain_v6_networks_0_t_Update
Compiling module work.realmain_v6_networks_0_t_IntTop
Compiling module work.realmain_v6_networks_0_t_Wrap
Compiling module work.realmain_v6_networks_0_t_csr
Compiling module work.realmain_v6_networks_0_t
Compiling module work.TopPipe_lvl_3_t_local_start_1_co...
Compiling module work.TopPipe_lvl_3_t_local_start_1_co...
Compiling module work.TopPipe_lvl_3_t_local_start_1
Compiling module work.TopPipe_lvl_3_t_EngineStage_0
Compiling module work.TopPipe_lvl_3_t_realmain_v6_netw...
Compiling module work.TopPipe_lvl_3_t_realmain_v6_netw...
Compiling module work.TopPipe_lvl_3_t_realmain_v6_netw...
Compiling module work.TopPipe_lvl_3_t_EngineStage_1
Compiling module work.TopPipe_lvl_3_t_NoAction_0_sec_c...
Compiling module work.TopPipe_lvl_3_t_NoAction_0_sec_c...
Compiling module work.TopPipe_lvl_3_t_NoAction_0_sec
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_control...
Compiling module work.TopPipe_lvl_3_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_3_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_3_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_3_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_3_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_3_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_3_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_3_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_3_t_realmain_set_egr...
Compiling module work.TopPipe_lvl_3_t_EngineStage_2
Compiling module work.TopPipe_lvl_3_t_sink_compute_con...
Compiling module work.TopPipe_lvl_3_t_sink_compute_con...
Compiling module work.TopPipe_lvl_3_t_sink
Compiling module work.TopPipe_lvl_3_t_EngineStage_3
Compiling module work.TopPipe_lvl_3_t_Engine
Compiling module work.TopPipe_lvl_3_t
Compiling module work.TopDeparser_t_EngineStage_0_Erro...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0
Compiling module work.TopDeparser_t_EngineStage_1_Erro...
Compiling module work.TopDeparser_t_act_32_sec_compute...
Compiling module work.TopDeparser_t_act_32_sec_compute...
Compiling module work.TopDeparser_t_act_32_sec
Compiling module work.TopDeparser_t_EngineStage_1
Compiling module work.TopDeparser_t_EngineStage_2_Erro...
Compiling module work.TopDeparser_t_emit_10_compute_co...
Compiling module work.TopDeparser_t_emit_10_compute__S...
Compiling module work.TopDeparser_t_emit_10_compute__S...
Compiling module work.TopDeparser_t_emit_10_compute__S...
Compiling module work.TopDeparser_t_emit_10_compute_co...
Compiling module work.TopDeparser_t_emit_10_compute_co...
Compiling module work.TopDeparser_t_emit_10
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2
Compiling module work.TopDeparser_t_EngineStage_3_Erro...
Compiling module work.TopDeparser_t_emit_9_compute_con...
Compiling module work.TopDeparser_t_emit_9_compute__ST...
Compiling module work.TopDeparser_t_emit_9_compute__ST...
Compiling module work.TopDeparser_t_emit_9_compute__ST...
Compiling module work.TopDeparser_t_emit_9_compute__ST...
Compiling module work.TopDeparser_t_emit_9_compute_con...
Compiling module work.TopDeparser_t_emit_9_compute_con...
Compiling module work.TopDeparser_t_emit_9
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
Compiling module work.TopDeparser_t_EngineStage_3
Compiling module work.TopDeparser_t_EngineStage_4_Erro...
Compiling module work.TopDeparser_t_emit_8_compute_con...
Compiling module work.TopDeparser_t_emit_8_compute__ST...
Compiling module work.TopDeparser_t_emit_8_compute__ST...
Compiling module work.TopDeparser_t_emit_8_compute__ST...
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Compiling module work.TopDeparser_t_emit_8_compute__ST...
Compiling module work.TopDeparser_t_emit_8_compute_con...
Compiling module work.TopDeparser_t_emit_8_compute_con...
Compiling module work.TopDeparser_t_emit_8
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
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Compiling module work.TopDeparser_t_EngineStage_4_Edit...
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
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Compiling module work.TopDeparser_t_EngineStage_4_Edit...
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
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Compiling module work.TopDeparser_t_EngineStage_4_Edit...
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Compiling module work.TopDeparser_t_EngineStage_4_Edit...
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
Compiling module work.TopDeparser_t_EngineStage_4
Compiling module work.TopDeparser_t_EngineStage_5_Erro...
Compiling module work.TopDeparser_t_emit_7_compute_con...
Compiling module work.TopDeparser_t_emit_7_compute__ST...
Compiling module work.TopDeparser_t_emit_7_compute__ST...
Compiling module work.TopDeparser_t_emit_7_compute__ST...
Compiling module work.TopDeparser_t_emit_7_compute__ST...
Compiling module work.TopDeparser_t_emit_7_compute__ST...
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Compiling module work.TopDeparser_t_emit_7_compute__ST...
Compiling module work.TopDeparser_t_emit_7_compute__ST...
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Compiling module work.TopDeparser_t_Engine
Compiling module work.TopDeparser_t
Compiling module work.xpm_cdc_sync_rst(DEST_SYNC_FF=2,...
Compiling module work.xpm_fifo_rst(COMMON_CLOCK=0)
Compiling module work.xpm_fifo_reg_bit
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
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Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.S_BRIDGER_for_realmain_nat64_0_t...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module work.S_PROTOCOL_ADAPTER_INGRESS
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Compiling module work.xpm_fifo_rst_default
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_TopParser
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_S_SYNCER_for_S_SYNC...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=7)
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_S_SYNCER_for_S_SYNC...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_S_SYNCER_for_S_SYNC...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=10)
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_S_SYNCER_for_S_SYNC...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_S_SYNCER_for_TopDep...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_TopDeparser
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for__OUT_
Compiling module work.S_CONTROLLER_SimpleSumeSwitch
Compiling module work.SimpleSumeSwitch
Compiling module work.TB_System_Stim
Compiling module work.Check
Compiling module work.SimpleSumeSwitch_tb
Compiling module work.glbl
Built simulation snapshot work.SimpleSumeSwitch_tb#work.glbl

****** Webtalk v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Sun Aug  4 16:26:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2018.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Sun Aug  4 16:26:00 2019...
+ /opt/Xilinx/Vivado/2018.2/bin/xsim --runall SimpleSumeSwitch_tb#work.glbl

****** xsim v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsim_script.tcl
# xsim {work.SimpleSumeSwitch_tb#work.glbl} -autoloadwcfg -runall
Vivado Simulator 2018.2
Time resolution is 1 ps
run -all
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat64_0.realmain_nat64_0_t_Wrap_inst.realmain_nat64_0_t_IntTop_inst.realmain_nat64_0_t_Lookup_inst.realmain_nat64_0_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_795  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat64_0.realmain_nat64_0_t_Wrap_inst.realmain_nat64_0_t_IntTop_inst.realmain_nat64_0_t_Lookup_inst.realmain_nat64_0_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_795  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat64_0.realmain_nat64_0_t_Wrap_inst.realmain_nat64_0_t_IntTop_inst.realmain_nat64_0_t_Lookup_inst.realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_795  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat64_0.realmain_nat64_0_t_Wrap_inst.realmain_nat64_0_t_IntTop_inst.realmain_nat64_0_t_Lookup_inst.realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_795  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat64_0.realmain_nat64_0_t_Wrap_inst.realmain_nat64_0_t_IntTop_inst.realmain_nat64_0_t_Lookup_inst.realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_795  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat46_0.realmain_nat46_0_t_Wrap_inst.realmain_nat46_0_t_IntTop_inst.realmain_nat46_0_t_Lookup_inst.realmain_nat46_0_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat46_0/realmain_nat46_0_t_Wrap_inst/realmain_nat46_0_t_IntTop_inst/realmain_nat46_0_t_Lookup_inst/realmain_nat46_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_1252  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat46_0.realmain_nat46_0_t_Wrap_inst.realmain_nat46_0_t_IntTop_inst.realmain_nat46_0_t_Lookup_inst.realmain_nat46_0_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat46_0/realmain_nat46_0_t_Wrap_inst/realmain_nat46_0_t_IntTop_inst/realmain_nat46_0_t_Lookup_inst/realmain_nat46_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_1252  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat46_0.realmain_nat46_0_t_Wrap_inst.realmain_nat46_0_t_IntTop_inst.realmain_nat46_0_t_Lookup_inst.realmain_nat46_0_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat46_0/realmain_nat46_0_t_Wrap_inst/realmain_nat46_0_t_IntTop_inst/realmain_nat46_0_t_Lookup_inst/realmain_nat46_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_1252  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat46_0.realmain_nat46_0_t_Wrap_inst.realmain_nat46_0_t_IntTop_inst.realmain_nat46_0_t_Lookup_inst.realmain_nat46_0_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat46_0/realmain_nat46_0_t_Wrap_inst/realmain_nat46_0_t_IntTop_inst/realmain_nat46_0_t_Lookup_inst/realmain_nat46_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_1252  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat46_0.realmain_nat46_0_t_Wrap_inst.realmain_nat46_0_t_IntTop_inst.realmain_nat46_0_t_Lookup_inst.realmain_nat46_0_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat46_0/realmain_nat46_0_t_Wrap_inst/realmain_nat46_0_t_IntTop_inst/realmain_nat46_0_t_Lookup_inst/realmain_nat46_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_1252  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_3758  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_3758  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_3758  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_3758  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_3758  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v6_networks_0.realmain_v6_networks_0_t_Wrap_inst.realmain_v6_networks_0_t_IntTop_inst.realmain_v6_networks_0_t_Lookup_inst.realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v6_networks_0/realmain_v6_networks_0_t_Wrap_inst/realmain_v6_networks_0_t_IntTop_inst/realmain_v6_networks_0_t_Lookup_inst/realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_4091  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v6_networks_0.realmain_v6_networks_0_t_Wrap_inst.realmain_v6_networks_0_t_IntTop_inst.realmain_v6_networks_0_t_Lookup_inst.realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v6_networks_0/realmain_v6_networks_0_t_Wrap_inst/realmain_v6_networks_0_t_IntTop_inst/realmain_v6_networks_0_t_Lookup_inst/realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_4091  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v6_networks_0.realmain_v6_networks_0_t_Wrap_inst.realmain_v6_networks_0_t_IntTop_inst.realmain_v6_networks_0_t_Lookup_inst.realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v6_networks_0/realmain_v6_networks_0_t_Wrap_inst/realmain_v6_networks_0_t_IntTop_inst/realmain_v6_networks_0_t_Lookup_inst/realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_4091  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v6_networks_0.realmain_v6_networks_0_t_Wrap_inst.realmain_v6_networks_0_t_IntTop_inst.realmain_v6_networks_0_t_Lookup_inst.realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v6_networks_0/realmain_v6_networks_0_t_Wrap_inst/realmain_v6_networks_0_t_IntTop_inst/realmain_v6_networks_0_t_Lookup_inst/realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_4091  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v6_networks_0.realmain_v6_networks_0_t_Wrap_inst.realmain_v6_networks_0_t_IntTop_inst.realmain_v6_networks_0_t_Lookup_inst.realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v6_networks_0/realmain_v6_networks_0_t_Wrap_inst/realmain_v6_networks_0_t_IntTop_inst/realmain_v6_networks_0_t_Lookup_inst/realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_4091  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_realmain_nat64_0_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8328  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_realmain_nat46_0_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_realmain_nat46_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8418  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8418  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_realmain_v6_networks_0_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_realmain_v6_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8328  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.mg25zmf1ofwkfontqt1n9yffc8g_1043.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/mg25zmf1ofwkfontqt1n9yffc8g_1043/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8679  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.wd6m9hkohzrnvu5j5dn_1751.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/wd6m9hkohzrnvu5j5dn_1751/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8709  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.q5lt3xogum8dp0luiapuv_1803.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/q5lt3xogum8dp0luiapuv_1803/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8773  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.oluw49xc6s6x2lnan0woxnt4ki9d7_2683.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/oluw49xc6s6x2lnan0woxnt4ki9d7_2683/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8857  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.spvuwc5cdbma9ndkjnng82gbd0j4_1535.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/spvuwc5cdbma9ndkjnng82gbd0j4_1535/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8679  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.qwvpwwj1oqk3kbyib_1092.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/qwvpwwj1oqk3kbyib_1092/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8709  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.jgc9f3wvpo1cc9w0vmn_2622.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jgc9f3wvpo1cc9w0vmn_2622/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9038  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.urtk9g11l7b1wktpjhz_102.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/urtk9g11l7b1wktpjhz_102/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9122  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.lwvda5p0phh80ifjse30cqvz6x8_1929.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lwvda5p0phh80ifjse30cqvz6x8_1929/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9206  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.q0ok5zbwb1k22ohduxser9w36fwz_435.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/q0ok5zbwb1k22ohduxser9w36fwz_435/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8773  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.d0jbxzyh0rwrvsrwfo2tiu6xkef5fgxc_552.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/d0jbxzyh0rwrvsrwfo2tiu6xkef5fgxc_552/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8857  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.j0c4ak2u389gao017ldof4rnc2b7m_1226.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/j0c4ak2u389gao017ldof4rnc2b7m_1226/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9458  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.d1g105ht8m7v1qawb3o9dr9_2395.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/d1g105ht8m7v1qawb3o9dr9_2395/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8679  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.lxdqn3n2b9r4uil82nptfbk_678.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lxdqn3n2b9r4uil82nptfbk_678/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8709  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.ydve5pvbd124xpynovuqk6ztq84pi1_1854.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ydve5pvbd124xpynovuqk6ztq84pi1_1854/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9645  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.ge91zikxkmj90hjb4yelneqf0hg9av05_1448.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ge91zikxkmj90hjb4yelneqf0hg9av05_1448/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9206  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.gibuo1pkef5kdkguq0lw0h7qexzjis_1241.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gibuo1pkef5kdkguq0lw0h7qexzjis_1241/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9813  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.qjm14uo4rfitmca6wgpg9mwj6a9lqm_933.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/qjm14uo4rfitmca6wgpg9mwj6a9lqm_933/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9038  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.cw537g3h5y67zsrsyygxkgrbbl7od_1626.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/cw537g3h5y67zsrsyygxkgrbbl7od_1626/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8773  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.dw1aqd1f4p187ik0u0wkzgwobt1zsjd_1092.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dw1aqd1f4p187ik0u0wkzgwobt1zsjd_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9122  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.g4gvxu47klkpmd6h02ff2eu9wol7y_1275.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/g4gvxu47klkpmd6h02ff2eu9wol7y_1275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_10149  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.o8r7k7n9sszwwgpdfe70ufwwot04_1627.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/o8r7k7n9sszwwgpdfe70ufwwot04_1627/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8857  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.kpxmgg5e5a77g05bgdpz04szg_1353.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/kpxmgg5e5a77g05bgdpz04szg_1353/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9458  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.qjww57t2kruvp786g_1160.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/qjww57t2kruvp786g_1160/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8679  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.n7kcvr2ks3jg10i7w20bn4ofba5c2_560.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/n7kcvr2ks3jg10i7w20bn4ofba5c2_560/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8709  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.kd7cxsb37nl8ldklewh_2022.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/kd7cxsb37nl8ldklewh_2022/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9645  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.dliq5160x9q3ob3ziww3ec4l_2103.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dliq5160x9q3ob3ziww3ec4l_2103/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9206  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.mqi99bn8a9mqgqouvkhj6j_1314.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mqi99bn8a9mqgqouvkhj6j_1314/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9813  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.iq8mjxf1bdfj2mephm6rr4we_229.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/iq8mjxf1bdfj2mephm6rr4we_229/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9038  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.vm0wbvx6uh27b15dafqb9trz0_469.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vm0wbvx6uh27b15dafqb9trz0_469/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_10844  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.mg5e7uq4sox92ahre8_771.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mg5e7uq4sox92ahre8_771/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8773  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.c46492jd536yi3d835pvezn_2133.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/c46492jd536yi3d835pvezn_2133/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9122  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.pe9kxlbpfaf91t5q314jp5d3x_938.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/pe9kxlbpfaf91t5q314jp5d3x_938/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_10149  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.c5kbranu2plzerrko3e5rfcmcjgzw7d_2413.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/c5kbranu2plzerrko3e5rfcmcjgzw7d_2413/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8857  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.dva0wp6m6ftvi2mrfjif0_744.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dva0wp6m6ftvi2mrfjif0_744/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9458  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.wizuqatrrqcfahagcl_1321.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/wizuqatrrqcfahagcl_1321/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_11362  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.iisg9lr3w5gq38op0l4_633.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/iisg9lr3w5gq38op0l4_633/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_11392  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.ydbms2kcmdc8uj63xrkbqmwhyriohysk_840.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ydbms2kcmdc8uj63xrkbqmwhyriohysk_840/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_11456  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.f29vrzzis9si1z9m4whyn_1928.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f29vrzzis9si1z9m4whyn_1928/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_11542  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.wp0udhk2lji436nwn17r_1130.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/wp0udhk2lji436nwn17r_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_11626  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.xltsjk7qomt4gyy997hn7rf53jdcrewr_2265.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xltsjk7qomt4gyy997hn7rf53jdcrewr_2265/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_11710  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.fdc1b8jd5exgma5exsx6dwk0pshj8ik_2160.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/fdc1b8jd5exgma5exsx6dwk0pshj8ik_2160/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_11794  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.zb53m7redvl3txep8gt5g17b6fp_854.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/zb53m7redvl3txep8gt5g17b6fp_854/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_11794  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.w33d8ta3e2tbyikkacbvb_894.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/w33d8ta3e2tbyikkacbvb_894/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_11962  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.rg748xkzh2no7ovmtztpj9pyix8b83x_646.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rg748xkzh2no7ovmtztpj9pyix8b83x_646/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_12046  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.mqad144792y0rdib0ang0qsm_893.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mqad144792y0rdib0ang0qsm_893/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_12130  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.d1ak1chy39mywowfa0m_1818.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/d1ak1chy39mywowfa0m_1818/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_12214  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.y4ftfxhh5rf6q0wev8bbhugs93omj_1782.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y4ftfxhh5rf6q0wev8bbhugs93omj_1782/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_12298  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.s64kc2ihrwro7ehk90lyi0zp_1265.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/s64kc2ihrwro7ehk90lyi0zp_1265/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8679  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.pn8m4rk4gbr8khorxuwgb0ezepq_1176.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/pn8m4rk4gbr8khorxuwgb0ezepq_1176/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8709  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.l33zpga4pmoobgvodjq93lypw_795.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/l33zpga4pmoobgvodjq93lypw_795/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9645  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.o33l7rwv5gfhb2iwxxr4bywcci3_175.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/o33l7rwv5gfhb2iwxxr4bywcci3_175/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9206  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.xry0xg2ebrzf0ot8hebl_2383.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/xry0xg2ebrzf0ot8hebl_2383/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9813  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.k5f9trbkdldofkki5_1890.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/k5f9trbkdldofkki5_1890/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9038  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.b5xdw9d10icnscpo3riiilyyigczv5_789.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/b5xdw9d10icnscpo3riiilyyigczv5_789/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_10844  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.g2q1bdtvrcglf6z61e7oujxzn64_353.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/g2q1bdtvrcglf6z61e7oujxzn64_353/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_10844  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.i8sf7q9lkkkybx78k_313.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/i8sf7q9lkkkybx78k_313/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_12130  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.ef45rhntiq7opdchfwzlr0y69epii_119.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/ef45rhntiq7opdchfwzlr0y69epii_119/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8773  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.dl6ag915khdq5ffyfo1x_1591.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/dl6ag915khdq5ffyfo1x_1591/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9122  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.s7froqkebf9gcmh4irvu6lw_1911.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/s7froqkebf9gcmh4irvu6lw_1911/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_13247  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.b35irwsn41dv434k6rklp_1799.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/b35irwsn41dv434k6rklp_1799/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8857  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.ee35hckb3y2nr9m9nyzigwi3q99c_623.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/ee35hckb3y2nr9m9nyzigwi3q99c_623/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9458  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.yy31n4xifb3do8cpma0_1813.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/yy31n4xifb3do8cpma0_1813/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8679  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.nfum3utu3w2btbzx2srepjot9_2687.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/nfum3utu3w2btbzx2srepjot9_2687/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8709  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.vuc3mz123mlzv6upwtfz0jkrrdj7vp9_100.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/vuc3mz123mlzv6upwtfz0jkrrdj7vp9_100/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9038  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.mehas59hs1iy7s4w61_2049.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/mehas59hs1iy7s4w61_2049/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9122  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.a417v4s5yhrfhbcbhj49h52yypfo46_2106.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/a417v4s5yhrfhbcbhj49h52yypfo46_2106/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9206  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.bcf2vtzdberyj32nla0_1661.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/bcf2vtzdberyj32nla0_1661/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8773  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.hay87mz7kvds9hqo6lnum_1465.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/hay87mz7kvds9hqo6lnum_1465/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8857  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.lpq5gqc3vh2lyzsmz56msor1_578.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/lpq5gqc3vh2lyzsmz56msor1_578/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9458  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.oc4siagfop3sl6tkiksopl1wlsipurna_1042.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/oc4siagfop3sl6tkiksopl1wlsipurna_1042/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_14099  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.dtvtepq5etvb17igatwer9h5_663.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/dtvtepq5etvb17igatwer9h5_663/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8709  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.bsy64vs17k5552vkluev3a_407.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/bsy64vs17k5552vkluev3a_407/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_9206  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.zxj8spmjc8w3eutdsraqo8ywtwxb9_1694.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/zxj8spmjc8w3eutdsraqo8ywtwxb9_1694/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8773  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
[SW] CAM_Init() - start
[SW] CAM_Init() - done
SV_write_control()- start
[SW] CAM_EnableDevice() - start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_write_control()- start
SV_write_control()- done
[SW] CAM_EnableDevice() - done
CAM UPDATE           0: KEY(hex) = 20010DB800420000000000000A00002A VALUE(hex) = 220010DB80042000000000000000000000A00000020010DB80042000000000000000000000000
SV_write_control()- start
[SW] CAM_WriteEntry() - start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_read_control()- start
SV_read_control()- done
[SW] CAM_WriteEntry() - done
[SW] CAM_Init() - start
[SW] CAM_Init() - done
[SW] CAM_EnableDevice() - start
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_write_control()- start
SV_write_control()- done
[SW] CAM_EnableDevice() - done
[SW] CAM_WriteEntry() - start
CAM UPDATE           0: KEY(hex) = A000042 VALUE(hex) = 220010DB80042000000000000000000000A00000020010DB80042000000000000000000000000
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_read_control()- start
[SW] CAM_WriteEntry() - done
[SW] CAM_Init() - start
[SW] CAM_Init() - done
[SW] CAM_EnableDevice() - start
SV_read_control()- done
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_write_control()- start
SV_write_control()- done
[SW] CAM_EnableDevice() - done
[SW] CAM_WriteEntry() - start
CAM UPDATE           0: KEY(hex) = A00002A VALUE(hex) = 1100000000000000000000000
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_read_control()- start
[SW] CAM_WriteEntry() - done
[SW] CAM_Init() - start
[SW] CAM_Init() - done
[SW] CAM_EnableDevice() - start
SV_read_control()- done
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_write_control()- start
SV_write_control()- done
[SW] CAM_EnableDevice() - done
[SW] CAM_WriteEntry() - start
CAM UPDATE           0: KEY(hex) = 20010DB8004200000000000000000042 VALUE(hex) = 1400000000000000000000000
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_read_control()- start
[SW] CAM_WriteEntry() - done
SV_read_control()- done
[7448686]  INFO: finished packet stimulus file
[9799412]  INFO: packet 1 tuple OK < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000040100000 >
[9799412]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 000000004200b80d01204011fc0100000060dd86081111111108082222222208)
[9802744]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 414129bffc0129098813420000000000000000004200b80d01202a00000a0000)
[9806076]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9809408]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9812740]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9816072]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9819404]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9822736]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9826068]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9829400]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9832732]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9836064]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9839396]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9842728]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9846060]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9849392]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9852724]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9856056]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (1, 0003ffff, 000a4200000a7264114000000000414141414141414141414141414141414141)
[9859388]  INFO: packet 2 tuple OK < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000010400000 >
[9859388]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 000a4200000a7264114000000000100200450008082222222208081111111108)
[9862720]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 414141414141414141414141414141414141414141412011fc01881329092a00)
[9866052]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9869384]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9872716]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9876048]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9879380]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9882712]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9886044]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9889376]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9892708]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9896040]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9899372]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9902704]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9906036]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9909368]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 4141414141414141414141414141414141414141414141414141414141414141)
[9912700]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (1, 3fffffff, 0000414141414141414141414141414141414141414141414141414141414141)
[13248032]  INFO: stopping simulation after 1000 idle cycles
[13248032]  INFO: all expected data successfully received
[13248032]  INFO: TEST PASSED
$finish called at time : 13248032 ps : File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" Line 207
run: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:18 . Memory (MB): peak = 1404.152 ; gain = 128.000 ; free physical = 7398 ; free virtual = 29184
exit
INFO: [Common 17-206] Exiting xsim at Sun Aug  4 16:26:28 2019...
+ grep ^expected /home/nico/master-thesis/netpfga/log/compile-2019-08-04-162430-10.2-nat64-simulationonly
+ sed -e s/.*= <// -e s/.*= (//
+ expected_line=
+ grep ^actual /home/nico/master-thesis/netpfga/log/compile-2019-08-04-162430-10.2-nat64-simulationonly
+ sed -e s/.*= <// -e s/.*= (//
+ actual_line=
+ exit 0
