+ date
Mit Jul 24 22:29:42 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
+ make
make -C src/ clean
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
make -C testdata/ clean
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
rm -rf nf_sume_sdnet_ip/
rm -f 
rm -f sw/config_tables.c
make -C src/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
actions_egress.p4(52): warning: Table v6_networks is not used; removing
table v6_networks {
      ^^^^^^^^^^^
actions_egress.p4(69): warning: Table v4_networks is not used; removing
table v4_networks {
      ^^^^^^^^^^^
actions_nat64_generic.p4(174): warning: Table nat46 is not used; removing
    table nat46 {
          ^^^^^
minip4_solution.p4(38): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when RealParser terminates
    out metadata meta,
                 ^^^^
minip4_solution.p4(35)
parser RealParser(
       ^^^^^^^^^^
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
make -C testdata/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
./gen_testdata.py
Applying pkt on nf0 at 1: 
Applying pkt on nf1 at 2: 
Applying pkt on nf2 at 3: 
Applying pkt on nf3 at 4: 
nf0_applied times:  [1]
nf1_applied times:  [2]
nf2_applied times:  [3]
nf3_applied times:  [4]
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
Xilinx SDNet Compiler version 2018.2, build 2342300

Compilation successful
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_externs.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ ./testdata/ ./sw/ --base_address 0x44020000
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_API.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_CLI.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API 
cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o libcam.so libcam.o CAM.o -lsumereg 
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/LPM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/LPM.c: In function ‘LPM_Mgt_LoadDataset’:
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/LPM.c:203:51: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
             if(cx->base | my_config_data[i][0] == (uint32_t)&dev->update_req)
                                                   ^
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/LPM.c: In function ‘LPM_Mgt_VerifyDataset’:
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/LPM.c:293:40: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
             if (my_config_tmp[i][0] == (uint32_t)&dev->update_req)
                                        ^
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/LPM.c:303:27: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
             cmd_address = (uint32_t )&dev->update_req;
                           ^
cc -std=c99 -Wall -Werror -fPIC -c liblpm.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API 
cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o liblpm.so liblpm.o LPM.o -lsumereg 
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
# The following command only applies if running P4_SWITCH Questa Simulation with Ubuntu
sed -i 's/vsim/vsim \-ldflags \"\-B\/usr\/lib\/x86\_64\-linux-gnu\"/g' nf_sume_sdnet_ip/SimpleSumeSwitch/questa.bash
# modify the P4_SWITCH_tb so that it writes the table configuration writes to a file
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/modify_P4_SWITCH_tb.py nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv
# Fix introduced for SDNet 2017.4
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
# Fix introduced for SDNet 2018.2
sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/
cp testdata/*.axi nf_sume_sdnet_ip/SimpleSumeSwitch/
+ date
Mit Jul 24 22:29:47 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch
+ ./vivado_sim.bash
+ find -name '*.v' -o -name '*.vp' -o -name '*.sv'
+ xargs -I % /opt/Xilinx/Vivado/2018.2/bin/xvlog -sv %
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_Engine
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_4
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_4_compute_realmain_lookup_table_0_req_lookup_request_key
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_4_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_4_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_4_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_NoAction_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_NoAction_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_NoAction_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_user_metadata_table_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_TopPipe_fl_realmain_src_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_TopPipe_fl_realmain_dst_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_version
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_ihl
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_diff_serv
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_ecn
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_totalLen
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_identification
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_flags
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_fragOffset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_ttl
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_protocol
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_src_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_dst_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ethernet_ethertype
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_user_metadata_chk_ipv4
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv6_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_3
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_3
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_3_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_3_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_4
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_0_sec_compute_TopPipe_fl_realmain_tmp_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec_compute_TopPipe_fl_realmain_tmp_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_5
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_2_compute_realmain_lookup_table_0_req_lookup_request_key
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_2_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_2_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_2_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_6
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_1_compute_realmain_lookup_table_0_req_lookup_request_key
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_1_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_1_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_1_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_7
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_p_icmp_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_p_ipv4_protocol
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_user_metadata_switch_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_user_metadata_chk_icmp
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_p_icmp6_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_p_icmp6_na_ns_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_p_icmp6_option_link_layer_addr_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_8
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_0_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_0_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_9
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_p_icmp_type
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_p_icmp_code
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_10
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_compute_realmain_lookup_table_0_req_lookup_request_key
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_11
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_p_icmp_type
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_p_icmp_code
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_realmain_lookup_table_0_req_lookup_request_key
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_12
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_local_end
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_local_end_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_local_end_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for__OUT_
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_fifo.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_fifo_base
INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
INFO: [VRFC 10-311] analyzing module xpm_counter_updn
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
INFO: [VRFC 10-311] analyzing module xpm_fifo_async
INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopParser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_nat64_0_tuple_in_request.v" into library work
INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_realmain_nat64_0_tuple_in_request
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_fifo_base
INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
INFO: [VRFC 10-311] analyzing module xpm_counter_updn
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
INFO: [VRFC 10-311] analyzing module xpm_fifo_async
INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_nat64_0_tuple_in_request.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request.v" into library work
INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_1_t.HDL/TopPipe_lvl_1_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_Engine
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_start
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_start_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_start_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_lookup_table_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_lookup_table_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_lookup_table_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_do_nothing_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_do_nothing_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_do_nothing_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_all_ports_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_all_ports_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_all_ports_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_all_ports_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_port1_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_port1_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_port1_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_port1_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec_compute_TopPipe_fl_realmain_temp_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec_compute_p_ethernet_dst_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec_compute_p_ethernet_src_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_3
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_sink
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_sink_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_sink_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_1_t.HDL/TopPipe_lvl_1_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_Engine
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_realmain_nat64_0_req_lookup_request_key_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp" into library work
ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.v" into library work
INFO: [VRFC 10-311] analyzing module S_CONTROLLER_SimpleSumeSwitch
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v" into library work
INFO: [VRFC 10-311] analyzing module TB_System_Stim
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" into library work
INFO: [VRFC 10-311] analyzing module Check
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" into library work
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch_tb
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopDeparser_t_Engine
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_remove
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_3_sec
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_3_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_3_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_dst_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_src_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_ethertype
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataMux
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopDeparser_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v" into library work
INFO: [VRFC 10-311] analyzing module S_RESETTER_line
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v" into library work
INFO: [VRFC 10-311] analyzing module S_RESETTER_lookup
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v" into library work
INFO: [VRFC 10-311] analyzing module S_RESETTER_control
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopParser_t_Engine
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ExtractShifter
INFO: [VRFC 10-311] analyzing module TopParser_t_start
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ipv4_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ipv6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_tcp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_udp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_cpu_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_na_ns_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_arp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dma_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf3_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf2_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf1_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf0_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_send_dig_to_cpu
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_drop
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_pkt_len
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_ethertype
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_digest_data_1_unused
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_ethertype
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_version
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_ihl
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_diff_serv
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_ecn
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_totalLen
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_identification
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_flags
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_fragOffset
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_ttl
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_protocol
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_version
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_traffic_class
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_flow_label
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_payload_length
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_next_header
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_hop_limit
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_seqNo
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_ackNo
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_data_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_res
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_cwr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_ece
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_urg
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_ack
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_psh
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_rst
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_syn
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_fin
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_window
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_urgentPtr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_payload_length
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_type
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_code
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_task
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_ingress_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_ethertype
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_table_id
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_type
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_code
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_router
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_solicitated
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_override
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_reserved
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_target_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_type
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_ll_length
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_hw_type
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_protocol
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_hw_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_protocol_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_opcode
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_src_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_src_ipv4_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_dst_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_dst_ipv4_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_switch_task
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_icmp6_na_ns
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_icmp6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_icmp
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_ipv4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_udp_v4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_udp_v6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_tcp_v4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_tcp_v6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_length_without_ip_header
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_cast_length
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_v4sum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_v6sum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_headerdiff
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_table_id
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_digest_data_unused
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_dma_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf3_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf2_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf1_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf0_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_send_dig_to_cpu
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_drop
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_pkt_len
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_reject
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_TupleForward
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_accept
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopParser_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v" into library work
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_EGRESS
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v" into library work
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_INGRESS
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/realmain_lookup_table_0_t.v" into library work
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/realmain_lookup_table_0_t.vp" into library work
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Wrap
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_IntTop
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Lookup
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Hash_Lookup
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_RamR1RW1
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Cam
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Update
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Hash_Update
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Randmod4
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Randmod4_Rnd
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Randmod5
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Randmod5_Rnd
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_csr
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v" into library work
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/felzy7ag20kyqn7zvny4tkasci5zqqj_1261.v" into library work
INFO: [VRFC 10-311] analyzing module felzy7ag20kyqn7zvny4tkasci5zqqj_1261
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/zdxfn79flaooijhgm_926.v" into library work
INFO: [VRFC 10-311] analyzing module zdxfn79flaooijhgm_926
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xu1hdrn6ve6krhb0ps_1240.v" into library work
INFO: [VRFC 10-311] analyzing module xu1hdrn6ve6krhb0ps_1240
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/realmain_nat64_0_t.v" into library work
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/ohzn5p6m721kfvtg07gth_1464.v" into library work
INFO: [VRFC 10-311] analyzing module ohzn5p6m721kfvtg07gth_1464
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/realmain_nat64_0_t.vp" into library work
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_wrap
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_csr
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/dp_ram.v" into library work
INFO: [VRFC 10-311] analyzing module dp_ram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/s0iqcu87b4s5z34uqbraut95u0_1430.v" into library work
INFO: [VRFC 10-311] analyzing module s0iqcu87b4s5z34uqbraut95u0_1430
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/realmain_nat64_0_t_table.v" into library work
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_table
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/wscmn54bh89j9mysvbjhj4un_1561.v" into library work
INFO: [VRFC 10-311] analyzing module wscmn54bh89j9mysvbjhj4un_1561
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/wyc7fw30w2yiqpfxumfi5_368.v" into library work
INFO: [VRFC 10-311] analyzing module wyc7fw30w2yiqpfxumfi5_368
+ true
+ mkdir -p xsim.dir/xsc
+ find -name '*.c'
+ xargs /opt/Xilinx/Vivado/2018.2/bin/xsc -mt off -v 1
Turned off multi-threading.
Running compilation flow
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc  -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/    -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/CAM.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" -DXILINX_SIMULATOR
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc  -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/    -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/LPM.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/LPM.lnx64.o" -DXILINX_SIMULATOR
./Testbench/LPM.c: In function ‘LPM_Mgt_LoadDataset’:
./Testbench/LPM.c:203:51: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
             if(cx->base | my_config_data[i][0] == (uint32_t)&dev->update_req)
                                                   ^
./Testbench/LPM.c: In function ‘LPM_Mgt_VerifyDataset’:
./Testbench/LPM.c:293:40: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
             if (my_config_tmp[i][0] == (uint32_t)&dev->update_req)
                                        ^
./Testbench/LPM.c:303:27: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
             cmd_address = (uint32_t )&dev->update_req;
                           ^
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc  -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/    -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/user.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -DXILINX_SIMULATOR
./Testbench/user.c: In function ‘register_write_control’:
./Testbench/user.c:40:5: warning: implicit declaration of function ‘SV_write_control’ [-Wimplicit-function-declaration]
     SV_write_control(&sv_addr, &sv_data);
     ^~~~~~~~~~~~~~~~
./Testbench/user.c: In function ‘register_read_control’:
./Testbench/user.c:54:5: warning: implicit declaration of function ‘SV_read_control’ [-Wimplicit-function-declaration]
     SV_read_control(&sv_addr, &sv_data);
     ^~~~~~~~~~~~~~~
./Testbench/user.c: In function ‘CAM_Init’:
./Testbench/user.c:91:76: warning: passing argument 9 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
     if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
                                                                            ^~~~~~~~~~~~~~
In file included from ./Testbench/user.c:7:0:
./Testbench/CAM.h:169:5: note: expected ‘void (*)(addr_t,  uint32_t) {aka void (*)(long long unsigned int,  unsigned int)}’ but argument is of type ‘void (*)(uint32_t,  uint32_t) {aka void (*)(unsigned int,  unsigned int)}’
 int CAM_Init_ValidateContext(
     ^~~~~~~~~~~~~~~~~~~~~~~~
./Testbench/user.c:91:92: warning: passing argument 10 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
     if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
                                                                                            ^~~~~~~~~~~~~
In file included from ./Testbench/user.c:7:0:
./Testbench/CAM.h:169:5: note: expected ‘uint32_t (*)(addr_t) {aka unsigned int (*)(long long unsigned int)}’ but argument is of type ‘uint32_t (*)(uint32_t) {aka unsigned int (*)(unsigned int)}’
 int CAM_Init_ValidateContext(
     ^~~~~~~~~~~~~~~~~~~~~~~~
./Testbench/user.c: In function ‘LPM_Init’:
./Testbench/user.c:216:67: warning: passing argument 8 of ‘LPM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
     if(LPM_Init_ValidateContext(cx,baseAddr,256,depth,k,v,shadow, register_write, register_read, &log_msg, log_level))
                                                                   ^~~~~~~~~~~~~~
In file included from ./Testbench/user.c:8:0:
./Testbench/LPM.h:134:5: note: expected ‘void (*)(addr_t,  uint32_t) {aka void (*)(long long unsigned int,  unsigned int)}’ but argument is of type ‘void (*)(uint32_t,  uint32_t) {aka void (*)(unsigned int,  unsigned int)}’
 int LPM_Init_ValidateContext(
     ^~~~~~~~~~~~~~~~~~~~~~~~
./Testbench/user.c:216:83: warning: passing argument 9 of ‘LPM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
     if(LPM_Init_ValidateContext(cx,baseAddr,256,depth,k,v,shadow, register_write, register_read, &log_msg, log_level))
                                                                                   ^~~~~~~~~~~~~
In file included from ./Testbench/user.c:8:0:
./Testbench/LPM.h:134:5: note: expected ‘uint32_t (*)(addr_t) {aka unsigned int (*)(long long unsigned int)}’ but argument is of type ‘uint32_t (*)(uint32_t) {aka unsigned int (*)(unsigned int)}’
 int LPM_Init_ValidateContext(
     ^~~~~~~~~~~~~~~~~~~~~~~~
./Testbench/user.c: In function ‘LPM_LoadDataset’:
./Testbench/user.c:254:42: warning: passing argument 2 of ‘LPM_Mgt_LoadDataset’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
     error_code = LPM_Mgt_LoadDataset(cx, filename);
                                          ^~~~~~~~
In file included from ./Testbench/user.c:8:0:
./Testbench/LPM.h:149:5: note: expected ‘char *’ but argument is of type ‘const char *’
 int LPM_Mgt_LoadDataset(LPM_CONTEXT* cx, char* filename);
     ^~~~~~~~~~~~~~~~~~~
./Testbench/user.c: In function ‘LPM_VerifyDataset’:
./Testbench/user.c:268:44: warning: passing argument 2 of ‘LPM_Mgt_VerifyDataset’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
     error_code = LPM_Mgt_VerifyDataset(cx, filename);
                                            ^~~~~~~~
In file included from ./Testbench/user.c:8:0:
./Testbench/LPM.h:150:5: note: expected ‘char *’ but argument is of type ‘const char *’
 int LPM_Mgt_VerifyDataset(LPM_CONTEXT* cx, char* filename);
     ^~~~~~~~~~~~~~~~~~~~~
Done compilation
Linking with command:
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W  -O -fPIC  -m64  -shared  -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/LPM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o"     -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel  -lrdi_xsim_systemc  -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ 

Running command : /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W  -O -fPIC  -m64  -shared  -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/LPM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o"     -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel  -lrdi_xsim_systemc  -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ 
Done linking: "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so"
+ /opt/Xilinx/Vivado/2018.2/bin/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl 
Multi-threading is on. Using 6 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module work.S_RESETTER_line
Compiling module work.S_RESETTER_lookup
Compiling module work.S_RESETTER_control
Compiling module work.TopParser_t_EngineStage_0_ErrorC...
Compiling module work.TopParser_t_EngineStage_0_Extrac...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_p_ethe...
Compiling module work.TopParser_t_start_compute_p_ethe...
Compiling module work.TopParser_t_start_compute_p_ethe...
Compiling module work.TopParser_t_start_compute_p_ethe...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_udp_...
Compiling module work.TopParser_t_start_compute_p_udp_...
Compiling module work.TopParser_t_start_compute_p_udp_...
Compiling module work.TopParser_t_start_compute_p_udp_...
Compiling module work.TopParser_t_start_compute_p_udp_...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_cpu_...
Compiling module work.TopParser_t_start_compute_p_cpu_...
Compiling module work.TopParser_t_start_compute_p_cpu_...
Compiling module work.TopParser_t_start_compute_p_cpu_...
Compiling module work.TopParser_t_start_compute_p_cpu_...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_digest...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_contro...
Compiling module work.TopParser_t_start_compute_contro...
Compiling module work.TopParser_t_start
Compiling module work.TopParser_t_reject_compute_contr...
Compiling module work.TopParser_t_reject_compute_contr...
Compiling module work.TopParser_t_reject
Compiling module work.TopParser_t_EngineStage_0_TupleF...
Compiling module work.TopParser_t_EngineStage_0
Compiling module work.TopParser_t_EngineStage_1_ErrorC...
Compiling module work.TopParser_t_accept_compute_contr...
Compiling module work.TopParser_t_accept_compute_contr...
Compiling module work.TopParser_t_accept
Compiling module work.TopParser_t_EngineStage_1
Compiling module work.TopParser_t_Engine
Compiling module work.TopParser_t
Compiling module work.TopPipe_lvl_t_setup_compute_real...
Compiling module work.TopPipe_lvl_t_setup_compute_cont...
Compiling module work.TopPipe_lvl_t_setup_compute_cont...
Compiling module work.TopPipe_lvl_t_setup
Compiling module work.TopPipe_lvl_t_EngineStage_0
Compiling module work.TopPipe_lvl_t_Engine
Compiling module work.TopPipe_lvl_t
Compiling module work.felzy7ag20kyqn7zvny4tkasci5zqqj_...
Compiling module work.dp_ram(data_width=437,addr_width...
Compiling module work.zdxfn79flaooijhgm_926
Compiling module work.dp_ram(data_width=437,addr_width...
Compiling module work.wscmn54bh89j9mysvbjhj4un_1561
Compiling module work.dp_ram(data_width=437,addr_width...
Compiling module work.ohzn5p6m721kfvtg07gth_1464
Compiling module work.dp_ram(data_width=437,addr_width...
Compiling module work.wyc7fw30w2yiqpfxumfi5_368
Compiling module work.dp_ram(data_width=437,addr_width...
Compiling module work.xu1hdrn6ve6krhb0ps_1240
Compiling module work.s0iqcu87b4s5z34uqbraut95u0_1430
Compiling module work.realmain_nat64_0_t_table
Compiling module work.realmain_nat64_0_t_wrap
Compiling module work.realmain_nat64_0_t_csr
Compiling module work.realmain_nat64_0_t
Compiling module work.TopPipe_lvl_0_t_condition_sec_4_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_4_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_4_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_4_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_4
Compiling module work.TopPipe_lvl_0_t_EngineStage_0
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_0...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_0...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_0...
Compiling module work.TopPipe_lvl_0_t_EngineStage_1
Compiling module work.TopPipe_lvl_0_t_NoAction_0_sec_c...
Compiling module work.TopPipe_lvl_0_t_NoAction_0_sec_c...
Compiling module work.TopPipe_lvl_0_t_NoAction_0_sec
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_EngineStage_2
Compiling module work.TopPipe_lvl_0_t_condition_sec_3_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_3_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_3
Compiling module work.TopPipe_lvl_0_t_EngineStage_3
Compiling module work.TopPipe_lvl_0_t_act_0_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_0_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_0_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_0_sec
Compiling module work.TopPipe_lvl_0_t_act_sec_compute_...
Compiling module work.TopPipe_lvl_0_t_act_sec_compute_...
Compiling module work.TopPipe_lvl_0_t_act_sec_compute_...
Compiling module work.TopPipe_lvl_0_t_act_sec
Compiling module work.TopPipe_lvl_0_t_EngineStage_4
Compiling module work.TopPipe_lvl_0_t_condition_sec_2_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_2_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_2_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_2_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_2
Compiling module work.TopPipe_lvl_0_t_EngineStage_5
Compiling module work.TopPipe_lvl_0_t_condition_sec_1_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_1_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_1_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_1_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_1
Compiling module work.TopPipe_lvl_0_t_EngineStage_6
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_EngineStage_7
Compiling module work.TopPipe_lvl_0_t_condition_sec_0_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_0_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_0
Compiling module work.TopPipe_lvl_0_t_EngineStage_8
Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_1_sec
Compiling module work.TopPipe_lvl_0_t_EngineStage_9
Compiling module work.TopPipe_lvl_0_t_condition_sec_co...
Compiling module work.TopPipe_lvl_0_t_condition_sec_co...
Compiling module work.TopPipe_lvl_0_t_condition_sec_co...
Compiling module work.TopPipe_lvl_0_t_condition_sec_co...
Compiling module work.TopPipe_lvl_0_t_condition_sec
Compiling module work.TopPipe_lvl_0_t_EngineStage_10
Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_2_sec
Compiling module work.TopPipe_lvl_0_t_EngineStage_11
Compiling module work.TopPipe_lvl_0_t_local_end_comput...
Compiling module work.TopPipe_lvl_0_t_local_end_comput...
Compiling module work.TopPipe_lvl_0_t_local_end
Compiling module work.TopPipe_lvl_0_t_EngineStage_12
Compiling module work.TopPipe_lvl_0_t_Engine
Compiling module work.TopPipe_lvl_0_t
Compiling module work.realmain_lookup_table_0_t_Hash_L...
Compiling module work.xpm_memory_base(MEMORY_SIZE=880,...
Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=88...
Compiling module work.realmain_lookup_table_0_t_RamR1R...
Compiling module work.realmain_lookup_table_0_t_Cam
Compiling module work.realmain_lookup_table_0_t_Lookup
Compiling module work.realmain_lookup_table_0_t_Hash_U...
Compiling module work.realmain_lookup_table_0_t_Randmo...
Compiling module work.realmain_lookup_table_0_t_Randmo...
Compiling module work.realmain_lookup_table_0_t_Randmo...
Compiling module work.realmain_lookup_table_0_t_Randmo...
Compiling module work.realmain_lookup_table_0_t_Update
Compiling module work.realmain_lookup_table_0_t_IntTop
Compiling module work.realmain_lookup_table_0_t_Wrap
Compiling module work.realmain_lookup_table_0_t_csr
Compiling module work.realmain_lookup_table_0_t
Compiling module work.TopPipe_lvl_1_t_local_start_comp...
Compiling module work.TopPipe_lvl_1_t_local_start_comp...
Compiling module work.TopPipe_lvl_1_t_local_start
Compiling module work.TopPipe_lvl_1_t_EngineStage_0
Compiling module work.TopPipe_lvl_1_t_realmain_lookup_...
Compiling module work.TopPipe_lvl_1_t_realmain_lookup_...
Compiling module work.TopPipe_lvl_1_t_realmain_lookup_...
Compiling module work.TopPipe_lvl_1_t_EngineStage_1
Compiling module work.TopPipe_lvl_1_t_realmain_do_noth...
Compiling module work.TopPipe_lvl_1_t_realmain_do_noth...
Compiling module work.TopPipe_lvl_1_t_realmain_do_noth...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_EngineStage_2
Compiling module work.TopPipe_lvl_1_t_sink_compute_con...
Compiling module work.TopPipe_lvl_1_t_sink_compute_con...
Compiling module work.TopPipe_lvl_1_t_sink
Compiling module work.TopPipe_lvl_1_t_EngineStage_3
Compiling module work.TopPipe_lvl_1_t_Engine
Compiling module work.TopPipe_lvl_1_t
Compiling module work.TopDeparser_t_EngineStage_0_Erro...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0
Compiling module work.TopDeparser_t_EngineStage_1_Erro...
Compiling module work.TopDeparser_t_act_3_sec_compute_...
Compiling module work.TopDeparser_t_act_3_sec_compute_...
Compiling module work.TopDeparser_t_act_3_sec
Compiling module work.TopDeparser_t_EngineStage_1
Compiling module work.TopDeparser_t_EngineStage_2_Erro...
Compiling module work.TopDeparser_t_emit_0_compute_con...
Compiling module work.TopDeparser_t_emit_0_compute__ST...
Compiling module work.TopDeparser_t_emit_0_compute__ST...
Compiling module work.TopDeparser_t_emit_0_compute__ST...
Compiling module work.TopDeparser_t_emit_0_compute_con...
Compiling module work.TopDeparser_t_emit_0_compute_con...
Compiling module work.TopDeparser_t_emit_0
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2
Compiling module work.TopDeparser_t_Engine
Compiling module work.TopDeparser_t
Compiling module work.xpm_cdc_sync_rst(DEST_SYNC_FF=2,...
Compiling module work.xpm_fifo_rst(COMMON_CLOCK=0)
Compiling module work.xpm_fifo_reg_bit
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=8)
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=9)
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_BRIDGER_for_realmain_nat64_0_t...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_BRIDGER_for_realmain_lookup_ta...
Compiling module work.S_PROTOCOL_ADAPTER_INGRESS
Compiling module work.S_PROTOCOL_ADAPTER_EGRESS
Compiling module work.xpm_fifo_rst_default
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_TopParser
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_S_SYNCER_for_S_SYNC...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=7)
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_S_SYNCER_for_S_SYNC...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_S_SYNCER_for_TopDep...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_TopDeparser
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for__OUT_
Compiling module work.S_CONTROLLER_SimpleSumeSwitch
Compiling module work.SimpleSumeSwitch
Compiling module work.TB_System_Stim
Compiling module work.Check
Compiling module work.SimpleSumeSwitch_tb
Compiling module work.glbl
Built simulation snapshot work.SimpleSumeSwitch_tb#work.glbl

****** Webtalk v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Wed Jul 24 22:30:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2018.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Wed Jul 24 22:30:46 2019...
+ /opt/Xilinx/Vivado/2018.2/bin/xsim --runall SimpleSumeSwitch_tb#work.glbl

****** xsim v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsim_script.tcl
# xsim {work.SimpleSumeSwitch_tb#work.glbl} -autoloadwcfg -runall
Vivado Simulator 2018.2
Time resolution is 1 ps
run -all
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_lookup_table_0.realmain_lookup_table_0_t_Wrap_inst.realmain_lookup_table_0_t_IntTop_inst.realmain_lookup_table_0_t_Lookup_inst.realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_959  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_lookup_table_0.realmain_lookup_table_0_t_Wrap_inst.realmain_lookup_table_0_t_IntTop_inst.realmain_lookup_table_0_t_Lookup_inst.realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_959  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_lookup_table_0.realmain_lookup_table_0_t_Wrap_inst.realmain_lookup_table_0_t_IntTop_inst.realmain_lookup_table_0_t_Lookup_inst.realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_959  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_lookup_table_0.realmain_lookup_table_0_t_Wrap_inst.realmain_lookup_table_0_t_IntTop_inst.realmain_lookup_table_0_t_Lookup_inst.realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_959  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_lookup_table_0.realmain_lookup_table_0_t_Wrap_inst.realmain_lookup_table_0_t_IntTop_inst.realmain_lookup_table_0_t_Lookup_inst.realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_959  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_realmain_nat64_0_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1701  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1791  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.ikk7xvkczz6hc5bqx1yyxox_1328.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/ikk7xvkczz6hc5bqx1yyxox_1328/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1880  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.mtcmi2i9x8c4842a2c8gm6gzua6tzqx_1427.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/mtcmi2i9x8c4842a2c8gm6gzua6tzqx_1427/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1910  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.dn7sgvg0a7r79g2x36sc4a1ooqerux_1642.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/dn7sgvg0a7r79g2x36sc4a1ooqerux_1642/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1974  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.izud4gd1d160iij6mmekef_1929.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/izud4gd1d160iij6mmekef_1929/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2058  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.a917rerwfl39sab53so7tmd_2489.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/a917rerwfl39sab53so7tmd_2489/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1880  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v74gbeb1kxu784r2t2w_1141.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v74gbeb1kxu784r2t2w_1141/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1910  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.ahmskmn84l9nmc9pscqr9l5j_781.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ahmskmn84l9nmc9pscqr9l5j_781/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2239  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.efgbgqrrhgyjeez7w7m_811.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/efgbgqrrhgyjeez7w7m_811/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2323  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.ot83udxs7wlxf6d8_540.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ot83udxs7wlxf6d8_540/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2407  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.rm9q8nwkrb2rbst4vcii65tahk7_386.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rm9q8nwkrb2rbst4vcii65tahk7_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1974  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.j1acjq0w6bqcl9v8qixtqe8ykmgth_965.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/j1acjq0w6bqcl9v8qixtqe8ykmgth_965/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2058  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.doy4j98upj1nv09961ra140yo_1195.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/doy4j98upj1nv09961ra140yo_1195/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2659  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.medxsptsgaw2sjnvjp8ux4cghgd4_2024.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/medxsptsgaw2sjnvjp8ux4cghgd4_2024/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1880  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.lzte0eo9a3kl4ev412wp3e5ah8e0mc1k_604.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lzte0eo9a3kl4ev412wp3e5ah8e0mc1k_604/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1910  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.r7ixo67nae8gi90ae6vhnw4_2358.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/r7ixo67nae8gi90ae6vhnw4_2358/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2846  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.fyfsqfrb1w6a5phfz5fo97fxfn_499.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/fyfsqfrb1w6a5phfz5fo97fxfn_499/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2407  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.dym958psdxlbycqhv60wq_1450.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dym958psdxlbycqhv60wq_1450/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_3014  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.zn5pspfabsp5cmugfdq0ogt707_1621.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/zn5pspfabsp5cmugfdq0ogt707_1621/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2239  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.trk6rgwlm382z5nbvbxs_2205.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/trk6rgwlm382z5nbvbxs_2205/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1974  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.wmuk5lanzwi3leq6k0sp1kd_130.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/wmuk5lanzwi3leq6k0sp1kd_130/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2323  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.a7pzvb132e3nkepkrt502_2348.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/a7pzvb132e3nkepkrt502_2348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_3350  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.jjztieel31pl5gtgbw0c3rzoorhul_654.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jjztieel31pl5gtgbw0c3rzoorhul_654/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2058  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.vqw36o0koj93yepe7xh0_1616.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vqw36o0koj93yepe7xh0_1616/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2659  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.gxo6yfw8cnz0rref3bttyb_2668.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/gxo6yfw8cnz0rref3bttyb_2668/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1880  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.qwxngizo3v6lu7xqm31e0d_1838.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/qwxngizo3v6lu7xqm31e0d_1838/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1910  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.v4t2r7uggsgrp5mdvr88rypmha5mu_2577.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/v4t2r7uggsgrp5mdvr88rypmha5mu_2577/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2846  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.l4v4vbvggvumuehgz9_451.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/l4v4vbvggvumuehgz9_451/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2407  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.ej0pyoipvk3xtwdb4y30pzrisecagoha_1304.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/ej0pyoipvk3xtwdb4y30pzrisecagoha_1304/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_3014  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.g8yolsubu5o96w6e2g6op_421.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/g8yolsubu5o96w6e2g6op_421/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2239  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.dqa1lxvu8juyyqns1wq95vy30zs_2320.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/dqa1lxvu8juyyqns1wq95vy30zs_2320/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4045  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.uq242lnijpfm7c2ogvqe3vxdv50jqh_1967.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/uq242lnijpfm7c2ogvqe3vxdv50jqh_1967/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1974  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.xf2x3vxeysaddqajmgqb5nei_135.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/xf2x3vxeysaddqajmgqb5nei_135/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2323  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.yp6hvicw9eyj1yd9t9_419.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/yp6hvicw9eyj1yd9t9_419/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4297  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.sviwzaomxavc6mmbsopsz2_1593.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/sviwzaomxavc6mmbsopsz2_1593/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2058  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.drzxxrpdhjtnk7ppslqvapfgu3f5n_1961.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/drzxxrpdhjtnk7ppslqvapfgu3f5n_1961/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2659  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.m6xrmpom67sh250zfs8vw237x9v_2215.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/m6xrmpom67sh250zfs8vw237x9v_2215/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1880  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.tlsnp64xdixw8gqwv_1286.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/tlsnp64xdixw8gqwv_1286/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1910  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.abo03a0f18t9i682kyo5i357v5jll82v_2207.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/abo03a0f18t9i682kyo5i357v5jll82v_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2239  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.jnm5md0kge033tpwdk_2284.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/jnm5md0kge033tpwdk_2284/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2323  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.t2fy08h6k9szel5isi1z2azayrmciu7l_260.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/t2fy08h6k9szel5isi1z2azayrmciu7l_260/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2407  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.s5fhd18wj16jf0ic8n5ekgt9_699.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/s5fhd18wj16jf0ic8n5ekgt9_699/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1974  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.rdrqc4oexjpjkij4gz0ty5q83svjx17_173.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/rdrqc4oexjpjkij4gz0ty5q83svjx17_173/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2058  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.nhqfqdu2nw9n2zf5x4foasgkpkqne_48.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/nhqfqdu2nw9n2zf5x4foasgkpkqne_48/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2659  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.dwktdn25r8a5cwsxrds44owsjusigh_1860.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/dwktdn25r8a5cwsxrds44owsjusigh_1860/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5149  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.knkpkeqbzoq39frympa8_2613.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/knkpkeqbzoq39frympa8_2613/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1910  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.wrt2lulxu3lrgtbupmezgtieolfhx7_1918.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/wrt2lulxu3lrgtbupmezgtieolfhx7_1918/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2407  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.kxcqrmmjc1l7temr_2536.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/kxcqrmmjc1l7temr_2536/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1974  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv
[SW] LPM_Init() - start
[SW] LPM_Init() - done
[SW] LPM_LoadDataset() - start
[SW] LPM_LoadDataset() failed with error code = 12
FATAL_ERROR: Vivado Simulator kernel has encounted an exception from DPI C function: LPM_VerifyDataset(). Please correct.
Time: 2016466 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/LPM_VerifyDataset
  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv

HDL Line: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv:432
[SW] LPM_VerifyDataset() - start
exit
INFO: [Common 17-206] Exiting xsim at Wed Jul 24 22:30:56 2019...
+ grep ^expected /home/nico/master-thesis/netpfga/log/compile-2019-07-24-222942-nat64apply-no-arp-6.2
+ sed -e s/.*= <// -e s/.*= (//
+ expected_line=
+ grep ^actual /home/nico/master-thesis/netpfga/log/compile-2019-07-24-222942-nat64apply-no-arp-6.2
+ sed -e s/.*= <// -e s/.*= (//
+ actual_line=
+ [  !=  ]
+ date
Mit Jul 24 22:30:56 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
+ make config_writes
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata
Traceback (most recent call last):
  File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py", line 104, in <module>
    main()
  File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py", line 96, in main
    dic = parse_config_writes(args.filename)
  File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py", line 47, in parse_config_writes
    with open(filename) as f:
IOError: [Errno 2] No such file or directory: 'nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt'
Makefile:56: recipe for target 'config_writes' failed
make: *** [config_writes] Error 1
