diff --git a/doc/plan.org b/doc/plan.org index 728e7e3..83b944b 100644 --- a/doc/plan.org +++ b/doc/plan.org @@ -2914,7 +2914,7 @@ actual < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000040010000 > < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 > -***** TODO Testing packets: does not arrive on nf0 +***** DONE Testing packets: does not arrive on nf0 with ping6 4: nf0: mtu 1500 qdisc fq_codel state UP group default qlen 1000 link/ether 02:53:55:4d:45:00 brd ff:ff:ff:ff:ff:ff inet6 fe80::53:55ff:fe4d:4500/64 scope link @@ -2942,7 +2942,17 @@ listening on nf1, link-type EN10MB (Ethernet), capture size 262144 bytes 19:28:37.725181 IP6 2001:db8::1 > ff02::1:ff00:2: ICMP6, neighbor solicitation, who has 2001:db8::2, length 32 19:28:38.749195 IP6 2001:db8::1 > ff02::1:ff00:2: ICMP6, neighbor solicitation, who has 2001:db8::2, length 32 +***** TODO Testing packets with send_packet.py: nothing arrives +root@rainbow:/home/nico/master-thesis/bin# python send_packet.py nf1 +. +Sent 1 packets. +root@rainbow:/home/nico/master-thesis/bin# python send_packet.py nf0 +. +Sent 1 packets. +root@rainbow:/home/nico/master-thesis/bin# +-> only shows up on the interface that we send, not on nf0 if sending + on nf1 *** TODO Create either HDL or PX for supporting payload checksum https://github.com/NetFPGA/P4-NetFPGA-public/issues/13 https://github.com/NetFPGA/P4-NetFPGA-public/issues/13#issuecomment-490431016 @@ -3718,6 +3728,48 @@ Fragmented ICMP/ICMPv6 packets will not be translated by IP/ICMP translators. **** TODO Security issue: not checking checksums before - Could be implemented +** Log various +*** 2019-06-06 +No device seen after loading modules after reboot - netfpga. +Trying to reprogram + +#+BEGIN_CENTER ++ xsct /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl -tclargs minip4.bit +rlwrap: warning: your $TERM is 'screen' but rlwrap couldn't find it in the terminfo database. Expect some problems. +RUN loading image file. +minip4.bit +attempting to launch hw_server + +****** Xilinx hw_server v2018.2 + **** Build date : Jun 14 2018-20:18:37 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +INFO: hw_server application started +INFO: Use Ctrl-C to exit hw_server application + +INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121 + +100% 11MB 1.7MB/s 00:06 + ++ bash /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/pci_rescan_run.sh +Check programming FPGA or Reboot machine ! ++ rmmod sume_riffa +rmmod: ERROR: Module sume_riffa is not currently loaded ++ modprobe sume_riffa ++ ifconfig nf0 up +nf0: ERROR while getting interface flags: No such device ++ ifconfig nf1 up +nf1: ERROR while getting interface flags: No such device ++ ifconfig nf2 up +nf2: ERROR while getting interface flags: No such device ++ ifconfig nf3 up +nf3: ERROR while getting interface flags: No such device ++ bash config_writes.sh +root@rainbow:~/master-thesis/netpfga/minip4/simple_sume_switch/bitfiles# + +#+END_CENTER + + ** References / Follow up *** RFC 791 IPv4 https://tools.ietf.org/html/rfc791 *** RFC 792 ICMP https://tools.ietf.org/html/rfc792 diff --git a/netpfga/do-all-steps.sh b/netpfga/do-all-steps.sh index 353a6fc..e1cfc52 100755 --- a/netpfga/do-all-steps.sh +++ b/netpfga/do-all-steps.sh @@ -7,6 +7,8 @@ echo "First source all variables and THEN run this script" read something + + # Step 1..3: create code # Step 4 cd $P4_PROJECT_DIR && make @@ -35,8 +37,12 @@ cd $NF_DESIGN_DIR/test/sim_switch_default && make # Step 9 cd $SUME_FOLDER && ./tools/scripts/nf_test.py sim --major switch --minor default -# Step 10 -cd $NF_DESIGN_DIR && make +# Step 10: long compile step +if [ "$something" = no ]; then + : +else + cd $NF_DESIGN_DIR && make +fi # Step 11: (nothing to be done)