diff --git a/doc/plan.org b/doc/plan.org index 0a6f358..1b10431 100644 --- a/doc/plan.org +++ b/doc/plan.org @@ -5944,7 +5944,138 @@ Opening simple_sume_switch Implementation design ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open Vivado% #+END_CENTER -**** TODO try8: use new script generating different sequences/objects in gen_testdata +**** DONE try8: use new script generating different sequences/objects in gen_testdata + CLOSED: [2019-07-21 Sun 19:00] +output around gen_testdata: + +#+BEGIN_CENTER +./gen_testdata.py +Applying pkt on nf0 at 1: +Applying pkt on nf1 at 2: +Applying pkt on nf2 at 3: +Applying pkt on nf3 at 4: +nf0_applied times: [1] +nf1_applied times: [2] +nf2_applied times: [3] +nf3_applied times: [4] + +nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ cat /home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt +: (00000020, 00000001) +: (00000020, 00000000) +nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ ls -alh /home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt +-rw-rw-r-- 1 nico nico 70 Jul 21 16:44 /home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt +nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ date +Son Jul 21 16:48:08 CEST 2019 + +#+END_CENTER +**** TODO try9: generated files missing + +#+BEGIN_CENTER +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'. +WARNING: [IP_Flow 19-3664] IP 'bd_7ad4_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-14144-nsg-System/coregen/bd_7ad4_xpcs_0_1/elaborate/configure_gt.tcl'. Please regenerate to continue. +WARNING: [IP_Flow 19-3664] IP 'bd_a1aa_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-14144-nsg-System/coregen/bd_a1aa_xpcs_0_2/elaborate/configure_gt.tcl'. Please regenerate to continue. + +#+END_CENTER + +One (maybe critical) error message on the way + +#+BEGIN_CENTER +ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details +#+END_CENTER + +#+BEGIN_CENTER +WARNING: [Synth 8-689] width (12) of port connection 'control_S_AXI_ARADDR' does not match port width (8) of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:199] +ERROR: [Synth 8-448] named port connection 'tuple_out_sume_metadata_VALID' does not exist for instance 'SimpleSumeSwitch_inst' of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:218] +ERROR: [Synth 8-448] named port connection 'tuple_out_sume_metadata_DATA' does not exist for instance 'SimpleSumeSwitch_inst' of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:219] +ERROR: [Synth 8-6156] failed synthesizing module 'nf_sume_sdnet' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:44] +ERROR: [Synth 8-6156] failed synthesizing module 'nf_sume_sdnet_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/synth/nf_sume_sdnet_ip.v:57] +ERROR: [Synth 8-6156] failed synthesizing module 'nf_datapath' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:44] +ERROR: [Synth 8-6156] failed synthesizing module 'top' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:43] + +#+END_CENTER + +Finding all errors/warnings: + +#+BEGIN_CENTER +[19:05] line:log% grep -i -e error -e warn compile-2019-07-21-164256 | wc -l +328 +[19:05] line:log% grep -i -e error compile-2019-07-21-164256 | wc -l +68 + +#+END_CENTER + +Log from beginning to end + +#+BEGIN_CENTER +/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata +orig dic: OrderedDict([(0, ('00000020', '00000001')), (1, ('00000020', '00000000'))]) +new dic: OrderedDict() + +WARNING: [IP_Flow 19-3656] If you move the project, the path for +repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become +invalid. A better location for the repository would be in a path +adjacent to the project. (Current project location is +'/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.) + +WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/wrapper/changeEndian.v'. +WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.h'. +WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp'. + +INFO: [IP_Flow 19-2181] Payment Required is not set for this core. +INFO: [IP_Flow 19-2187] The Product Guide file is missing. + +WARNING: command 'get_user_parameter' will be removed in the 2015.3 +release, use 'get_user_parameters' instead + +echo 16028002 >> rom_data.txt +echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt +grep: ../../../RELEASE_NOTES: No such file or directory +echo 00000204 >> rom_data.txt + +## create_root_design "" +CRITICAL WARNING: [BD 41-737] Cannot set the parameter TRANSLATION_MODE on /axi_interconnect_0. It is read-only. +### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 + +update_compile_order: Time (s): cpu = 00:00:21 ; elapsed = 00:00:11 . Memory (MB): peak = 2029.402 ; gain = 8.012 ; free physical = 9120 ; free virtual = 14551 +loading libsume.. +Traceback (most recent call last): + File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py", line 42, in + import config_writes + File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py", line 7 + + ^ +IndentationError: expected an indented block + while executing +"exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py" + invoked from within +"set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]" + (file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 177) +INFO: [Common 17-206] Exiting Vivado at Sun Jul 21 16:46:22 2019... +Makefile:120: recipe for target 'sim' failed +make: *** [sim] Error 1 +make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test' + + +#+END_CENTER + +#+BEGIN_CENTER +nico@nsg-System:~$ cat ~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py + +from NFTest import * + +NUM_WRITES = 0 + +def config_tables(): + +#+END_CENTER +**** fact9: generated python script has a syntax error +#+BEGIN_CENTER + ~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py +#+END_CENTER + + *** TODO Further notes P4/master thesis - Cannot easily run P4 on notebook - changes to the system very invasive @@ -5963,6 +6094,21 @@ control_sub_m02_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-proj nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ less /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log: No such file or directory + - A script/makefile generates a python script that generates a shell + script and later then a python script. If there is a mistake in + generating the first python script (syntax ok, but content is + not correct) then a much later stage of the compile process will + fail due to a syntax error in the third generated + script. However that syntax error is not fatal in the build + process and thus can only be seen with careful analysis of the + logfile, which is around 700 KiB or 10k lines per compile + process and contains 328 lines matching "error" and + "warning". + + Most of the error and warning messages seem to be non-critical + (even if saying they are). Then there are a variety of INFO + messages that actually constitute ERROR messages, but are not + flagged as such nor do they cause the build process to abort. ** The NetPFGA saga Problems encountered: