diff --git a/doc/plan.org b/doc/plan.org index fd4addd..6d33ffb 100644 --- a/doc/plan.org +++ b/doc/plan.org @@ -6099,7 +6099,156 @@ nico@nsg-System:~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switc #+END_CENTER *** DONE 2019-07-23: check: switch_calc compiles CLOSED: [2019-07-23 Tue 08:59] +*** TODO Reset project to plain send-to-port1 code, no includes *** TODO 2019-07-23: merge/migrate code into switch calc until it breaks +*** TODO 2019-07-23: install xilinx & co. to eth2.nico.ungleich.cloud -> 2nd compiler [MANUAL] +**** DONE Install SDNET via xsetup + CLOSED: [2019-07-23 Tue 11:03] +**** DONE Not enough space for installing vivado (40g+ required) + CLOSED: [2019-07-23 Tue 11:16] +#+BEGIN_CENTER +root@ESPRIMO-P956:~# mount /dev/sdb3 /mnt/ +root@ESPRIMO-P956:~# df -h +Filesystem Size Used Avail Use% Mounted on +udev 7.0G 0 7.0G 0% /dev +tmpfs 1.4G 146M 1.3G 11% /run +/dev/sda5 100G 62G 34G 65% / +tmpfs 7.0G 192K 7.0G 1% /dev/shm +tmpfs 5.0M 4.0K 5.0M 1% /run/lock +tmpfs 7.0G 0 7.0G 0% /sys/fs/cgroup +/dev/sda2 96M 29M 68M 30% /boot/efi +tmpfs 1.4G 36K 1.4G 1% /run/user/108 +tmpfs 1.4G 0 1.4G 0% /run/user/1000 +tmpfs 1.4G 0 1.4G 0% /run/user/1001 +/dev/sdb3 666G 122G 510G 20% /mnt + +#+END_CENTER + +Need to move install files to different partition + +**** DONE Install Vivado via xsetup + CLOSED: [2019-07-23 Tue 11:53] +**** DONE Install netpfga-live repo: mkdir + git clone + CLOSED: [2019-07-23 Tue 11:20] + - git@github.com:NetFPGA/P4-NetFPGA-live.git to ~/project/P4-NetFPGA + +#+BEGIN_CENTER +nico@ESPRIMO-P956:~$ mkdir ~/projects +nico@ESPRIMO-P956:~$ cd ~/projects/ +nico@ESPRIMO-P956:~/projects$ git clone git@github.com:NetFPGA/P4-NetFPGA-live.git +Cloning into 'P4-NetFPGA-live'... +The authenticity of host 'github.com (140.82.118.4)' can't be established. +RSA key fingerprint is SHA256:nThbg6kXUpJWGl7E1IGOCspRomTxdCARLviKw6E5SY8. +Are you sure you want to continue connecting (yes/no)? yes +Warning: Permanently added 'github.com,140.82.118.4' (RSA) to the list of known hosts. +remote: Enumerating objects: 1822, done. +remote: Total 1822 (delta 0), reused 0 (delta 0), pack-reused 1822 +Receiving objects: 100% (1822/1822), 6.00 MiB | 3.20 MiB/s, done. +Resolving deltas: 100% (970/970), done. +Checking connectivity... done. +nico@ESPRIMO-P956:~/projects$ + +#+END_CENTER +**** DONE Change ~/projects/P4-NetFPGA/tools/settings.sh for minip4 + CLOSED: [2019-07-23 Tue 11:59] +#+BEGIN_CENTER + +#export P4_PROJECT_NAME=switch_calc +export P4_PROJECT_NAME=minip4 +export NF_PROJECT_NAME=simple_sume_switch +export SUME_FOLDER=${HOME}/projects/P4-NetFPGA +export SUME_SDNET=${SUME_FOLDER}/contrib-projects/sume-sdnet-switch +export P4_PROJECT_DIR=${SUME_SDNET}/projects/${P4_PROJECT_NAME} +export LD_LIBRARY_PATH=${SUME_SDNET}/sw/sume:${LD_LIBRARY_PATH} +export PROJECTS=${SUME_FOLDER}/projects +export DEV_PROJECTS=${SUME_FOLDER}/contrib-projects +export IP_FOLDER=${SUME_FOLDER}/lib/hw/std/cores +export CONTRIB_IP_FOLDER=${SUME_FOLDER}/lib/hw/contrib/cores +export CONSTRAINTS=${SUME_FOLDER}/lib/hw/std/constraints +export XILINX_IP_FOLDER=${SUME_FOLDER}/lib/hw/xilinx/cores +export NF_DESIGN_DIR=${P4_PROJECT_DIR}/${NF_PROJECT_NAME} +export NF_WORK_DIR=/tmp/${USER} +export PYTHONPATH=.:${SUME_SDNET}/bin:${SUME_FOLDER}/tools/scripts/:${NF_DESIGN_DIR}/lib/Python:${SUME_FOLDER}/tools/scripts/NFTest +export DRIVER_NAME=sume_riffa_v1_0_0 +export DRIVER_FOLDER=${SUME_FOLDER}/lib/sw/std/driver/${DRIVER_NAME} +export APPS_FOLDER=${SUME_FOLDER}/lib/sw/std/apps/${DRIVER_NAME} +export HWTESTLIB_FOLDER=${SUME_FOLDER}/lib/sw/std/hwtestlib +#+END_CENTER +**** DONE Allow password less sudo + CLOSED: [2019-07-23 Tue 11:17] + ⚡ root  root cat /etc/sudoers.d/nico +nico ALL=(ALL) NOPASSWD: ALL +**** DONE Install git + CLOSED: [2019-07-23 Tue 11:07] +**** Install python-scapy +**** DONE Install master thesis repo: git clone git@gitlab.ethz.ch:nicosc/master-thesis.git + CLOSED: [2019-07-23 Tue 11:20] +**** DONE Setup path sourcing in ~/.bashrc + CLOSED: [2019-07-23 Tue 12:05] +#+BEGIN_CENTER +nico@ESPRIMO-P956:~$ tail -n 2 .bashrc +. ~/master-thesis/netpfga/bashinit +#+END_CENTER + +**** DONE Setup bind mount / links / paths for compiling minip4 + CLOSED: [2019-07-23 Tue 12:05] +nico@ESPRIMO-P956:~/projects/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects$ ln -s ~/master-thesis/netpfga/minip4/nico@ESPRIMO-P956:~/projects/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects$ +**** DONE Compile sume library + CLOSED: [2019-07-23 Tue 12:07] +#+BEGIN_CENTER +cd $SUME_FOLDER/lib/hw/xilinx/cores/tcam_v1_1_0/ && make update && make +cd $SUME_FOLDER/lib/hw/xilinx/cores/cam_v1_1_0/ && make update && make +cd $SUME_SDNET/sw/sume && make +cd $SUME_FOLDER && make +#+END_CENTER +**** TODO Install build deps +#+BEGIN_CENTER + +sudo apt-get -y install python-matplotlib +sudo apt-get -y install python-pip +sudo pip install ascii_graph +sudo apt-get install -y libc6-dev-i386 +sudo apt install -y libc6-dev + +#+END_CENTER +*** 2019-07-23: compiling on ISG computer +**** DONE try1: "souce" files: / missing sumereg + CLOSED: [2019-07-23 Tue 12:14] + +#+BEGIN_CENTER +cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API +cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API +cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o libcam.so libcam.o CAM.o -lsumereg +/usr/bin/ld: cannot find -lsumereg +collect2: error: ld returned 1 exit status +Makefile:52: recipe for target 'libcam' failed +make[1]: *** [libcam] Error 1 +make[1]: Leaving directory '/home/nico/master-thesis/netpfga/minip4/sw/CLI' +ERROR: could not compile libcam souce files + +#+END_CENTER +**** TODO try2: includes missing +#+BEGIN_CENTER +/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/CAM.c" -O1 -o "/home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" -DXILINX_SIMULATOR +In file included from /usr/include/stdio.h:27:0, + from ./Testbench/CAM.c:30: +/usr/include/features.h:367:25: fatal error: sys/cdefs.h: No such file or directory + # include + ^ +compilation terminated. +ERROR: [XSIM 43-3409] Failed to compile generated C file ./Testbench/CAM.c. +ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting... +nico@ESPRIMO-P956:~$ + + + +nico@nsg-System:~/master-thesis/netpfga/log$ dpkg -S /usr/include/sys/cdefs.h +libc6-dev-i386: /usr/include/sys/cdefs.h + + +#+END_CENTER + + *** the config writes madness - step9 (sume simulation, the longest step) in the process calls "config_writes.py" @@ -6119,7 +6268,6 @@ nico@nsg-System:~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switc responsible for writing the content, which in turn uses axi4_lite_master_write_request_control - **** More notes for the config writes madness xsc and xelab are described in https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=2ahUKEwiGqfiAmcjjAhXEC-wKHW3_C78QFjABegQIBBAC&url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fsw_manuals%2Fxilinx2014_4%2Fug900-vivado-logic-simulation.pdf&usg=AOvVaw1jgWuqcjeph5qOplb4eJMq diff --git a/netpfga/do-all-steps.sh b/netpfga/do-all-steps.sh index 202da83..6f6448a 100755 --- a/netpfga/do-all-steps.sh +++ b/netpfga/do-all-steps.sh @@ -7,7 +7,7 @@ echo "First source all variables and THEN run this script" read something LOG=~/master-thesis/netpfga/log/compile-$(date +%F-%H%M%S) -exec | tee "$LOG" +exec > "$LOG" exec 2>&1 # Step 1..3: create code diff --git a/p4src/minip4_solution.p4 b/p4src/minip4_solution.p4 deleted file mode 120000 index b9afb80..0000000 --- a/p4src/minip4_solution.p4 +++ /dev/null @@ -1 +0,0 @@ -minip4_solution-mirror.p4 \ No newline at end of file diff --git a/p4src/minip4_solution.p4 b/p4src/minip4_solution.p4 new file mode 100644 index 0000000..6c512b3 --- /dev/null +++ b/p4src/minip4_solution.p4 @@ -0,0 +1,133 @@ +#include +#include +#include "headers.p4" + +/******************************************************************************** + * Header + */ + +typedef bit<48> EthAddr_t; +header Ethernet_h { + EthAddr_t dstAddr; + EthAddr_t srcAddr; + bit<16> etherType; +} + +struct Parsed_packet { + Ethernet_h ethernet; +} + +// user defined metadata: can be used to share information between +// TopParser, TopPipe, and TopDeparser +struct user_metadata_t { + bit<8> unused; +} + +// digest_data, MUST be 256 bits -- what is this used for? +struct digest_data_t { + bit<256> unused; +} + + +/******************************************************************************** + * Parser + */ + +@Xilinx_MaxPacketRegion(1024) +parser TopParser(packet_in b, + out Parsed_packet p, + out user_metadata_t user_metadata, + out digest_data_t digest_data, + inout sume_metadata_t sume_metadata) { + state start { + b.extract(p.ethernet); + user_metadata.unused = 0; + digest_data.unused = 0; + + transition accept; + } +} + +/******************************************************************************** + * Main + */ +control TopPipe(inout Parsed_packet p, + inout user_metadata_t user_metadata, + inout digest_data_t digest_data, + inout sume_metadata_t sume_metadata) { + + action swap_eth_addresses() { + EthAddr_t temp = p.ethernet.dstAddr; + p.ethernet.dstAddr = p.ethernet.srcAddr; + p.ethernet.srcAddr = temp; + + /* set egress port */ + sume_metadata.dst_port = sume_metadata.src_port; + } + + action send_to_port1() { + sume_metadata.dst_port = 1; + } + + action send_to_all_ports() { + /* Taken from commands.txt of the "int" project: + table_cam_add_entry forward set_output_port 0xffffffffffff => 0b01010101 + + python convert: + >>> 0b01010101 + 85 + + */ + sume_metadata.dst_port = 85; + } + + action do_nothing() { + EthAddr_t temp = p.ethernet.dstAddr; + } + + table lookup_table { + key = { + p.ethernet.dstAddr: exact; + } + + actions = { + swap_eth_addresses; + do_nothing; + send_to_port1; + send_to_all_ports; + } + size = 64; +// default_action = swap_eth_addresses; // test_mirror(): in gen_testdata.py + default_action = send_to_port1; // test_port1() +// default_action = send_to_all_ports; // test_allports(): + } + + apply { + lookup_table.apply(); + } +} + +/******************************************************************************** + * Deparser + */ + +@Xilinx_MaxPacketRegion(1024) +control TopDeparser(packet_out b, + in Parsed_packet p, + in user_metadata_t user_metadata, + inout digest_data_t digest_data, + inout sume_metadata_t sume_metadata) { + apply { + b.emit(p.ethernet); + } +} + +/******************************************************************************** + * Switch + */ + +SimpleSumeSwitch( + TopParser(), + TopPipe(), + TopDeparser() +) main;