From 71404d9a586ebfc698c868216d06d0b1913aeaf7 Mon Sep 17 00:00:00 2001 From: Nico Schottelius Date: Sun, 21 Jul 2019 14:52:43 +0200 Subject: [PATCH] ++notes --- doc/plan.org | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/doc/plan.org b/doc/plan.org index 1a5fc2f..b88437f 100644 --- a/doc/plan.org +++ b/doc/plan.org @@ -5897,6 +5897,35 @@ nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/project 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001040000 #+END_CENTER +**** TODO try6: debug the compile process further / find out gen_testdata use +#+BEGIN_CENTER +nico@nsg-System:~/master-thesis/netpfga/minip4$ grep gen_testdata -r . +./testdata/Makefile: ./gen_testdata.py +./src/minip4_solution-mirror.p4:// default_action = swap_eth_addresses; // test_mirror(): in gen_testdata.py +nico@nsg-System:~/master-thesis/netpfga/minip4$ + +nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ ./gen_testdata.py +apply packet on nf0 at 1: > +exppkt packet on nf0: > +apply packet on nf1 at 3: > +exppkt packet on nf0: > +nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ + +#+END_CENTER + +So why did the above compile output say 3/3? like this: + +#+BEGIN_CENTER +./gen_testdata.py +nf0_applied times: [3] +nf1_applied times: [3] +nf2_applied times: [] +nf3_applied times: [] +#+END_CENTER + +Should that not be [1] and then [3]? +--------> same packet / object!!!!!!!!!! + *** TODO Further notes P4/master thesis - Cannot easily run P4 on notebook - changes to the system very @@ -5910,7 +5939,7 @@ nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/project Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/runme.log nico@nsg-System:~/master-thesis/netpfga/log$ ls -alh /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/runme.log ls: cannot access '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/runme.log': No such file or directory - + - even "short" compile runs taking 30m+ ** The NetPFGA saga Problems encountered: