diff --git a/doc/plan.org b/doc/plan.org index f69435e..fa9c13d 100644 --- a/doc/plan.org +++ b/doc/plan.org @@ -424,12 +424,15 @@ | 2019-07-11 | | | | | Meeting Laurent | | | | | | -| | - Delta diff in P4 from v4 -> v6: checksum working | | +| | - Delta diff in P4 from v4 -> v6: checksum working, off by one error | | +| | -> assume overflow | | +| | -> very likely | | +| | | | | | - Investigating why NDP doesn't work | | | | | | -| | - compile to netpfga: silent errors | | -| | - netpfga: icmp6/ndp might not work | | -| | | | +| | - compile to netpfga: silent errors | | +| | - netpfga: icmp6/ndp might not work => shifting back to controller | | +| | - network card | | | | | | | | Integrated org-documentation into latex / export working | | | | https://bastibe.de/2014-09-23-org-cite.html | | @@ -4998,7 +5001,6 @@ Using --> gateway not reachable! -> need to verify neighbor discovery *** 2019-07-11: again silent errors - End of log file #+BEGIN_CENTER @@ -5057,6 +5059,101 @@ nico@nsg-System:~/master-thesis/netpfga$ date Don Jul 11 10:54:22 CEST 2019 #+END_CENTER + +*** 2019-07-11: repair icmp6 in bmv2 + - correctly re-imported checksumming +*** 2019-07-13: get small netpfga working again +**** current error + +#+BEGIN_CENTER +cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py +16 + +mv -f id_rom16x32.coe ../hw/create_ip/ +mv -f rom_data.txt ../hw/create_ip/ +if test -d project; then\ + echo "export simple_sume_switch project to SDK"; \ + vivado -mode tcl -source tcl/export_hardware.tcl -tclargs simple_sume_switch;\ +else \ + echo "Project simple_sume_switch does not exist.";\ + echo "Please run \"make project\" to create and build the project first";\ +fi;\ + +export simple_sume_switch project to SDK + + ****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source tcl/export_hardware.tcl +# set design [lindex $argv 0] +# puts "\nOpening $design XPR project\n" + +Opening simple_sume_switch XPR project + +# open_project project/$design.xpr +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/ip_repo'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'. +WARNING: [IP_Flow 19-3664] IP 'bd_7ad4_xpcs_0' generated file not found '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/.Xil/Vivado-24530-nsg-System/coregen/bd_7ad4_xpcs_0_1/elaborate/configure_gt.tcl'. Please regenerate to continue. +WARNING: [IP_Flow 19-3664] IP 'bd_a1aa_xpcs_0' generated file not found '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/.Xil/Vivado-24530-nsg-System/coregen/bd_a1aa_xpcs_0_2/elaborate/configure_gt.tcl'. Please regenerate to continue. +open_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1364.332 ; gain = 187.594 ; free physical = 10415 ; free virtual = 15693 +# puts "\nOpening $design Implementation design\n" + +Opening simple_sume_switch Implementation design + +# open_run impl_1 +ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open +Vivado% +Vivado% +Vivado% quit + +#+END_CENTER +**** might be missing .runs/synth_1 (impl_1 respectively) +**** TODO Grep'ing for errors gives one unexpected EOF, but continues +#+BEGIN_CENTER +nico@nsg-System:~/master-thesis/netpfga$ grep -i error MAINLOG +cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API +ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37] +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_4_ErrorCheck +Compiling module work.TopParser_t_EngineStage_0_ErrorC... +Compiling module work.TopParser_t_EngineStage_1_ErrorC... +Compiling module work.TopParser_t_EngineStage_2_ErrorC... +Compiling module work.TopParser_t_EngineStage_3_ErrorC... +Compiling module work.TopParser_t_EngineStage_4_ErrorC... + +#+END_CENTER +**** TODO gen_testdata only shows one packet -> no receiving? +#+BEGIN_CENTER +./gen_testdata.py +nf0_applied times: [1] +nf1_applied times: [] +nf2_applied times: [] +nf3_applied times: [] + +#+END_CENTER +**** go through all steps again and try to understand why it (silently) fails later +*** 2019-07-13: fix overflow error ** References / Follow up *** RFC 791 IPv4 https://tools.ietf.org/html/rfc791 *** RFC 792 ICMP https://tools.ietf.org/html/rfc792 diff --git a/netpfga/do-all-steps.sh b/netpfga/do-all-steps.sh index 6d30c7f..c7fbbec 100755 --- a/netpfga/do-all-steps.sh +++ b/netpfga/do-all-steps.sh @@ -6,9 +6,6 @@ set -x echo "First source all variables and THEN run this script" read something - - - # Step 1..3: create code # Step 4 cd $P4_PROJECT_DIR && make diff --git a/netpfga/minip4/testdata/gen_testdata-port1.py b/netpfga/minip4/testdata/gen_testdata-port1.py index 9a67dae..aeada70 100755 --- a/netpfga/minip4/testdata/gen_testdata-port1.py +++ b/netpfga/minip4/testdata/gen_testdata-port1.py @@ -101,6 +101,7 @@ lookup_table = { } def test_port1(): + """ packets for a certain mac always go to nf0 """ pktCnt = 0 # First ethernet @@ -108,6 +109,14 @@ def test_port1(): pkt = Ether(dst=MAC2, src=MAC1) pkt = pad_pkt(pkt, 64) applyPkt(pkt, 'nf0', pktCnt) + + pktCnt += 1 + expPkt(pkt, 'nf0') + + pktCnt += 1 + applyPkt(pkt, 'nf1', pktCnt) + + pktCnt += 1 expPkt(pkt, 'nf0') # Test that packets are being mirrored diff --git a/p4app/controller.py b/p4app/controller.py index 559ce7c..f4b3642 100755 --- a/p4app/controller.py +++ b/p4app/controller.py @@ -65,6 +65,7 @@ class CpuHeader(Packet): name = 'CpuPacket' fields_desc = [ ShortEnumField('task', 1, cpu_fields ), + ShortField('ingress_port', 0), XShortEnumField("type", 0x9000, ETHER_TYPES), ShortEnumField('table_id', 1, table_id_fields ) diff --git a/p4src/actions_delta_checksum.p4 b/p4src/actions_delta_checksum.p4 index 5fc1c60..7b03af3 100644 --- a/p4src/actions_delta_checksum.p4 +++ b/p4src/actions_delta_checksum.p4 @@ -57,9 +57,10 @@ action delta_ipv4_from_v6_to_v4() { v4sum(); v6sum(); - bit<16> diff = meta.v6sum - meta.v4sum; + bit<16> diff = meta.v4sum - meta.v6sum ; hdr.tcp.checksum = hdr.tcp.checksum + ~diff +1; } + #endif \ No newline at end of file