diff --git a/netpfga/log/compile-2019-07-21-164256 b/netpfga/log/compile-2019-07-21-164256 index 48aab9c..8433dc9 100644 --- a/netpfga/log/compile-2019-07-21-164256 +++ b/netpfga/log/compile-2019-07-21-164256 @@ -9629,4 +9629,10 @@ Opening simple_sume_switch Implementation design # open_run impl_1 ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open -Vivado% \ No newline at end of file +Vivado% quit +INFO: [Common 17-206] Exiting Vivado at Sun Jul 21 19:12:27 2019... +make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw' +make -C sw/embedded/ project +make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded' +mkdir ./SDK_Workspace +xsdk -batch -source ./tcl/simple_sume_switch_xsdk.tcl diff --git a/netpfga/log/step5-2019-07-22-110213 b/netpfga/log/step5-2019-07-22-110213 new file mode 100644 index 0000000..f04e7ae --- /dev/null +++ b/netpfga/log/step5-2019-07-22-110213 @@ -0,0 +1,1721 @@ ++ find -name '*.v' -o -name '*.vp' -o -name '*.sv' ++ xargs -I % /opt/Xilinx/Vivado/2018.2/bin/xvlog -sv % +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v" into library work +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp" into library work +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_Engine +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_0 +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_dummy_table_for_netpfga_sec +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_dummy_table_for_netpfga_sec_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_dummy_table_for_netpfga_sec_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_1 +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_sume_metadata_dst_port +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port_0_sec +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port_0_sec_compute_sume_metadata_dst_port +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port_0_sec_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port_0_sec_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_2 +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_increment_offset +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work +INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v" into library work +INFO: [VRFC 10-311] analyzing module S_SYNCER_for__OUT_ +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work +INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_TopDeparser +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_fifo.sv" into library work +INFO: [VRFC 10-311] analyzing module xpm_fifo_base +INFO: [VRFC 10-311] analyzing module xpm_fifo_rst +INFO: [VRFC 10-311] analyzing module xpm_counter_updn +INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec +INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit +INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit +INFO: [VRFC 10-311] analyzing module xpm_fifo_sync +INFO: [VRFC 10-311] analyzing module xpm_fifo_async +INFO: [VRFC 10-311] analyzing module xpm_fifo_axis +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv" into library work +INFO: [VRFC 10-311] analyzing module xpm_memory_base +INFO: [VRFC 10-311] analyzing module asym_bwe_bb +INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram +INFO: [VRFC 10-311] analyzing module xpm_memory_dprom +INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram +INFO: [VRFC 10-311] analyzing module xpm_memory_spram +INFO: [VRFC 10-311] analyzing module xpm_memory_sprom +INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv" into library work +INFO: [VRFC 10-311] analyzing module xpm_cdc_single +INFO: [VRFC 10-311] analyzing module xpm_cdc_gray +INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake +INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse +INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single +INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst +INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v" into library work +INFO: [VRFC 10-311] analyzing module glbl +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v" into library work +INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopDeparser +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v" into library work +INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopParser +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request.vp" into library work +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv" into library work +INFO: [VRFC 10-311] analyzing module xpm_fifo_base +INFO: [VRFC 10-311] analyzing module xpm_fifo_rst +INFO: [VRFC 10-311] analyzing module xpm_counter_updn +INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec +INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit +INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit +INFO: [VRFC 10-311] analyzing module xpm_fifo_sync +INFO: [VRFC 10-311] analyzing module xpm_fifo_async +INFO: [VRFC 10-311] analyzing module xpm_fifo_axis +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv" into library work +INFO: [VRFC 10-311] analyzing module xpm_memory_base +INFO: [VRFC 10-311] analyzing module asym_bwe_bb +INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram +INFO: [VRFC 10-311] analyzing module xpm_memory_dprom +INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram +INFO: [VRFC 10-311] analyzing module xpm_memory_spram +INFO: [VRFC 10-311] analyzing module xpm_memory_sprom +INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv" into library work +INFO: [VRFC 10-311] analyzing module xpm_cdc_single +INFO: [VRFC 10-311] analyzing module xpm_cdc_gray +INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake +INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse +INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single +INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst +INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v" into library work +INFO: [VRFC 10-311] analyzing module glbl +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request.v" into library work +INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.vp" into library work +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_Engine +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_EngineStage_0 +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_dummy_table_for_netpfga_req_lookup_request_key +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_increment_offset +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v" into library work +INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp" into library work +ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37] +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.v" into library work +INFO: [VRFC 10-311] analyzing module S_CONTROLLER_SimpleSumeSwitch +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v" into library work +INFO: [VRFC 10-311] analyzing module TB_System_Stim +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" into library work +INFO: [VRFC 10-311] analyzing module Check +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" into library work +INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch_tb +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp" into library work +INFO: [VRFC 10-311] analyzing module TopDeparser_t_Engine +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec +INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_remove +INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoWriter +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_LatencyBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoReader +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterSelect +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_BarrelShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate_UniShifter2X +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataMux +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec +INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_insert +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_dst_addr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_src_addr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_ethertype +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoWriter +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_LatencyBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoReader +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterSelect +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_BarrelShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownMask +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownTuple +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate_UniShifter2X +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataMux +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_insert +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_task +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_ingress_port +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_ethertype +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_table_id +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_FifoWriter +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DscFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DscFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_LatencyBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_PktFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_PktFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_FifoReader +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterSelect +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer_BarrelShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge_UniShifterDownMask +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge_UniShifterDownTuple +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_BidirShifterUpdate +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_BidirShifterUpdate_UniShifter2X +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataMux +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_insert +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_version +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ihl +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_diff_serv +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ecn +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_totalLen +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_identification +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_flags +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_fragOffset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ttl +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_protocol +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_checksum +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_src_addr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_dst_addr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_FifoWriter +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DscFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DscFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_LatencyBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_PktFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_PktFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_FifoReader +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterSelect +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer_BarrelShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge_UniShifterDownMask +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge_UniShifterDownTuple +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_BidirShifterUpdate +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_BidirShifterUpdate_UniShifter2X +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataMux +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_insert +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_version +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_traffic_class +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_flow_label +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_payload_length +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_next_header +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_hop_limit +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_src_addr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_dst_addr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_FifoWriter +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DscFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DscFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_LatencyBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_PktFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_PktFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_FifoReader +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterSelect +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer_BarrelShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownMask +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_BidirShifterUpdate +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_BidirShifterUpdate_UniShifter2X +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataMux +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_insert +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_hw_type +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_protocol +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_hw_size +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_protocol_size +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_opcode +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_src_mac_addr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_src_ipv4_addr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_dst_mac_addr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_dst_ipv4_addr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_FifoWriter +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DscFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DscFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_LatencyBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_PktFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_PktFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_FifoReader +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterSelect +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer_BarrelShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge_UniShifterDownMask +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge_UniShifterDownTuple +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_BidirShifterUpdate +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_BidirShifterUpdate_UniShifter2X +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataMux +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_insert +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_src_port +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_dst_port +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_seqNo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ackNo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_data_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_res +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_cwr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ece +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_urg +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ack +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_psh +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_rst +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_syn +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_fin +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_window +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_checksum +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_urgentPtr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_FifoWriter +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DscFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DscFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_LatencyBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_PktFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_PktFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_FifoReader +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterSelect +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer_BarrelShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge_UniShifterDownMask +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge_UniShifterDownTuple +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_BidirShifterUpdate +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_BidirShifterUpdate_UniShifter2X +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataMux +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_insert +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_src_port +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_dst_port +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_payload_length +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_checksum +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_FifoWriter +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DscFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DscFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_LatencyBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_PktFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_PktFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_FifoReader +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterSelect +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer_BarrelShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge_UniShifterDownMask +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge_UniShifterDownTuple +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_BidirShifterUpdate +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_BidirShifterUpdate_UniShifter2X +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataMux +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_insert +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_type +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_code +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_checksum +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_FifoWriter +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DscFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DscFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_LatencyBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_PktFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_PktFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_FifoReader +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterSelect +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer_BarrelShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge_UniShifterDownMask +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge_UniShifterDownTuple +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_BidirShifterUpdate +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_BidirShifterUpdate_UniShifter2X +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataMux +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_insert +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_type +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_code +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_checksum +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_FifoWriter +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DscFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DscFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_LatencyBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_PktFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_PktFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_FifoReader +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterSelect +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer_BarrelShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge_UniShifterDownMask +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge_UniShifterDownTuple +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_BidirShifterUpdate +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_BidirShifterUpdate_UniShifter2X +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataMux +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_insert +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_router +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_solicitated +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_override +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_reserved +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_target_addr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_FifoWriter +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DscFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DscFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_LatencyBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_PktFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_PktFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_FifoReader +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterSelect +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer_BarrelShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge_UniShifterDownMask +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge_UniShifterDownTuple +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_BidirShifterUpdate +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_BidirShifterUpdate_UniShifter2X +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataMux +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0 +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_insert +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_type +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_ll_length +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_mac_addr +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_FifoWriter +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DscFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DscFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_LatencyBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_PktFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_PktFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleFifo +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleFifo_RAM +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_FifoReader +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterSelect +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer_BarrelShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge_UniShifterDownMask +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge_UniShifterDownTuple +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_UniShifterDown +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_UniShifterUp +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_BidirShifterUpdate +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_BidirShifterUpdate_UniShifter2X +INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataMux +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v" into library work +INFO: [VRFC 10-311] analyzing module TopDeparser_t +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v" into library work +INFO: [VRFC 10-311] analyzing module S_RESETTER_line +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v" into library work +INFO: [VRFC 10-311] analyzing module S_RESETTER_lookup +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v" into library work +INFO: [VRFC 10-311] analyzing module S_RESETTER_control +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp" into library work +INFO: [VRFC 10-311] analyzing module TopParser_t_Engine +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0 +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ExtractShifter +INFO: [VRFC 10-311] analyzing module TopParser_t_start +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_icmp +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_icmp6 +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_icmp6_na_ns +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_ipv4 +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_udp_v6 +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_udp_v4 +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_tcp_v6 +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_tcp_v4 +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_v4sum +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_v6sum +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_headerdiff +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_isValid +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_dst_addr +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_src_addr +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_ethertype +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_extracts_size +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopParser_t_reject +INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_TupleForward +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1 +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ExtractShifter +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4 +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_isValid +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_version +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_ihl +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_diff_serv +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_ecn +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_totalLen +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_identification +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_flags +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_fragOffset +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_ttl +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_protocol +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_checksum +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_src_addr +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_dst_addr +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_TopParser_extracts_size +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_meta_length_without_ip_header +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6 +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_isValid +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_version +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_traffic_class +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_flow_label +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_payload_length +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_next_header +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_hop_limit +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_src_addr +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_dst_addr +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_TopParser_extracts_size +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_meta_length_without_ip_header +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopParser_t_arp +INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_isValid +INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_hw_type +INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_protocol +INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_hw_size +INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_protocol_size +INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_opcode +INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_src_mac_addr +INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_src_ipv4_addr +INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_dst_mac_addr +INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_dst_ipv4_addr +INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_TopParser_extracts_size +INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_TupleForward +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2 +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_ExtractShifter +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6 +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_isValid +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_type +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_code +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_checksum +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_TopParser_extracts_size +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_isValid +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_src_port +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_dst_port +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_seqNo +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_ackNo +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_data_offset +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_res +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_cwr +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_ece +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_urg +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_ack +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_psh +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_rst +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_syn +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_fin +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_window +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_checksum +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_urgentPtr +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_TopParser_extracts_size +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopParser_t_udp +INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_isValid +INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_src_port +INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_dst_port +INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_payload_length +INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_checksum +INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_TopParser_extracts_size +INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_isValid +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_type +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_code +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_checksum +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_TopParser_extracts_size +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_TupleForward +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3 +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_ExtractShifter +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_isValid +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_router +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_solicitated +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_override +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_reserved +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_target_addr +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_isValid +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_type +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_ll_length +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_mac_addr +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_TopParser_extracts_size +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_control_increment_offset +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_TupleForward +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_4 +INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_4_ErrorCheck +INFO: [VRFC 10-311] analyzing module TopParser_t_accept +INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_nextSection +INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_increment_offset +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v" into library work +INFO: [VRFC 10-311] analyzing module TopParser_t +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v" into library work +INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_EGRESS +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp" into library work +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp" into library work +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v" into library work +INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_INGRESS +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/dummy_table_for_netpfga_t.vp" into library work +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Wrap +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_IntTop +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Lookup +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Hash_Lookup +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_RamR1RW1 +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Cam +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Update +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Hash_Update +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Randmod4 +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Randmod4_Rnd +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Randmod5 +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Randmod5_Rnd +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_csr +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv" into library work +INFO: [VRFC 10-311] analyzing module xpm_memory_base +INFO: [VRFC 10-311] analyzing module asym_bwe_bb +INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram +INFO: [VRFC 10-311] analyzing module xpm_memory_dprom +INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram +INFO: [VRFC 10-311] analyzing module xpm_memory_spram +INFO: [VRFC 10-311] analyzing module xpm_memory_sprom +INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_cdc.sv" into library work +INFO: [VRFC 10-311] analyzing module xpm_cdc_single +INFO: [VRFC 10-311] analyzing module xpm_cdc_gray +INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake +INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse +INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single +INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst +INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/dummy_table_for_netpfga_t.v" into library work +INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v" into library work +INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch ++ true ++ mkdir -p xsim.dir/xsc ++ find -name '*.c' ++ xargs /opt/Xilinx/Vivado/2018.2/bin/xsc -mt off -v 1 +Turned off multi-threading. +Running compilation flow +/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/CAM.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" -DXILINX_SIMULATOR +/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/user.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -DXILINX_SIMULATOR +./Testbench/user.c: In function ‘register_write_control’: +./Testbench/user.c:37:5: warning: implicit declaration of function ‘SV_write_control’ [-Wimplicit-function-declaration] + SV_write_control(&sv_addr, &sv_data); + ^~~~~~~~~~~~~~~~ +./Testbench/user.c: In function ‘register_read_control’: +./Testbench/user.c:51:5: warning: implicit declaration of function ‘SV_read_control’ [-Wimplicit-function-declaration] + SV_read_control(&sv_addr, &sv_data); + ^~~~~~~~~~~~~~~ +./Testbench/user.c: In function ‘CAM_Init’: +./Testbench/user.c:88:76: warning: passing argument 9 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types] + if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level)) + ^~~~~~~~~~~~~~ +In file included from ./Testbench/user.c:7:0: +./Testbench/CAM.h:169:5: note: expected ‘void (*)(addr_t, uint32_t) {aka void (*)(long long unsigned int, unsigned int)}’ but argument is of type ‘void (*)(uint32_t, uint32_t) {aka void (*)(unsigned int, unsigned int)}’ + int CAM_Init_ValidateContext( + ^~~~~~~~~~~~~~~~~~~~~~~~ +./Testbench/user.c:88:92: warning: passing argument 10 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types] + if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level)) + ^~~~~~~~~~~~~ +In file included from ./Testbench/user.c:7:0: +./Testbench/CAM.h:169:5: note: expected ‘uint32_t (*)(addr_t) {aka unsigned int (*)(long long unsigned int)}’ but argument is of type ‘uint32_t (*)(uint32_t) {aka unsigned int (*)(unsigned int)}’ + int CAM_Init_ValidateContext( + ^~~~~~~~~~~~~~~~~~~~~~~~ +Done compilation +Linking with command: +/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ + +Running command : /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ +Done linking: "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" ++ /opt/Xilinx/Vivado/2018.2/bin/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl +Multi-threading is on. Using 6 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling module work.S_RESETTER_line +Compiling module work.S_RESETTER_lookup +Compiling module work.S_RESETTER_control +Compiling module work.TopParser_t_EngineStage_0_ErrorC... +Compiling module work.TopParser_t_EngineStage_0_Extrac... +Compiling module work.TopParser_t_start_compute_meta_c... +Compiling module work.TopParser_t_start_compute_meta_c... +Compiling module work.TopParser_t_start_compute_meta_c... +Compiling module work.TopParser_t_start_compute_meta_c... +Compiling module work.TopParser_t_start_compute_meta_c... +Compiling module work.TopParser_t_start_compute_meta_c... +Compiling module work.TopParser_t_start_compute_meta_c... +Compiling module work.TopParser_t_start_compute_meta_c... +Compiling module work.TopParser_t_start_compute_meta_v... +Compiling module work.TopParser_t_start_compute_meta_v... +Compiling module work.TopParser_t_start_compute_meta_h... +Compiling module work.TopParser_t_start_compute_hdr_et... +Compiling module work.TopParser_t_start_compute_hdr_et... +Compiling module work.TopParser_t_start_compute_hdr_et... +Compiling module work.TopParser_t_start_compute_hdr_et... +Compiling module work.TopParser_t_start_compute_TopPar... +Compiling module work.TopParser_t_start_compute_contro... +Compiling module work.TopParser_t_start_compute_contro... +Compiling module work.TopParser_t_start +Compiling module work.TopParser_t_reject_compute_contr... +Compiling module work.TopParser_t_reject_compute_contr... +Compiling module work.TopParser_t_reject +Compiling module work.TopParser_t_EngineStage_0_TupleF... +Compiling module work.TopParser_t_EngineStage_0 +Compiling module work.TopParser_t_EngineStage_1_ErrorC... +Compiling module work.TopParser_t_EngineStage_1_Extrac... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv4_compute_TopPars... +Compiling module work.TopParser_t_ipv4_compute_meta_le... +Compiling module work.TopParser_t_ipv4_compute_control... +Compiling module work.TopParser_t_ipv4_compute_control... +Compiling module work.TopParser_t_ipv4 +Compiling module work.TopParser_t_ipv6_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv6_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv6_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv6_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv6_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv6_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv6_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv6_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv6_compute_hdr_ipv... +Compiling module work.TopParser_t_ipv6_compute_TopPars... +Compiling module work.TopParser_t_ipv6_compute_meta_le... +Compiling module work.TopParser_t_ipv6_compute_control... +Compiling module work.TopParser_t_ipv6_compute_control... +Compiling module work.TopParser_t_ipv6 +Compiling module work.TopParser_t_arp_compute_hdr_arp_... +Compiling module work.TopParser_t_arp_compute_hdr_arp_... +Compiling module work.TopParser_t_arp_compute_hdr_arp_... +Compiling module work.TopParser_t_arp_compute_hdr_arp_... +Compiling module work.TopParser_t_arp_compute_hdr_arp_... +Compiling module work.TopParser_t_arp_compute_hdr_arp_... +Compiling module work.TopParser_t_arp_compute_hdr_arp_... +Compiling module work.TopParser_t_arp_compute_hdr_arp_... +Compiling module work.TopParser_t_arp_compute_hdr_arp_... +Compiling module work.TopParser_t_arp_compute_hdr_arp_... +Compiling module work.TopParser_t_arp_compute_TopParse... +Compiling module work.TopParser_t_arp_compute_control_... +Compiling module work.TopParser_t_arp_compute_control_... +Compiling module work.TopParser_t_arp +Compiling module work.TopParser_t_EngineStage_1_TupleF... +Compiling module work.TopParser_t_EngineStage_1 +Compiling module work.TopParser_t_EngineStage_2_ErrorC... +Compiling module work.TopParser_t_EngineStage_2_Extrac... +Compiling module work.TopParser_t_icmp6_compute_hdr_ic... +Compiling module work.TopParser_t_icmp6_compute_hdr_ic... +Compiling module work.TopParser_t_icmp6_compute_hdr_ic... +Compiling module work.TopParser_t_icmp6_compute_hdr_ic... +Compiling module work.TopParser_t_icmp6_compute_TopPar... +Compiling module work.TopParser_t_icmp6_compute_contro... +Compiling module work.TopParser_t_icmp6_compute_contro... +Compiling module work.TopParser_t_icmp6 +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_hdr_tcp_... +Compiling module work.TopParser_t_tcp_compute_TopParse... +Compiling module work.TopParser_t_tcp_compute_control_... +Compiling module work.TopParser_t_tcp_compute_control_... +Compiling module work.TopParser_t_tcp +Compiling module work.TopParser_t_udp_compute_hdr_udp_... +Compiling module work.TopParser_t_udp_compute_hdr_udp_... +Compiling module work.TopParser_t_udp_compute_hdr_udp_... +Compiling module work.TopParser_t_udp_compute_hdr_udp_... +Compiling module work.TopParser_t_udp_compute_hdr_udp_... +Compiling module work.TopParser_t_udp_compute_TopParse... +Compiling module work.TopParser_t_udp_compute_control_... +Compiling module work.TopParser_t_udp_compute_control_... +Compiling module work.TopParser_t_udp +Compiling module work.TopParser_t_icmp_compute_hdr_icm... +Compiling module work.TopParser_t_icmp_compute_hdr_icm... +Compiling module work.TopParser_t_icmp_compute_hdr_icm... +Compiling module work.TopParser_t_icmp_compute_hdr_icm... +Compiling module work.TopParser_t_icmp_compute_TopPars... +Compiling module work.TopParser_t_icmp_compute_control... +Compiling module work.TopParser_t_icmp_compute_control... +Compiling module work.TopParser_t_icmp +Compiling module work.TopParser_t_EngineStage_2_TupleF... +Compiling module work.TopParser_t_EngineStage_2 +Compiling module work.TopParser_t_EngineStage_3_ErrorC... +Compiling module work.TopParser_t_EngineStage_3_Extrac... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_icmp6_neighbor_solic... +Compiling module work.TopParser_t_EngineStage_3_TupleF... +Compiling module work.TopParser_t_EngineStage_3 +Compiling module work.TopParser_t_EngineStage_4_ErrorC... +Compiling module work.TopParser_t_accept_compute_contr... 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work.xpm_counter_updn(COUNTER_WIDTH=8... +Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8... +Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... +Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT... +Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=8) +Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT... +Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=9) +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.S_BRIDGER_for_dummy_table_for_ne... +Compiling module work.S_PROTOCOL_ADAPTER_INGRESS +Compiling module work.S_PROTOCOL_ADAPTER_EGRESS +Compiling module work.xpm_fifo_rst_default +Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1... +Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9... +Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9... +Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... +Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... +Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... +Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... +Compiling module work.xpm_counter_updn(COUNTER_WIDTH=2... +Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1... +Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... +Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.S_SYNCER_for_TopParser +Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... +Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... +Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1... +Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... +Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.S_SYNCER_for_S_SYNCER_for_S_SYNC... +Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... +Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... +Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1... +Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8... +Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7... +Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7... +Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... +Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT... +Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=7) +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.S_SYNCER_for_S_SYNCER_for_TopDep... +Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... +Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... +Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1... +Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.S_SYNCER_for_TopDeparser +Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... +Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... +Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... +Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... +Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... +Compiling module work.S_SYNCER_for__OUT_ +Compiling module work.S_CONTROLLER_SimpleSumeSwitch +Compiling module work.SimpleSumeSwitch +Compiling module work.TB_System_Stim +Compiling module work.Check +Compiling module work.SimpleSumeSwitch_tb +Compiling module work.glbl +Built simulation snapshot work.SimpleSumeSwitch_tb#work.glbl + +****** Webtalk v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-186] '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Mon Jul 22 11:03:04 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2018.2/doc/webtalk_introduction.html. +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 22 11:03:04 2019... ++ /opt/Xilinx/Vivado/2018.2/bin/xsim --runall SimpleSumeSwitch_tb#work.glbl + +****** xsim v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsim_script.tcl +# xsim {work.SimpleSumeSwitch_tb#work.glbl} -autoloadwcfg -runall +Vivado Simulator 2018.2 +Time resolution is 1 ps +run -all +Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.dummy_table_for_netpfga.dummy_table_for_netpfga_t_Wrap_inst.dummy_table_for_netpfga_t_IntTop_inst.dummy_table_for_netpfga_t_Lookup_inst.dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/dummy_table_for_netpfga/dummy_table_for_netpfga_t_Wrap_inst/dummy_table_for_netpfga_t_IntTop_inst/dummy_table_for_netpfga_t_Lookup_inst/dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_678 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.dummy_table_for_netpfga.dummy_table_for_netpfga_t_Wrap_inst.dummy_table_for_netpfga_t_IntTop_inst.dummy_table_for_netpfga_t_Lookup_inst.dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/dummy_table_for_netpfga/dummy_table_for_netpfga_t_Wrap_inst/dummy_table_for_netpfga_t_IntTop_inst/dummy_table_for_netpfga_t_Lookup_inst/dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_678 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.dummy_table_for_netpfga.dummy_table_for_netpfga_t_Wrap_inst.dummy_table_for_netpfga_t_IntTop_inst.dummy_table_for_netpfga_t_Lookup_inst.dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/dummy_table_for_netpfga/dummy_table_for_netpfga_t_Wrap_inst/dummy_table_for_netpfga_t_IntTop_inst/dummy_table_for_netpfga_t_Lookup_inst/dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_678 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.dummy_table_for_netpfga.dummy_table_for_netpfga_t_Wrap_inst.dummy_table_for_netpfga_t_IntTop_inst.dummy_table_for_netpfga_t_Lookup_inst.dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/dummy_table_for_netpfga/dummy_table_for_netpfga_t_Wrap_inst/dummy_table_for_netpfga_t_IntTop_inst/dummy_table_for_netpfga_t_Lookup_inst/dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_678 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.dummy_table_for_netpfga.dummy_table_for_netpfga_t_Wrap_inst.dummy_table_for_netpfga_t_IntTop_inst.dummy_table_for_netpfga_t_Lookup_inst.dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/dummy_table_for_netpfga/dummy_table_for_netpfga_t_Wrap_inst/dummy_table_for_netpfga_t_IntTop_inst/dummy_table_for_netpfga_t_Lookup_inst/dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_678 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4843 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.q3qm7b9i98vxwzmbhgha93exy_77.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/q3qm7b9i98vxwzmbhgha93exy_77/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4936 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.rg95s6ilqqpyigaxfgfq81l2peow_728.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/rg95s6ilqqpyigaxfgfq81l2peow_728/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4966 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.iiczetq3f090mot8u_1945.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/iiczetq3f090mot8u_1945/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.gja47p6yw53fvyzt2nzjk2glb0t3_829.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/gja47p6yw53fvyzt2nzjk2glb0t3_829/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5114 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.pguwzfgk41cbbk0gv7qczocjbqi9d_570.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/pguwzfgk41cbbk0gv7qczocjbqi9d_570/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4936 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.witvzxsd4o24ppu4ph0p721_1734.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/witvzxsd4o24ppu4ph0p721_1734/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4966 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.y15t7s2lh0kyc9e8xzlc_575.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y15t7s2lh0kyc9e8xzlc_575/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5295 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.cf2sr3rr1xv1ronqbz3upoyxg42d6a_870.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/cf2sr3rr1xv1ronqbz3upoyxg42d6a_870/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5379 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.gc1l10cqohyzwuu5l9db9t5guewbc_452.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gc1l10cqohyzwuu5l9db9t5guewbc_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5463 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.kcle7o5dwrjp5niebfbuu9rfc9f_2433.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/kcle7o5dwrjp5niebfbuu9rfc9f_2433/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.tfounu8ngepa2ojycwc9h4_1522.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/tfounu8ngepa2ojycwc9h4_1522/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5114 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.rsk500hp4rrd8k5x2n4nbkhhxx5jcwn_1515.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rsk500hp4rrd8k5x2n4nbkhhxx5jcwn_1515/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5715 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.myh47dvvfhbdgaf49afqb6gcppcm452p_2275.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/myh47dvvfhbdgaf49afqb6gcppcm452p_2275/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4936 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.znmrw8chh4dlbdy5qw3wha0uphl7e4hy_1414.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/znmrw8chh4dlbdy5qw3wha0uphl7e4hy_1414/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4966 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.dhhqg6ugti4voc2zke965xevd4smgseq_2683.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/dhhqg6ugti4voc2zke965xevd4smgseq_2683/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5463 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.zb5abyk8gg5n0tbucp2s0ahn_740.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/zb5abyk8gg5n0tbucp2s0ahn_740/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5295 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.tuiyjgdeqb7ij45ldm4r_1288.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/tuiyjgdeqb7ij45ldm4r_1288/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6068 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.oi2o5fdktbxvjyxuoab56ahjoj63_825.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/oi2o5fdktbxvjyxuoab56ahjoj63_825/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5379 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.upnxdxmynkj9gex5ihi5zgbcgxsl_2301.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/upnxdxmynkj9gex5ihi5zgbcgxsl_2301/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.vmt4r2t4c5xj33gcs1sp9sm_2270.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/vmt4r2t4c5xj33gcs1sp9sm_2270/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6320 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.tle5iq9tenjjk7dmx57o7m2mc7e6_263.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/tle5iq9tenjjk7dmx57o7m2mc7e6_263/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5114 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.mt9u8xl7hpx38eb42bdqg_1976.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/mt9u8xl7hpx38eb42bdqg_1976/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5715 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.dcjmp7c7fmppjp83p2e854adnpkit_185.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/dcjmp7c7fmppjp83p2e854adnpkit_185/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4936 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.sxfteah8jf8qdhbhqfrpo1bwu9jque_1687.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/sxfteah8jf8qdhbhqfrpo1bwu9jque_1687/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4966 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.tvn1baz5ywk8kys4sn1r52tm48c_1342.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/tvn1baz5ywk8kys4sn1r52tm48c_1342/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5295 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.fmahnh8s1jb0lp9y_1268.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/fmahnh8s1jb0lp9y_1268/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5379 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.x5xfsmcw5w2g4a3e4anu4d2x14z_933.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/x5xfsmcw5w2g4a3e4anu4d2x14z_933/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5463 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.hg51dquwrzmlwjcny2ttd5h2eiqnt1t_1412.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/hg51dquwrzmlwjcny2ttd5h2eiqnt1t_1412/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.h1dpyxgbpittfn0ryd97x_1052.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/h1dpyxgbpittfn0ryd97x_1052/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5114 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.dpe4noss20bcg5dtm_2385.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/dpe4noss20bcg5dtm_2385/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5715 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.wflcv45bf8qrcmhzotn_958.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/wflcv45bf8qrcmhzotn_958/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_7174 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.lvepud277hegeei4w1y26py5utj_1809.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/lvepud277hegeei4w1y26py5utj_1809/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4966 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.gg9ts8sphva3iipsrbolr99gf1v_1551.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/gg9ts8sphva3iipsrbolr99gf1v_1551/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5463 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.kl2jmadeuopud91kgrey1m0y8qhdx_1060.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 +Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/kl2jmadeuopud91kgrey1m0y8qhdx_1060/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv +[SW] CAM_Init() - start +[SW] CAM_Init() - done +[SW] CAM_EnableDevice() - start +SV_write_control()- start +SV_write_control()- done +SV_read_control()- start +SV_read_control()- done +SV_write_control()- start +SV_write_control()- done +[SW] CAM_EnableDevice() - done +[2280754] INFO: finished packet stimulus file +[3728508] INFO: packet 1 tuple OK < tuple_out_digest_data, tuple_out_standard_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 > +[3728508] INFO: packet 1 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208) +[3731840] INFO: packet 1 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000) +[3738504] INFO: packet 2 tuple OK < tuple_out_digest_data, tuple_out_standard_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001040000 > +[3738504] INFO: packet 2 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208) +[3741836] INFO: packet 2 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000) +[3748500] INFO: packet 3 tuple OK < tuple_out_digest_data, tuple_out_standard_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001100000 > +[3748500] INFO: packet 3 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208) +[3751832] INFO: packet 3 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000) +[3758496] INFO: packet 4 tuple OK < tuple_out_digest_data, tuple_out_standard_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001400000 > +[3758496] INFO: packet 4 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208) +[3761828] INFO: packet 4 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000) +[7097160] INFO: stopping simulation after 1000 idle cycles +[7097160] INFO: all expected data successfully received +[7097160] INFO: TEST PASSED +$finish called at time : 7097160 ps : File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" Line 207 +exit +INFO: [Common 17-206] Exiting xsim at Mon Jul 22 11:03:17 2019...