diff --git a/doc/plan.org b/doc/plan.org
index 7d975e6..c4e31fb 100644
--- a/doc/plan.org
+++ b/doc/plan.org
@@ -2174,6 +2174,97 @@ new dic: OrderedDict()
 
 
 ****** TODO try10: find out, why nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt has too less content
+******* DONE find out what generates config_writes.txt
+Seems to be step 5:
+
+#+BEGIN_CENTER
+[14:22] rainbow:SimpleSumeSwitch% pwd
+/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch
+[14:23] rainbow:SimpleSumeSwitch% ls -lh config_writes.txt
+-rw-rw-r-- 1 nico nico 140 May 25 14:21 config_writes.txt
+[14:23] rainbow:SimpleSumeSwitch% date
+Sat 25 May 2019 02:23:41 PM CEST
+[14:23] rainbow:SimpleSumeSwitch%
+#+END_CENTER
+******* TODO Debug vivado_sim.bash -> run w/ x11 output, also vivado_sim_waveform.bash
+Open GUI, pressing "play" button, getting different / new errors
+#+BEGIN_CENTER
+[SW] CAM_Init() - done
+[SW] CAM_EnableDevice() - start
+SV_write_control()- start
+SV_write_control()- done
+SV_read_control()- start
+SV_read_control()- done
+SV_write_control()- start
+SV_write_control()- done
+[SW] CAM_EnableDevice() - done
+[2420698]  INFO: finished packet stimulus file
+[2735572] ERROR: tuple mismatch for packet 1
+expected < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
+actual   < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000010000 >
+$finish called at time : 2735572 ps : File
+"/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v"
+Line 120
+
+#+END_CENTER
+
+Error message created in
+/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v
+
+Same error on shell only version:
+
+#+BEGIN_CENTER
+projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv
+[SW] CAM_Init() - start
+[SW] CAM_Init() - done
+[SW] CAM_EnableDevice() - start
+SV_write_control()- start
+SV_write_control()- done
+SV_read_control()- start
+SV_read_control()- done
+SV_write_control()- start
+SV_write_control()- done
+[SW] CAM_EnableDevice() - done
+[2420698]  INFO: finished packet stimulus file
+[2735572] ERROR: tuple mismatch for packet 1
+expected < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
+actual   < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000010000 >
+$finish called at time : 2735572 ps : File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" Line 120
+exit
+INFO: [Common 17-206] Exiting xsim at Sat May 25 14:38:05 2019...
+[14:38] rainbow:SimpleSumeSwitch% echo $?
+0
+[14:38] rainbow:SimpleSumeSwitch%
+
+#+END_CENTER
+
+Analysing Makefile in testdata + scripts
+******** get_testdata.py: generates some pcap with some packets
+
+Need to find out
+import sss_sdnet_tuples
+sss_sdnet_tuples.clear_tuple_files()
+
+Result of this script is src.pcap and dst.pcap.
+
+Is the lookup table related to the devices?
+
+NUM_KEYS = 4
+lookup_table = {
+    0: 0x00000001,
+    1: 0x00000010,
+    2: 0x00000100,
+    3: 0x00001000
+}
+
+Where are in/out ports?!
+
+Modifying / adjusting P4 code to mirror input packets
+
+******** switch_calc_headers creates some headers
+some specific packet,  uses bind_layers
+
+
 
 ***** run step 11: checking design -- skipped
 ***** TODO run step 12: ok
@@ -2305,6 +2396,15 @@ sume_riffa             28672  0
 #+END_CENTER
 
 
+***** 2019-05-26, netfpga integration
+
+#+BEGIN_CENTER
+[10:56] rainbow:projects% mv minip4 ~/master-thesis/netpfga/
+[10:56] rainbow:projects% ln -s ~/master-thesis/netpfga/minip4
+[10:56] rainbow:projects%
+
+#+END_CENTER
+
 **** DONE Understand a bit of xilinx/netfpga/vivado ~ somewhat
      - https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug900-vivado-logic-simulation.pdf
 The xvhdl and xvlog commands parse VHDL and Verilog files, respectively. Descriptions