make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test' vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_defines.tcl ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_defines.tcl # set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 # set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF # set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 # set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 # set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF # set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 # set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 # set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF # set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 # set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 # set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF # set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 # set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 # set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF # set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 # set M00_BASEADDR 0x44000000 # set M00_HIGHADDR 0x44000FFF # set M00_SIZEADDR 0x1000 # set M01_BASEADDR 0x44010000 # set M01_HIGHADDR 0x44010FFF # set M01_SIZEADDR 0x1000 # set M02_BASEADDR 0x44020000 # set M02_HIGHADDR 0x44020FFF # set M02_SIZEADDR 0x1000 # set M03_BASEADDR 0x44030000 # set M03_HIGHADDR 0x44030FFF # set M03_SIZEADDR 0x1000 # set M04_BASEADDR 0x44040000 # set M04_HIGHADDR 0x44040FFF # set M04_SIZEADDR 0x1000 # set M05_BASEADDR 0x44050000 # set M05_HIGHADDR 0x44050FFF # set M05_SIZEADDR 0x1000 # set M06_BASEADDR 0x44060000 # set M06_HIGHADDR 0x44060FFF # set M06_SIZEADDR 0x1000 # set M07_BASEADDR 0x44070000 # set M07_HIGHADDR 0x44070FFF # set M07_SIZEADDR 0x1000 # set M08_BASEADDR 0x44080000 # set M08_HIGHADDR 0x44080FFF # set M08_SIZEADDR 0x1000 # set IDENTIFIER_BASEADDR $M00_BASEADDR # set IDENTIFIER_HIGHADDR $M00_HIGHADDR # set IDENTIFIER_SIZEADDR $M00_SIZEADDR # set INPUT_ARBITER_BASEADDR $M01_BASEADDR # set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR # set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR # set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR # set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR # set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR # set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR # set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR # set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR # set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR # set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR # set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR # set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR # set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR # set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR # set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR # set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR # set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR # set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR # set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR # set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR # set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR # set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR # set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR INFO: [Common 17-206] Exiting Vivado at Mon Jul 22 22:30:21 2019... vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/export_registers.tcl ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/export_registers.tcl # set DEF_LIST { # {MICROBLAZE_AXI_IIC 0 0 ""} \ # {MICROBLAZE_UARTLITE 0 0 ""} \ # {MICROBLAZE_DLMB_BRAM 0 0 ""} \ # {MICROBLAZE_ILMB_BRAM 0 0 ""} \ # {MICROBLAZE_AXI_INTC 0 0 ""} \ # {INPUT_ARBITER 0 1 input_arbiter_v1_0_0/data/input_arbiter_regs_defines.txt} \ # {OUTPUT_QUEUES 0 1 output_queues_v1_0_0/data/output_queues_regs_defines.txt} \ # {OUTPUT_PORT_LOOKUP 0 1 switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.txt} \ # {NF_10G_INTERFACE0 0 1 nf_10ge_interface_shared_v1_0_0/data/nf_10g_interface_shared_regs_defines.txt} \ # {NF_10G_INTERFACE1 1 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ # {NF_10G_INTERFACE2 2 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ # {NF_10G_INTERFACE3 3 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ # {NF_RIFFA_DMA 0 1 nf_riffa_dma_v1_0_0/data/nf_riffa_dma_regs_defines.txt} \ # # # } # set target_path $::env(NF_DESIGN_DIR)/sw/embedded/src/ # set target_file $target_path/sume_register_defines.h # proc write_header { target_file } { # # # creat a blank header file # # do a fresh rewrite in case the file already exits # file delete -force $target_file # open $target_file "w" # set h_file [open $target_file "w"] # # # puts $h_file "//-" # puts $h_file "// Copyright (c) 2015 University of Cambridge" # puts $h_file "// All rights reserved." # puts $h_file "//" # puts $h_file "// This software was developed by Stanford University and the University of Cambridge Computer Laboratory " # puts $h_file "// under National Science Foundation under Grant No. CNS-0855268," # puts $h_file "// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and" # puts $h_file "// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 (\"MRC2\"), " # puts $h_file "// as part of the DARPA MRC research programme." # puts $h_file "//" # puts $h_file "// @NETFPGA_LICENSE_HEADER_START@" # puts $h_file "//" # puts $h_file "// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor" # puts $h_file "// license agreements. See the NOTICE file distributed with this work for" # puts $h_file "// additional information regarding copyright ownership. NetFPGA licenses this" # puts $h_file "// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the" # puts $h_file "// \"License\"); you may not use this file except in compliance with the" # puts $h_file "// License. You may obtain a copy of the License at:" # puts $h_file "//" # puts $h_file "// http://www.netfpga-cic.org" # puts $h_file "//" # puts $h_file "// Unless required by applicable law or agreed to in writing, Work distributed" # puts $h_file "// under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR" # puts $h_file "// CONDITIONS OF ANY KIND, either express or implied. See the License for the" # puts $h_file "// specific language governing permissions and limitations under the License." # puts $h_file "//" # puts $h_file "// @NETFPGA_LICENSE_HEADER_END@" # puts $h_file "/////////////////////////////////////////////////////////////////////////////////" # puts $h_file "// This is an automatically generated header definitions file" # puts $h_file "/////////////////////////////////////////////////////////////////////////////////" # puts $h_file "" # # close $h_file # # }; # proc write_core {target_file prefix id has_registers lib_name} { # # # set h_file [open $target_file "a"] # # #First, read the memory map information from the reference_project defines file # source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl # set public_repo_dir $::env(SUME_FOLDER)/lib/hw/ # # # set baseaddr [set $prefix\_BASEADDR] # set highaddr [set $prefix\_HIGHADDR] # set sizeaddr [set $prefix\_SIZEADDR] # # puts $h_file "//######################################################" # puts $h_file "//# Definitions for $prefix" # puts $h_file "//######################################################" # # puts $h_file "#define SUME_$prefix\_BASEADDR $baseaddr" # puts $h_file "#define SUME_$prefix\_HIGHADDR $highaddr" # puts $h_file "#define SUME_$prefix\_SIZEADDR $sizeaddr" # puts $h_file "" # # #Second, read the registers information from the library defines file # if $has_registers { # set lib_path "$public_repo_dir/std/cores/$lib_name" # set regs_h_define_file $lib_path # set regs_h_define_file_read [open $regs_h_define_file r] # set regs_h_define_file_data [read $regs_h_define_file_read] # close $regs_h_define_file_read # set regs_h_define_file_data_line [split $regs_h_define_file_data "\n"] # # foreach read_line $regs_h_define_file_data_line { # if {[regexp "#define" $read_line]} { # puts $h_file "#define SUME_[lindex $read_line 2]\_$id\_[lindex $read_line 3]\_[lindex $read_line 4] [lindex $read_line 5]" # } # } # } # puts $h_file "" # close $h_file # }; # write_header $target_file # foreach lib_item $DEF_LIST { # write_core $target_file [lindex $lib_item 0] [lindex $lib_item 1] [lindex $lib_item 2] [lindex $lib_item 3] # } ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR INFO: [Common 17-206] Exiting Vivado at Mon Jul 22 22:30:27 2019... cd ../sw/embedded/src && cp /home/nico/projects/P4-NetFPGA/tools/scripts/xparam2regdefines.py . && python xparam2regdefines.py cd ../sw/embedded/src && rm -f xparam2regdefines.py && mv reg_defines.h ../ cd ../sw/embedded && cp /home/nico/projects/P4-NetFPGA/tools/scripts/python_parser.py . && python python_parser.py cd ../sw/embedded && rm -f python_parser.py && mv reg_defines.py ../../test/reg_defines_simple_sume_switch.py make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test' make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test' rm -rf proj_* vivado*.* *.*~ .Xil* /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/ rm -rf *[0-9]_{stim,expected,log}.axi rm -f *.axi rm -f portconfig.sim rm -f seed rm -f *.log rm -f ../test/Makefile rm -rf ../test/*.log rm -rf ../test/*.axi rm -rf ../test/seed rm -rf ../test/*.sim rm -rf ../test/proj_* rm -rf ../test/ip_repo rm -f ../test/vivado*.* rm -f ../test/*_*_*/reg_defines_simple_sume_switch.py rm -f ../test/*_*_*/reg_defines_simple_sume_switch.pyc rm -f ../hw/create_ip/id_rom16x32.coe cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh echo 16028002 >> rom_data.txt echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt grep: ../../../RELEASE_NOTES: No such file or directory echo 00000204 >> rom_data.txt echo 0000FFFF >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py 16 mv -f id_rom16x32.coe ../hw/create_ip/ mv -f rom_data.txt ../hw/create_ip/ cp -f /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_defines_simple_sume_switch.py /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/reg_defines_simple_sume_switch.py vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl -tclargs sim_switch_default ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl # set design $::env(NF_PROJECT_NAME) # set top top_sim # set sim_top top_tb # set device xc7vx690t-3-ffg1761 # set proj_dir ./project # set public_repo_dir $::env(SUME_FOLDER)/lib/hw/ # set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/ # set repo_dir ./ip_repo # set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc # set project_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_general.xdc # set nf_10g_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_10g.xdc # set test_name [lindex $argv 0] # source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR # create_project -name ${design} -force -dir "$::env(NF_DESIGN_DIR)/hw/${proj_dir}" -part ${device} # set_property source_mgmt_mode DisplayOnly [current_project] # set_property top ${top} [current_fileset] # puts "Creating User Datapath reference project" Creating User Datapath reference project # create_fileset -constrset -quiet constraints # file copy ${public_repo_dir}/ ${repo_dir} # set_property ip_repo_paths ${repo_dir} [current_fileset] # add_files -fileset constraints -norecurse ${bit_settings} # add_files -fileset constraints -norecurse ${project_constraints} # add_files -fileset constraints -norecurse ${nf_10g_constraints} # set_property is_enabled true [get_files ${project_constraints}] # set_property is_enabled true [get_files ${bit_settings}] # set_property is_enabled true [get_files ${project_constraints}] # update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/ip_repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'. # create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip # set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci] # reset_target all [get_ips nf_sume_sdnet_ip] # generate_target all [get_ips nf_sume_sdnet_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_sume_sdnet_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_sume_sdnet_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_sume_sdnet_ip'... # create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip # set_property -dict [list CONFIG.C_BASEADDR $INPUT_ARBITER_BASEADDR] [get_ips input_arbiter_ip] # set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci] # reset_target all [get_ips input_arbiter_ip] # generate_target all [get_ips input_arbiter_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'input_arbiter_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'input_arbiter_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'input_arbiter_ip'... # create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip # set_property -dict [list CONFIG.C_BASEADDR $OUTPUT_QUEUES_BASEADDR] [get_ips sss_output_queues_ip] # set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci] # reset_target all [get_ips sss_output_queues_ip] # generate_target all [get_ips sss_output_queues_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'sss_output_queues_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'sss_output_queues_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'sss_output_queues_ip'... # create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip INFO: [Device 21-403] Loading part xc7vx690tffg1761-3 create_ip: Time (s): cpu = 00:00:22 ; elapsed = 00:00:59 . Memory (MB): peak = 1690.246 ; gain = 390.395 ; free physical = 10323 ; free virtual = 15527 # set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {1024} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip] # set_property generate_synth_checkpoint false [get_files identifier_ip.xci] # reset_target all [get_ips identifier_ip] # generate_target all [get_ips identifier_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'identifier_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'identifier_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'identifier_ip'... INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'identifier_ip'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'identifier_ip'... # create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip # set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip] WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '5.000' to '5.0' has been ignored for IP 'clk_wiz_ip' # set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci] # reset_target all [get_ips clk_wiz_ip] # generate_target all [get_ips clk_wiz_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz_ip'... INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz_ip'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz_ip'... # create_ip -name barrier -vendor NetFPGA -library NetFPGA -module_name barrier_ip # reset_target all [get_ips barrier_ip] # generate_target all [get_ips barrier_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'barrier_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'barrier_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'barrier_ip'... # create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip0 # set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_0_log.axi] [get_ips axis_sim_record_ip0] # reset_target all [get_ips axis_sim_record_ip0] # generate_target all [get_ips axis_sim_record_ip0] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip0'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip0'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip0'... # create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip1 # set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_1_log.axi] [get_ips axis_sim_record_ip1] # reset_target all [get_ips axis_sim_record_ip1] # generate_target all [get_ips axis_sim_record_ip1] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip1'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip1'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip1'... # create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip2 # set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_2_log.axi] [get_ips axis_sim_record_ip2] # reset_target all [get_ips axis_sim_record_ip2] # generate_target all [get_ips axis_sim_record_ip2] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip2'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip2'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip2'... # create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip3 # set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_3_log.axi] [get_ips axis_sim_record_ip3] # reset_target all [get_ips axis_sim_record_ip3] # generate_target all [get_ips axis_sim_record_ip3] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip3'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip3'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip3'... # create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip4 # set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/dma_0_log.axi] [get_ips axis_sim_record_ip4] # reset_target all [get_ips axis_sim_record_ip4] # generate_target all [get_ips axis_sim_record_ip4] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip4'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip4'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip4'... # create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip0 # set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_0_stim.axi] [get_ips axis_sim_stim_ip0] # generate_target all [get_ips axis_sim_stim_ip0] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip0'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip0'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip0'... # create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip1 # set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_1_stim.axi] [get_ips axis_sim_stim_ip1] # generate_target all [get_ips axis_sim_stim_ip1] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip1'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip1'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip1'... # create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip2 # set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_2_stim.axi] [get_ips axis_sim_stim_ip2] # generate_target all [get_ips axis_sim_stim_ip2] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip2'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip2'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip2'... # create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip3 # set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_3_stim.axi] [get_ips axis_sim_stim_ip3] # generate_target all [get_ips axis_sim_stim_ip3] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip3'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip3'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip3'... # create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip4 # set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/dma_0_stim.axi] [get_ips axis_sim_stim_ip4] # generate_target all [get_ips axis_sim_stim_ip4] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip4'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip4'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip4'... # create_ip -name axi_sim_transactor -vendor NetFPGA -library NetFPGA -module_name axi_sim_transactor_ip # set_property -dict [list CONFIG.STIM_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.axi CONFIG.EXPECT_FILE $::env(NF_DESIGN_DIR)/test/reg_expect.axi CONFIG.LOG_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.log] [get_ips axi_sim_transactor_ip] # reset_target all [get_ips axi_sim_transactor_ip] # generate_target all [get_ips axi_sim_transactor_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_sim_transactor_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_sim_transactor_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_sim_transactor_ip'... # update_ip_catalog # source $::env(NF_DESIGN_DIR)/hw/tcl/control_sub_sim.tcl ## set scripts_vivado_version 2018.2 ## set current_vivado_version [version -short] ## if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { ## puts "" ## puts "ERROR: This script was created for Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script." ## ## return 1 ## } ## set design_name control_sub ## if { [get_projects -quiet] eq "" } { ## puts "ERROR: Please open or create a project!" ## return 1 ## } ## set errMsg "" ## set nRet 0 ## set cur_design [current_bd_design -quiet] ## set list_cells [get_bd_cells -quiet] ## if { ${design_name} eq "" } { ## # USE CASES: ## # 1) Design_name not set ## ## set errMsg "ERROR: Please set the variable to a non-empty value." ## set nRet 1 ## ## } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { ## # USE CASES: ## # 2): Current design opened AND is empty AND names same. ## # 3): Current design opened AND is empty AND names diff; design_name NOT in project. ## # 4): Current design opened AND is empty AND names diff; design_name exists in project. ## ## if { $cur_design ne $design_name } { ## puts "INFO: Changing value of from <$design_name> to <$cur_design> since current design is empty." ## set design_name [get_property NAME $cur_design] ## } ## puts "INFO: Constructing design in IPI design <$cur_design>..." ## ## } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { ## # USE CASES: ## # 5) Current design opened AND has components AND same names. ## ## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." ## set nRet 1 ## } elseif { [get_files -quiet ${design_name}.bd] ne "" } { ## # USE CASES: ## # 6) Current opened design, has components, but diff names, design_name exists in project. ## # 7) No opened design, design_name exists in project. ## ## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." ## set nRet 2 ## ## } else { ## # USE CASES: ## # 8) No opened design, design_name not in project. ## # 9) Current opened design, has components, but diff names, design_name not in project. ## ## puts "INFO: Currently there is no design <$design_name> in project, so creating one..." ## ## create_bd_design $design_name ## ## puts "INFO: Making design <$design_name> as current_bd_design." ## current_bd_design $design_name ## ## } INFO: Currently there is no design in project, so creating one... Wrote : INFO: Making design as current_bd_design. ## puts "INFO: Currently the variable is equal to \"$design_name\"." INFO: Currently the variable is equal to "control_sub". ## if { $nRet != 0 } { ## puts $errMsg ## return $nRet ## } ## proc create_root_design { parentCell } { ## ## if { $parentCell eq "" } { ## set parentCell [get_bd_cells /] ## } ## ## # Get object for parentCell ## set parentObj [get_bd_cells $parentCell] ## if { $parentObj == "" } { ## puts "ERROR: Unable to find parent cell <$parentCell>!" ## return ## } ## ## # Make sure parentObj is hier blk ## set parentType [get_property TYPE $parentObj] ## if { $parentType ne "hier" } { ## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." ## return ## } ## ## # Save current instance; Restore later ## set oldCurInst [current_bd_instance .] ## ## # Set parent object as current ## current_bd_instance $parentObj ## ## ## # Create interface ports ## set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M00_AXI ## set M01_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M01_AXI ## set M02_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M02_AXI ## set M03_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M03_AXI ## set M04_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M04_AXI ## set M05_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M05_AXI ## set M06_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M06_AXI ## set M07_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M07_AXI ## set S00_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.ARUSER_WIDTH {0} CONFIG.AWUSER_WIDTH {0} CONFIG.BUSER_WIDTH {0} CONFIG.CLK_DOMAIN {} CONFIG.DATA_WIDTH {32} CONFIG.FREQ_HZ {100000000} CONFIG.ID_WIDTH {0} CONFIG.MAX_BURST_LENGTH {256} CONFIG.NUM_READ_OUTSTANDING {2} CONFIG.NUM_WRITE_OUTSTANDING {2} CONFIG.PHASE {0.000} CONFIG.PROTOCOL {AXI4} CONFIG.READ_WRITE_MODE {READ_WRITE} CONFIG.RUSER_WIDTH {0} CONFIG.SUPPORTS_NARROW_BURST {1} CONFIG.WUSER_WIDTH {0} ] $S00_AXI ## ## # Create ports ## set axi_lite_aclk [ create_bd_port -dir I -type clk axi_lite_aclk ] ## set axi_lite_areset [ create_bd_port -dir I -type rst axi_lite_areset ] ## set core_clk [ create_bd_port -dir I -type clk core_clk ] ## set_property -dict [ list CONFIG.FREQ_HZ {200000000} ] $core_clk ## set core_resetn [ create_bd_port -dir I -type rst core_resetn ] ## ## ## ## ## # Create instance: axi_interconnect_0, and set properties ## set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] ## set_property -dict [ list CONFIG.NUM_MI {8} CONFIG.TRANSLATION_MODE {0} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M00_HAS_REGSLICE {3} CONFIG.M00_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M01_HAS_REGSLICE {3} CONFIG.M01_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M02_HAS_REGSLICE {3} CONFIG.M02_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M03_HAS_REGSLICE {3} CONFIG.M03_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M04_HAS_REGSLICE {3} CONFIG.M04_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M05_HAS_REGSLICE {3} CONFIG.M05_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M06_HAS_REGSLICE {3} CONFIG.M06_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M07_HAS_REGSLICE {3} CONFIG.M07_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.S00_HAS_REGSLICE {3} CONFIG.S00_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## ## ## # Add AXI clock converter ## create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ## connect_bd_intf_net [get_bd_intf_ports S00_AXI] [get_bd_intf_pins axi_clock_converter_0/S_AXI] ## connect_bd_intf_net [get_bd_intf_pins axi_clock_converter_0/M_AXI] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S00_AXI] ## ## # Create interface connections ## connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports M01_AXI] [get_bd_intf_pins axi_interconnect_0/M01_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports M02_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports M03_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports M04_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_ports M05_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_ports M06_AXI] [get_bd_intf_pins axi_interconnect_0/M06_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_ports M07_AXI] [get_bd_intf_pins axi_interconnect_0/M07_AXI] ## ## # Create port connections ## connect_bd_net -net axi_lite_aclk_1 [get_bd_ports axi_lite_aclk] [get_bd_pins axi_clock_converter_0/s_axi_aclk] ## connect_bd_net -net core_clk_1 [get_bd_ports core_clk] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] ## connect_bd_net -net axi_lite_areset_1 [get_bd_ports axi_lite_areset] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] ## connect_bd_net -net core_resetn_1 [get_bd_ports core_resetn] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] ## ## # Create address segments ## source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl ## assign_bd_address [get_bd_addr_segs {M00_AXI/Reg }] ## set_property offset $M00_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}] ## set_property range $M00_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}] ## ## assign_bd_address [get_bd_addr_segs {M01_AXI/Reg }] ## set_property offset $M01_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}] ## set_property range $M01_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}] ## ## ## assign_bd_address [get_bd_addr_segs {M02_AXI/Reg }] ## set_property offset $M02_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}] ## set_property range $M02_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}] ## ## assign_bd_address [get_bd_addr_segs {M03_AXI/Reg }] ## set_property offset $M03_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}] ## set_property range $M03_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}] ## ## ## # Restore current instance ## current_bd_instance $oldCurInst ## ## save_bd_design ## } ## create_root_design "" CRITICAL WARNING: [BD 41-737] Cannot set the parameter TRANSLATION_MODE on /axi_interconnect_0. It is read-only. ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR is being mapped into at <0x44A00000 [ 64K ]> is being mapped into at <0x44A00000 [ 64K ]> is being mapped into at <0x44A00000 [ 64K ]> is being mapped into at <0x44A00000 [ 64K ]> Wrote : # read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/axi_clocking.v" # read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/nf_datapath.v" # read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_sim.v" # read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_tb.v" # update_compile_order -fileset sources_1 # update_compile_order -fileset sim_1 # set_property top ${sim_top} [get_filesets sim_1] # set_property include_dirs ${proj_dir} [get_filesets sim_1] # set_property simulator_language Mixed [current_project] # set_property verilog_define { {SIMULATION=1} } [get_filesets sim_1] # set_property -name xsim.more_options -value {-testplusarg TESTNAME=basic_test} -objects [get_filesets sim_1] # set_property runtime {} [get_filesets sim_1] # set_property target_simulator xsim [current_project] # set_property compxlib.xsim_compiled_library_dir {} [current_project] # set_property top_lib xil_defaultlib [get_filesets sim_1] # update_compile_order -fileset sim_1 update_compile_order: Time (s): cpu = 00:00:21 ; elapsed = 00:00:11 . Memory (MB): peak = 2029.395 ; gain = 8.004 ; free physical = 10167 ; free virtual = 15411 # set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py] # puts $output loading libsume.. About to start the test /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/nf1_expected.pcap not found /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/nf2_expected.pcap not found /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/nf3_expected.pcap not found scheduling pkts ... done scheduling pkts ... scheduling pkts ... done scheduling pkts ... scheduling pkts ... done scheduling pkts ... scheduling pkts ... done scheduling pkts ... sending pkts ... starting barrier ... starting nftest_finish ... complete !! # set_property xsim.view {} [get_filesets sim_1] # launch_simulation -simset sim_1 -mode behavioral INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... CRITICAL WARNING: [BD 41-1356] Address block is not mapped into . Please use Address Editor to either map or exclude it. CRITICAL WARNING: [BD 41-1356] Address block is not mapped into . Please use Address Editor to either map or exclude it. CRITICAL WARNING: [BD 41-1356] Address block is not mapped into . Please use Address Editor to either map or exclude it. CRITICAL WARNING: [BD 41-1356] Address block is not mapped into . Please use Address Editor to either map or exclude it. CRITICAL WARNING: [BD 41-1356] Address block is not mapped into . Please use Address Editor to either map or exclude it. CRITICAL WARNING: [BD 41-1356] Address block is not mapped into . Please use Address Editor to either map or exclude it. CRITICAL WARNING: [BD 41-1356] Address block is not mapped into . Please use Address Editor to either map or exclude it. CRITICAL WARNING: [BD 41-1356] Address block is not mapped into . Please use Address Editor to either map or exclude it. Wrote : VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/sim/control_sub.v VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hdl/control_sub_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_clock_converter_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/xbar . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s00_mmu . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m07_couplers/m07_data_fifo . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m06_couplers/m06_data_fifo . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m05_couplers/m05_data_fifo . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m04_couplers/m04_data_fifo . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m03_couplers/m03_data_fifo . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m02_couplers/m02_data_fifo . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m01_couplers/m01_data_fifo . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m00_couplers/m00_data_fifo . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s00_couplers/s00_data_fifo . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s00_couplers/auto_pc . Exporting to file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hw_handoff/control_sub.hwh Generated Block Design Tcl file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hw_handoff/control_sub_bd.tcl Generated Hardware Definition File /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.hwdef INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim' INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/opt/Xilinx/Vivado/2018.2/data/xsim/xsim.ini' copied to run dir:'/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... INFO: [SIM-utils-43] Exported '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/id_rom16x32.coe' INFO: [SIM-utils-43] Exported '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/identifier_ip.mif' INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... INFO: [USF-XSim-101] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim' xvlog --incr --relax -prj top_tb_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/barrier_ip/hdl/barrier.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module barrier INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/barrier_ip/sim/barrier_ip.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module barrier_ip INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/simulation/fifo_generator_vlog_beh.v" into library fifo_generator_v13_2_2 INFO: [VRFC 10-311] analyzing module fifo_generator_vlog_beh INFO: [VRFC 10-2458] undeclared symbol wr_rst_busy_i, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/simulation/fifo_generator_vlog_beh.v:1249] INFO: [VRFC 10-2458] undeclared symbol wr_eop_ad, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/simulation/fifo_generator_vlog_beh.v:1331] INFO: [VRFC 10-2458] undeclared symbol rd_eop_ad, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/simulation/fifo_generator_vlog_beh.v:1332] INFO: [VRFC 10-2458] undeclared symbol rd_rst_busy_axis, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/simulation/fifo_generator_vlog_beh.v:1574] INFO: [VRFC 10-2458] undeclared symbol rd_rst_busy_wach, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/simulation/fifo_generator_vlog_beh.v:2099] INFO: [VRFC 10-2458] undeclared symbol rd_rst_busy_wdch, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/simulation/fifo_generator_vlog_beh.v:2319] INFO: [VRFC 10-2458] undeclared symbol rd_rst_busy_wrch, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/simulation/fifo_generator_vlog_beh.v:2486] INFO: [VRFC 10-2458] undeclared symbol rd_rst_busy_rach, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/simulation/fifo_generator_vlog_beh.v:2866] INFO: [VRFC 10-2458] undeclared symbol rd_rst_busy_rdch, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/simulation/fifo_generator_vlog_beh.v:3099] INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_CONV_VER INFO: [VRFC 10-2458] undeclared symbol safety_ckt_rd_rst, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/simulation/fifo_generator_vlog_beh.v:4153] INFO: [VRFC 10-2458] undeclared symbol safety_ckt_rd_rst, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/simulation/fifo_generator_vlog_beh.v:4361] INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_sync_stage INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_bhv_ver_as INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_beh_ver_ll_afifo INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_bhv_ver_ss INFO: [VRFC 10-2458] undeclared symbol srst_wrst_busy, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/simulation/fifo_generator_vlog_beh.v:7793] INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_bhv_ver_preload0 INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_axic_reg_slice INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/hdl/fifo_generator_v13_2_rfs.v" into library fifo_generator_v13_2_2 INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2 INFO: [VRFC 10-2458] undeclared symbol sleep_i, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/hdl/fifo_generator_v13_2_rfs.v:519] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/sim/control_sub_axi_clock_converter_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub_axi_clock_converter_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/ip/control_sub_xbar_0/sim/control_sub_xbar_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub_xbar_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/ip/control_sub_s00_mmu_0/sim/control_sub_s00_mmu_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub_s00_mmu_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/ip/control_sub_m07_data_fifo_0/sim/control_sub_m07_data_fifo_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub_m07_data_fifo_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/ip/control_sub_m06_data_fifo_0/sim/control_sub_m06_data_fifo_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub_m06_data_fifo_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/ip/control_sub_m05_data_fifo_0/sim/control_sub_m05_data_fifo_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub_m05_data_fifo_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/ip/control_sub_m04_data_fifo_0/sim/control_sub_m04_data_fifo_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub_m04_data_fifo_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/ip/control_sub_m03_data_fifo_0/sim/control_sub_m03_data_fifo_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub_m03_data_fifo_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/ip/control_sub_m02_data_fifo_0/sim/control_sub_m02_data_fifo_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub_m02_data_fifo_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/ip/control_sub_m01_data_fifo_0/sim/control_sub_m01_data_fifo_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub_m01_data_fifo_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/ip/control_sub_m00_data_fifo_0/sim/control_sub_m00_data_fifo_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub_m00_data_fifo_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/ip/control_sub_s00_data_fifo_0/sim/control_sub_s00_data_fifo_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub_s00_data_fifo_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/ip/control_sub_auto_pc_0/sim/control_sub_auto_pc_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub_auto_pc_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/bd/control_sub/sim/control_sub.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module control_sub INFO: [VRFC 10-311] analyzing module control_sub_axi_interconnect_0_0 INFO: [VRFC 10-311] analyzing module m00_couplers_imp_35MSE9 INFO: [VRFC 10-311] analyzing module m01_couplers_imp_159MA5B INFO: [VRFC 10-311] analyzing module m02_couplers_imp_1UHPQGS INFO: [VRFC 10-311] analyzing module m03_couplers_imp_V7OM1U INFO: [VRFC 10-311] analyzing module m04_couplers_imp_73P722 INFO: [VRFC 10-311] analyzing module m05_couplers_imp_1194TWK INFO: [VRFC 10-311] analyzing module m06_couplers_imp_1YASCCN INFO: [VRFC 10-311] analyzing module m07_couplers_imp_RC6YHL INFO: [VRFC 10-311] analyzing module s00_couplers_imp_1S77UJ5 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip4/hdl/axis_sim_record.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module axis_sim_record WARNING: [VRFC 10-756] identifier state is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip4/hdl/axis_sim_record.v:93] WARNING: [VRFC 10-756] identifier ready_count is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip4/hdl/axis_sim_record.v:94] WARNING: [VRFC 10-756] identifier not_ready_count is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip4/hdl/axis_sim_record.v:95] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip4/sim/axis_sim_record_ip4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module axis_sim_record_ip4 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip3/hdl/axis_sim_record.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module axis_sim_record WARNING: [VRFC 10-756] identifier state is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip3/hdl/axis_sim_record.v:93] WARNING: [VRFC 10-756] identifier ready_count is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip3/hdl/axis_sim_record.v:94] WARNING: [VRFC 10-756] identifier not_ready_count is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip3/hdl/axis_sim_record.v:95] WARNING: [VRFC 10-2845] overwriting previous definition of module axis_sim_record [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip3/hdl/axis_sim_record.v:59] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip3/sim/axis_sim_record_ip3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module axis_sim_record_ip3 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip2/hdl/axis_sim_record.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module axis_sim_record WARNING: [VRFC 10-756] identifier state is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip2/hdl/axis_sim_record.v:93] WARNING: [VRFC 10-756] identifier ready_count is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip2/hdl/axis_sim_record.v:94] WARNING: [VRFC 10-756] identifier not_ready_count is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip2/hdl/axis_sim_record.v:95] WARNING: [VRFC 10-2845] overwriting previous definition of module axis_sim_record [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip2/hdl/axis_sim_record.v:59] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip2/sim/axis_sim_record_ip2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module axis_sim_record_ip2 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip1/hdl/axis_sim_record.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module axis_sim_record WARNING: [VRFC 10-756] identifier state is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip1/hdl/axis_sim_record.v:93] WARNING: [VRFC 10-756] identifier ready_count is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip1/hdl/axis_sim_record.v:94] WARNING: [VRFC 10-756] identifier not_ready_count is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip1/hdl/axis_sim_record.v:95] WARNING: [VRFC 10-2845] overwriting previous definition of module axis_sim_record [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip1/hdl/axis_sim_record.v:59] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip1/sim/axis_sim_record_ip1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module axis_sim_record_ip1 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module axis_sim_record WARNING: [VRFC 10-756] identifier state is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:93] WARNING: [VRFC 10-756] identifier ready_count is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:94] WARNING: [VRFC 10-756] identifier not_ready_count is used before its declaration [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:95] WARNING: [VRFC 10-2845] overwriting previous definition of module axis_sim_record [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:59] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/sim/axis_sim_record_ip0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module axis_sim_record_ip0 INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/sim/identifier_ip.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module identifier_ip INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_small_fifo.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sss_small_fifo INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_fallthrough_small_fifo.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sss_fallthrough_small_fifo INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/small_fifo.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module small_fifo INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/fallthrough_small_fifo.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module fallthrough_small_fifo INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues_cpu_regs.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sss_output_queues_cpu_regs INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sss_output_queues INFO: [VRFC 10-2458] undeclared symbol resetn_sync, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:754] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/sim/sss_output_queues_ip.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sss_output_queues_ip INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/axis_infrastructure_v1_1_0/hdl/axis_infrastructure_v1_1_vl_rfs.v" into library axis_infrastructure_v1_1_0 INFO: [VRFC 10-311] analyzing module axis_infrastructure_v1_1_0_mux_enc INFO: [VRFC 10-311] analyzing module axis_infrastructure_v1_1_0_util_aclken_converter INFO: [VRFC 10-311] analyzing module axis_infrastructure_v1_1_0_util_aclken_converter_wrapper INFO: [VRFC 10-311] analyzing module axis_infrastructure_v1_1_0_util_axis2vector INFO: [VRFC 10-311] analyzing module axis_infrastructure_v1_1_0_util_vector2axis INFO: [VRFC 10-311] analyzing module axis_infrastructure_v1_1_0_clock_synchronizer INFO: [VRFC 10-311] analyzing module axis_infrastructure_v1_1_0_cdc_handshake INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v" into library fifo_generator_v13_2_2 INFO: [VRFC 10-311] analyzing module fifo_generator_vlog_beh INFO: [VRFC 10-2458] undeclared symbol wr_rst_busy_i, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:1249] INFO: [VRFC 10-2458] undeclared symbol wr_eop_ad, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:1331] INFO: [VRFC 10-2458] undeclared symbol rd_eop_ad, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:1332] INFO: [VRFC 10-2458] undeclared symbol rd_rst_busy_axis, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:1574] INFO: [VRFC 10-2458] undeclared symbol rd_rst_busy_wach, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:2099] INFO: [VRFC 10-2458] undeclared symbol rd_rst_busy_wdch, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:2319] INFO: [VRFC 10-2458] undeclared symbol rd_rst_busy_wrch, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:2486] INFO: [VRFC 10-2458] undeclared symbol rd_rst_busy_rach, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:2866] INFO: [VRFC 10-2458] undeclared symbol rd_rst_busy_rdch, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:3099] WARNING: [VRFC 10-2845] overwriting previous definition of module fifo_generator_vlog_beh [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:98] INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_CONV_VER INFO: [VRFC 10-2458] undeclared symbol safety_ckt_rd_rst, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:4153] INFO: [VRFC 10-2458] undeclared symbol safety_ckt_rd_rst, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:4361] WARNING: [VRFC 10-2845] overwriting previous definition of module fifo_generator_v13_2_2_CONV_VER [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:3366] INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_sync_stage WARNING: [VRFC 10-2845] overwriting previous definition of module fifo_generator_v13_2_2_sync_stage [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:4938] INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_bhv_ver_as WARNING: [VRFC 10-2845] overwriting previous definition of module fifo_generator_v13_2_2_bhv_ver_as [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:4959] INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_beh_ver_ll_afifo WARNING: [VRFC 10-2845] overwriting previous definition of module fifo_generator_v13_2_2_beh_ver_ll_afifo [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:6937] INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_bhv_ver_ss INFO: [VRFC 10-2458] undeclared symbol srst_wrst_busy, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:7793] WARNING: [VRFC 10-2845] overwriting previous definition of module fifo_generator_v13_2_2_bhv_ver_ss [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:7065] INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_bhv_ver_preload0 WARNING: [VRFC 10-2845] overwriting previous definition of module fifo_generator_v13_2_2_bhv_ver_preload0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:9206] INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2_axic_reg_slice WARNING: [VRFC 10-2845] overwriting previous definition of module fifo_generator_v13_2_2_axic_reg_slice [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/simulation/fifo_generator_vlog_beh.v:10324] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/hdl/fifo_generator_v13_2_rfs.v" into library fifo_generator_v13_2_2 INFO: [VRFC 10-311] analyzing module fifo_generator_v13_2_2 INFO: [VRFC 10-2458] undeclared symbol sleep_i, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/hdl/fifo_generator_v13_2_rfs.v:519] WARNING: [VRFC 10-2845] overwriting previous definition of module fifo_generator_v13_2_2 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/hdl/fifo_generator_v13_2_rfs.v:74] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/axis_data_fifo_v1_1_18/hdl/axis_data_fifo_v1_1_vl_rfs.v" into library axis_data_fifo_v1_1_18 INFO: [VRFC 10-311] analyzing module axis_data_fifo_v1_1_18_axis_data_fifo INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module S_CONTROLLER_SimpleSumeSwitch INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_EGRESS WARNING: [VRFC 10-2654] begin/end is required for generate-for in this mode of verilog [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v:111] WARNING: [VRFC 10-2654] begin/end is required for generate-for in this mode of verilog [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v:110] WARNING: [VRFC 10-2654] begin/end is required for generate-for in this mode of verilog [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v:112] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_INGRESS WARNING: [VRFC 10-2654] begin/end is required for generate-for in this mode of verilog [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:218] WARNING: [VRFC 10-2654] begin/end is required for generate-for in this mode of verilog [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:217] WARNING: [VRFC 10-2654] begin/end is required for generate-for in this mode of verilog [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:219] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module S_RESETTER_control INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module S_RESETTER_line INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module S_RESETTER_lookup INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_TopDeparser INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopDeparser INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopParser INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module S_SYNCER_for__OUT_ INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module TopDeparser_t INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module TopDeparser_t_Engine INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_remove INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_dst_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_src_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_ethertype INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_task INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_ingress_port INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_ethertype INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_table_id INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_version INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ihl INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_diff_serv INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ecn INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_totalLen INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_identification INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_flags INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_fragOffset INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ttl INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_protocol INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_checksum INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_src_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_dst_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_version INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_traffic_class INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_flow_label INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_payload_length INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_next_header INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_hop_limit INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_src_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_dst_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_hw_type INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_protocol INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_hw_size INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_protocol_size INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_opcode INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_src_mac_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_src_ipv4_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_dst_mac_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_dst_ipv4_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_src_port INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_dst_port INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_seqNo INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ackNo INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_data_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_res INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_cwr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ece INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_urg INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ack INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_psh INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_rst INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_syn INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_fin INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_window INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_checksum INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_urgentPtr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_src_port INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_dst_port INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_payload_length INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_checksum INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_type INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_code INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_checksum INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_type INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_code INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_checksum INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_router INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_solicitated INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_override INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_reserved INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_target_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_type INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_ll_length INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_mac_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataMux INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module TopParser_t INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module TopParser_t_Engine INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0 INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ErrorCheck INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ExtractShifter INFO: [VRFC 10-311] analyzing module TopParser_t_start INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_icmp INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_icmp6 INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_icmp6_na_ns INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_ipv4 INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_udp_v6 INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_udp_v4 INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_tcp_v6 INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_tcp_v4 INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_v4sum INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_v6sum INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_headerdiff INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_dst_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_src_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_ethertype INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_reject INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_TupleForward INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1 INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ErrorCheck INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ExtractShifter INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4 INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_version INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_ihl INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_diff_serv INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_ecn INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_totalLen INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_identification INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_flags INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_fragOffset INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_ttl INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_protocol INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_src_addr INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_dst_addr INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_meta_length_without_ip_header INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6 INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_version INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_traffic_class INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_flow_label INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_payload_length INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_next_header INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_hop_limit INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_src_addr INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_dst_addr INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_meta_length_without_ip_header INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_arp INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_hw_type INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_protocol INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_hw_size INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_protocol_size INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_opcode INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_src_mac_addr INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_src_ipv4_addr INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_dst_mac_addr INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_dst_ipv4_addr INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_TupleForward INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2 INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_ErrorCheck INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_ExtractShifter INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6 INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_type INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_code INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_tcp INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_src_port INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_dst_port INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_seqNo INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_ackNo INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_data_offset INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_res INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_cwr INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_ece INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_urg INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_ack INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_psh INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_rst INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_syn INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_fin INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_window INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_urgentPtr INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_udp INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_src_port INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_dst_port INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_payload_length INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_icmp INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_type INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_code INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_TupleForward INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3 INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_ErrorCheck INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_ExtractShifter INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_router INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_solicitated INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_override INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_reserved INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_target_addr INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_type INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_ll_length INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_mac_addr INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_TupleForward INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_4 INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_4_ErrorCheck INFO: [VRFC 10-311] analyzing module TopParser_t_accept INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_increment_offset INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_Engine INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_dummy_table_for_netpfga_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_dummy_table_for_netpfga_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_dummy_table_for_netpfga_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_1 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_sume_metadata_dst_port INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port_0_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port_0_sec_compute_sume_metadata_dst_port INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port_0_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port_0_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_2 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_increment_offset INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.vp" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_Engine INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_EngineStage_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_dummy_table_for_netpfga_req_lookup_request_key INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_increment_offset INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/dummy_table_for_netpfga_t.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/dummy_table_for_netpfga_t.vp" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Wrap INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_IntTop INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Lookup INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Hash_Lookup INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_RamR1RW1 INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Cam INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Update INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Hash_Update INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Randmod4 INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Randmod4_Rnd INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Randmod5 INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Randmod5_Rnd INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_csr INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/sume_to_sdnet.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sume_to_sdnet INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_cdc.sv" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module xpm_cdc_single INFO: [VRFC 10-311] analyzing module xpm_cdc_gray INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_fifo.sv" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module xpm_fifo_base INFO: [VRFC 10-311] analyzing module xpm_fifo_rst INFO: [VRFC 10-311] analyzing module xpm_counter_updn INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit INFO: [VRFC 10-311] analyzing module xpm_fifo_sync INFO: [VRFC 10-311] analyzing module xpm_fifo_async INFO: [VRFC 10-311] analyzing module xpm_fifo_axis INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module xpm_memory_base INFO: [VRFC 10-311] analyzing module asym_bwe_bb INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram INFO: [VRFC 10-311] analyzing module xpm_memory_dprom INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram INFO: [VRFC 10-311] analyzing module xpm_memory_spram INFO: [VRFC 10-311] analyzing module xpm_memory_sprom INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module nf_sume_sdnet INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/sim/nf_sume_sdnet_ip.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module nf_sume_sdnet_ip INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module small_fifo WARNING: [VRFC 10-2845] overwriting previous definition of module small_fifo [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/fallthrough_small_fifo.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module fallthrough_small_fifo WARNING: [VRFC 10-2845] overwriting previous definition of module fallthrough_small_fifo [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/fallthrough_small_fifo.v:46] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter_cpu_regs.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module input_arbiter_cpu_regs INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module input_arbiter INFO: [VRFC 10-2458] undeclared symbol resetn_sync, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter.v:390] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/sim/input_arbiter_ip.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module input_arbiter_ip INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module clk_wiz_ip_clk_wiz INFO: [VRFC 10-2458] undeclared symbol clk_out1_clk_wiz_ip_en_clk, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:207] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module clk_wiz_ip INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/axi_clocking.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module axi_clocking INFO: [VRFC 10-2458] undeclared symbol clkin1, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/axi_clocking.v:64] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module nf_datapath INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_sim.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top_sim INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top_tb INFO: [VRFC 10-2458] undeclared symbol pcie_7x_mgt_rxn, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v:115] INFO: [VRFC 10-2458] undeclared symbol pcie_7x_mgt_rxp, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v:116] INFO: [VRFC 10-2458] undeclared symbol pcie_7x_mgt_txn, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v:117] INFO: [VRFC 10-2458] undeclared symbol pcie_7x_mgt_txp, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v:118] INFO: [VRFC 10-2458] undeclared symbol rxp, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v:121] INFO: [VRFC 10-2458] undeclared symbol rxn, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v:122] INFO: [VRFC 10-2458] undeclared symbol txp, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v:123] INFO: [VRFC 10-2458] undeclared symbol txn, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v:124] INFO: [VRFC 10-2458] undeclared symbol i2c_clk, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v:137] INFO: [VRFC 10-2458] undeclared symbol i2c_data, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v:138] INFO: [VRFC 10-2458] undeclared symbol si5324_rst_n, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v:139] INFO: [VRFC 10-2458] undeclared symbol led_0, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v:146] INFO: [VRFC 10-2458] undeclared symbol led_1, assumed default net type wire [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top_tb.v:147] INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl xvhdl --incr --relax -prj top_tb_vhdl.prj INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/lib_pkg_v1_0_2/hdl/lib_pkg_v1_0_rfs.vhd" into library lib_pkg_v1_0_2 INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/lib_srl_fifo_v1_0_2/hdl/lib_srl_fifo_v1_0_rfs.vhd" into library lib_srl_fifo_v1_0_2 INFO: [VRFC 10-307] analyzing entity cntr_incr_decr_addn_f INFO: [VRFC 10-307] analyzing entity dynshreg_f INFO: [VRFC 10-307] analyzing entity srl_fifo_rbu_f INFO: [VRFC 10-307] analyzing entity srl_fifo_f INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_sim_transactor_ip/hdl/axis_sim_pkg/axis_sim_pkg.vhd" into library xil_defaultlib INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_sim_transactor_ip/hdl/transactor_fifos.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity transactor_fifos INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_sim_transactor_ip/hdl/axi_sim_transactor.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity axi_sim_transactor INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_sim_transactor_ip/sim/axi_sim_transactor_ip.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity axi_sim_transactor_ip INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ipshared/7aff/hdl/fifo_generator_v13_2_rfs.vhd" into library fifo_generator_v13_2_2 INFO: [VRFC 10-307] analyzing entity input_blk INFO: [VRFC 10-307] analyzing entity output_blk INFO: [VRFC 10-307] analyzing entity shft_wrapper INFO: [VRFC 10-307] analyzing entity shft_ram INFO: [VRFC 10-307] analyzing entity wr_pf_as INFO: [VRFC 10-307] analyzing entity wr_pf_ss INFO: [VRFC 10-307] analyzing entity rd_pe_as INFO: [VRFC 10-307] analyzing entity rd_pe_ss INFO: [VRFC 10-307] analyzing entity synchronizer_ff INFO: [VRFC 10-307] analyzing entity delay INFO: [VRFC 10-307] analyzing entity bin_cntr INFO: [VRFC 10-307] analyzing entity clk_x_pntrs_builtin INFO: [VRFC 10-307] analyzing entity logic_builtin INFO: [VRFC 10-307] analyzing entity builtin_prim INFO: [VRFC 10-307] analyzing entity builtin_extdepth INFO: [VRFC 10-307] analyzing entity builtin_top INFO: [VRFC 10-307] analyzing entity reset_builtin INFO: [VRFC 10-307] analyzing entity builtin_prim_v6 INFO: [VRFC 10-307] analyzing entity builtin_extdepth_v6 INFO: [VRFC 10-307] analyzing entity builtin_extdepth_low_latency INFO: [VRFC 10-307] analyzing entity builtin_top_v6 INFO: [VRFC 10-307] analyzing entity fifo_generator_v13_2_2_builtin INFO: [VRFC 10-307] analyzing entity bram_sync_reg INFO: [VRFC 10-307] analyzing entity bram_fifo_rstlogic INFO: [VRFC 10-307] analyzing entity reset_blk_ramfifo INFO: [VRFC 10-307] analyzing entity axi_reg_slice INFO: [VRFC 10-307] analyzing entity fifo_generator_top INFO: [VRFC 10-307] analyzing entity fifo_generator_v13_2_2_synth INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip4/hdl/axis_sim_pkg/axis_sim_pkg.vhd" into library xil_defaultlib INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip4/hdl/axis_sim_stim.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity axis_sim_stim INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip4/sim/axis_sim_stim_ip4.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity axis_sim_stim_ip4 INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip3/hdl/axis_sim_pkg/axis_sim_pkg.vhd" into library xil_defaultlib INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip3/hdl/axis_sim_stim.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity axis_sim_stim INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip3/sim/axis_sim_stim_ip3.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity axis_sim_stim_ip3 INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip2/hdl/axis_sim_pkg/axis_sim_pkg.vhd" into library xil_defaultlib INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip2/hdl/axis_sim_stim.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity axis_sim_stim INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip2/sim/axis_sim_stim_ip2.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity axis_sim_stim_ip2 INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip1/hdl/axis_sim_pkg/axis_sim_pkg.vhd" into library xil_defaultlib INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip1/hdl/axis_sim_stim.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity axis_sim_stim INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip1/sim/axis_sim_stim_ip1.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity axis_sim_stim_ip1 INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip0/hdl/axis_sim_pkg/axis_sim_pkg.vhd" into library xil_defaultlib INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip0/hdl/axis_sim_stim.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity axis_sim_stim INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_stim_ip0/sim/axis_sim_stim_ip0.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity axis_sim_stim_ip0 INFO: [VRFC 10-163] Analyzing VHDL file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.ip_user_files/ipstatic/fifo_generator_v13_2_2/hdl/fifo_generator_v13_2_rfs.vhd" into library fifo_generator_v13_2_2 INFO: [VRFC 10-307] analyzing entity input_blk INFO: [VRFC 10-307] analyzing entity output_blk INFO: [VRFC 10-307] analyzing entity shft_wrapper INFO: [VRFC 10-307] analyzing entity shft_ram INFO: [VRFC 10-307] analyzing entity wr_pf_as INFO: [VRFC 10-307] analyzing entity wr_pf_ss INFO: [VRFC 10-307] analyzing entity rd_pe_as INFO: [VRFC 10-307] analyzing entity rd_pe_ss INFO: [VRFC 10-307] analyzing entity synchronizer_ff INFO: [VRFC 10-307] analyzing entity delay INFO: [VRFC 10-307] analyzing entity bin_cntr INFO: [VRFC 10-307] analyzing entity clk_x_pntrs_builtin INFO: [VRFC 10-307] analyzing entity logic_builtin INFO: [VRFC 10-307] analyzing entity builtin_prim INFO: [VRFC 10-307] analyzing entity builtin_extdepth INFO: [VRFC 10-307] analyzing entity builtin_top INFO: [VRFC 10-307] analyzing entity reset_builtin INFO: [VRFC 10-307] analyzing entity builtin_prim_v6 INFO: [VRFC 10-307] analyzing entity builtin_extdepth_v6 INFO: [VRFC 10-307] analyzing entity builtin_extdepth_low_latency INFO: [VRFC 10-307] analyzing entity builtin_top_v6 INFO: [VRFC 10-307] analyzing entity fifo_generator_v13_2_2_builtin INFO: [VRFC 10-307] analyzing entity bram_sync_reg INFO: [VRFC 10-307] analyzing entity bram_fifo_rstlogic INFO: [VRFC 10-307] analyzing entity reset_blk_ramfifo INFO: [VRFC 10-307] analyzing entity axi_reg_slice INFO: [VRFC 10-307] analyzing entity fifo_generator_top INFO: [VRFC 10-307] analyzing entity fifo_generator_v13_2_2_synth run_program: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2136.637 ; gain = 0.000 ; free physical = 10042 ; free virtual = 15334 INFO: [USF-XSim-69] 'compile' step finished in '6' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim' Vivado Simulator 2018.2 Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto ab4d7644e7344cc5bb8bc6cfafbf22d0 --incr --debug typical --relax --mt 8 -d SIMULATION=1 -L xil_defaultlib -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L axi_infrastructure_v1_1_0 -L fifo_generator_v13_2_2 -L axi_clock_converter_v2_1_16 -L generic_baseblocks_v2_1_0 -L axi_register_slice_v2_1_17 -L axi_data_fifo_v2_1_16 -L axi_crossbar_v2_1_18 -L axi_mmu_v2_1_15 -L axi_protocol_converter_v2_1_17 -L blk_mem_gen_v8_4_1 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v1_1_18 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration ERROR: [VRFC 10-426] cannot find port tuple_out_sume_metadata_DATA on this module [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:219] ERROR: [VRFC 10-426] cannot find port tuple_out_sume_metadata_VALID on this module [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:218] ERROR: [VRFC 10-426] cannot find port tuple_in_sume_metadata_DATA on this module [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:185] ERROR: [VRFC 10-426] cannot find port tuple_in_sume_metadata_VALID on this module [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:184] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:332] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:343] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:354] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:436] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:474] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:502] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:533] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:561] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:603] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:617] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:640] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:662] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:704] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:778] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:868] INFO: [#UNDEF] Sorry, too many errors.. ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '0' seconds INFO: [USF-XSim-99] Step results log file:'/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. launch_simulation: Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 2136.637 ; gain = 107.242 ; free physical = 10040 ; free virtual = 15334 ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. while executing "launch_simulation -simset sim_1 -mode behavioral" (file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 181) INFO: [Common 17-206] Exiting Vivado at Mon Jul 22 22:32:11 2019... Makefile:120: recipe for target 'sim' failed make: *** [sim] Error 1 make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test' cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.log': No such file or directory NetFPGA environment: Root dir: /home/nico/projects/P4-NetFPGA Project name: simple_sume_switch Project dir: /tmp/nico/test/simple_sume_switch Work dir: /tmp/nico 512 === Work directory is /tmp/nico/test/simple_sume_switch === Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default === Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']