+ date Mon Jul 29 16:29:50 CEST 2019 + cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4 + make make -C src/ clean make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src' rm -f *.sdnet *.tbl .sdnet_switch_info.dat make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src' make -C testdata/ clean make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata' rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata' rm -rf nf_sume_sdnet_ip/ rm -f rm -f sw/config_tables.c make -C src/ make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src' p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4 actions_egress.p4(51): warning: Table v6_networks is not used; removing table v6_networks { ^^^^^^^^^^^ actions_egress.p4(77): warning: Table v4_networks is not used; removing table v4_networks { ^^^^^^^^^^^ actions_nat64_generic.p4(159): warning: Table nat64 is not used; removing table nat64 { ^^^^^ actions_nat64_generic.p4(177): warning: Table nat46 is not used; removing table nat46 { ^^^^^ minip4_solution.p4(19): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when RealParser terminates out metadata meta, ^^^^ minip4_solution.p4(16) parser RealParser( ^^^^^^^^^^ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src' make -C testdata/ make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata' ./gen_testdata.py Applying pkt on nf0 at 1: Applying pkt on nf1 at 2: Applying pkt on nf2 at 3: Applying pkt on nf3 at 4: nf0_applied times: [1] nf1_applied times: [2] nf2_applied times: [3] nf3_applied times: [4] /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata' sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts Xilinx SDNet Compiler version 2018.2, build 2342300 Compilation successful /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_externs.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ ./testdata/ ./sw/ --base_address 0x44020000 /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_API.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000 /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_CLI.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000 make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI' cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o libcam.so libcam.o CAM.o -lsumereg make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI' # The following command only applies if running P4_SWITCH Questa Simulation with Ubuntu sed -i 's/vsim/vsim \-ldflags \"\-B\/usr\/lib\/x86\_64\-linux-gnu\"/g' nf_sume_sdnet_ip/SimpleSumeSwitch/questa.bash # modify the P4_SWITCH_tb so that it writes the table configuration writes to a file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/modify_P4_SWITCH_tb.py nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv # Fix introduced for SDNet 2017.4 sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash # Fix introduced for SDNet 2018.2 sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/ cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/ cp testdata/*.axi nf_sume_sdnet_ip/SimpleSumeSwitch/ + date Mon Jul 29 16:30:01 CEST 2019 + cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch + ./vivado_sim.bash + find -name '*.v' -o -name '*.vp' -o -name '*.sv' + xargs -I % /opt/Xilinx/Vivado/2018.2/bin/xvlog -sv % INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v" into library work INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp" into library work INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_Engine INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_dummy_table_for_netpfga_0_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_dummy_table_for_netpfga_0_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_dummy_table_for_netpfga_0_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_1 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_select_port_by_type_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_select_port_by_type_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_select_port_by_type_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_send_to_port1_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_send_to_port1_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_send_to_port1_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_2 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_19_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_19_sec_compute_TopPipe_fl_realmain_v6_out_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_19_sec_compute_TopPipe_fl_realmain_v4_out_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_19_sec_compute_TopPipe_fl_realmain_v6_src_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_19_sec_compute_TopPipe_fl_realmain_v6_dst_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_19_sec_compute_TopPipe_fl_realmain_nat64_prefix_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_19_sec_compute_TopPipe_fl_realmain_v4_dst_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_19_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_19_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_3 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_12 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_12_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_12_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_4 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_11 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_11_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_11_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_TopPipe_fl_realmain_src_1 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_TopPipe_fl_realmain_dst_1 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_isValid INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_version INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_ihl INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_diff_serv INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_ecn INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_totalLen INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_identification INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_flags INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_fragOffset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_ttl INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_protocol INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_src_addr INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_dst_addr INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ethernet_ethertype INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_user_metadata_chk_ipv4 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv6_isValid INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_5 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_4 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_4_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_4_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_TopPipe_fl_realmain_src_2 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_TopPipe_fl_realmain_dst_2 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_p_ipv6_isValid INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_p_ipv4_isValid INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_p_ethernet_ethertype INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_p_ipv6_dst_addr INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_p_ipv6_src_addr INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_p_ipv6_version INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_p_ipv6_traffic_class INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_p_ipv6_flow_label INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_p_ipv6_payload_length INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_p_ipv6_next_header INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_p_ipv6_hop_limit INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat46_static_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_4_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_4_sec_compute_sume_metadata_dst_port INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_4_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_4_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_6 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_10 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_10_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_10_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_sec_compute_user_metadata_v4sum INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_sec_compute_user_metadata_v6sum INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_7 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_0_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_0_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_0_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_0_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_5_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_5_sec_compute_user_metadata_v4sum INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_5_sec_compute_user_metadata_v6sum INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_5_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_5_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_8 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_10_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_10_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_10_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_10_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_3 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_3_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_3_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_9 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_9 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_9_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_9_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_10 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_9_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_9_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_9_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_9_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_11 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_12_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_12_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_12_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_12_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_2 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_2_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_2_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_12 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_8 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_8_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_8_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_13 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_11_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_11_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_11_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_11_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_3_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_3_sec_compute_p_udp_checksum INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_3_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_3_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_14 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_13_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_13_sec_compute_p_udp_checksum INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_13_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_13_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_1 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_1_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_1_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_15 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_7 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_7_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_7_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_4_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_4_sec_compute_user_metadata_v4sum INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_4_sec_compute_user_metadata_v6sum INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_4_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_4_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_16 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_5_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_5_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_5_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_5_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_6_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_6_sec_compute_user_metadata_v4sum INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_6_sec_compute_user_metadata_v6sum INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_6_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_delta_prepare_6_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_17 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_15_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_15_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_15_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_15_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_0_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_0_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_18 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_4_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_4_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_4_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_4_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_6 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_6_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_6_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_19 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_14_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_14_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_14_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_14_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_7_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_7_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_7_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_7_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_20 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_17_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_17_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_17_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_17_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_21 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_6_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_6_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_6_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_6_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_5 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_5_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_5_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_22 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_16_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_16_sec_compute_TopPipe_fl_realmain_tmp17_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_16_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_16_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_8_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_8_sec_compute_p_tcp_checksum INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_8_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_8_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_23 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_18_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_18_sec_compute_p_tcp_checksum INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_18_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_18_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_sec_compute_sume_metadata_dst_port INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_24 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_3_sec INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_3_sec_compute_sume_metadata_dst_port INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_3_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_3_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_25 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_increment_offset INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v" into library work INFO: [VRFC 10-311] analyzing module S_RESETTER_lookup INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v" into library work INFO: [VRFC 10-311] analyzing module S_RESETTER_line INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v" into library work INFO: [VRFC 10-311] analyzing module S_RESETTER_control INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp" into library work INFO: [VRFC 10-311] analyzing module TopDeparser_t_Engine INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_remove INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_20_sec INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_20_sec_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_20_sec_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_dst_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_src_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_ethertype INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_task INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_ingress_port INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_ethertype INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_table_id INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_version INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ihl INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_diff_serv INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ecn INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_totalLen INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_identification INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_flags INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_fragOffset INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ttl INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_protocol INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_checksum INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_src_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_dst_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_version INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_traffic_class INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_flow_label INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_payload_length INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_next_header INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_hop_limit INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_src_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_dst_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_hw_type INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_protocol INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_hw_size INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_protocol_size INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_opcode INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_src_mac_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_src_ipv4_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_dst_mac_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_dst_ipv4_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_src_port INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_dst_port INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_seqNo INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ackNo INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_data_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_res INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_cwr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ece INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_urg INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ack INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_psh INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_rst INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_syn INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_fin INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_window INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_checksum INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_urgentPtr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_src_port INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_dst_port INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_payload_length INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_checksum INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_type INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_code INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_checksum INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_type INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_code INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_checksum INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_router INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_solicitated INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_override INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_reserved INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_target_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataMux INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12 INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_ErrorCheck INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0 INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_insert INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_type INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_ll_length INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_mac_addr INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_FifoWriter INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DscFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DscFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_LatencyBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_PktFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_PktFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleFifo INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleFifo_RAM INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_FifoReader INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterSelect INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer_BarrelShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge_UniShifterDownMask INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge_UniShifterDownTuple INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_UniShifterDown INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_UniShifterUp INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_BidirShifterUpdate INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_BidirShifterUpdate_UniShifter2X INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataMux INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v" into library work INFO: [VRFC 10-311] analyzing module TopDeparser_t INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp" into library work INFO: [VRFC 10-311] analyzing module TopParser_t_Engine INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0 INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ErrorCheck INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ExtractShifter INFO: [VRFC 10-311] analyzing module TopParser_t_start INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ipv4_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ipv6_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_tcp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_udp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_cpu_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_na_ns_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_arp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dma_q_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf3_q_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf2_q_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf1_q_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf0_q_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_send_dig_to_cpu INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_drop INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dst_port INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_src_port INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_pkt_len INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_icmp INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_icmp6 INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_icmp6_na_ns INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_ipv4 INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_udp_v6 INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_udp_v4 INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_tcp_v6 INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_chk_tcp_v4 INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_v4sum INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_v6sum INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_headerdiff INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_digest_data_1_unused INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_dst_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_src_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_ethertype INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_reject INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_TupleForward INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1 INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ErrorCheck INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ExtractShifter INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4 INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_version INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_ihl INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_diff_serv INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_ecn INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_totalLen INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_identification INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_flags INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_fragOffset INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_ttl INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_protocol INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_src_addr INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_hdr_1_ipv4_dst_addr INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_TopParser_fl_meta_length_without_ip_header INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv4_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6 INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_version INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_traffic_class INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_flow_label INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_payload_length INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_next_header INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_hop_limit INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_src_addr INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_hdr_1_ipv6_dst_addr INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_TopParser_fl_meta_length_without_ip_header INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_ipv6_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_hw_type INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_protocol INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_hw_size INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_protocol_size INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_opcode INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_src_mac_addr INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_src_ipv4_addr INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_dst_mac_addr INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_fl_hdr_1_arp_dst_ipv4_addr INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_arp_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_TupleForward INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2 INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_ErrorCheck INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_ExtractShifter INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6 INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_TopParser_fl_hdr_1_icmp6_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_TopParser_fl_hdr_1_icmp6_type INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_TopParser_fl_hdr_1_icmp6_code INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_TopParser_fl_hdr_1_icmp6_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_src_port INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_dst_port INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_seqNo INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_ackNo INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_data_offset INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_res INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_cwr INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_ece INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_urg INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_ack INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_psh INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_rst INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_syn INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_fin INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_window INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_fl_hdr_1_tcp_urgentPtr INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_tcp_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_TopParser_fl_hdr_1_udp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_TopParser_fl_hdr_1_udp_src_port INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_TopParser_fl_hdr_1_udp_dst_port INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_TopParser_fl_hdr_1_udp_payload_length INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_TopParser_fl_hdr_1_udp_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_udp_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_TopParser_fl_hdr_1_icmp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_TopParser_fl_hdr_1_icmp_type INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_TopParser_fl_hdr_1_icmp_code INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_TopParser_fl_hdr_1_icmp_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_TupleForward INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3 INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_ErrorCheck INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_ExtractShifter INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_na_ns_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_na_ns_router INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_na_ns_solicitated INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_na_ns_override INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_na_ns_reserved INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_na_ns_target_addr INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_type INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_ll_length INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_mac_addr INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_TopParser_extracts_size INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_RealParser_icmp6_neighbor_solicitation_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_TupleForward INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_4 INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_4_ErrorCheck INFO: [VRFC 10-311] analyzing module TopParser_t_start_0 INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ethernet_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ethernet_dst_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ethernet_src_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ethernet_ethertype INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_version INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_ihl INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_diff_serv INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_ecn INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_totalLen INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_identification INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_flags INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_fragOffset INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_ttl INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_protocol INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_src_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv4_dst_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_version INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_traffic_class INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_flow_label INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_payload_length INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_next_header INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_hop_limit INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_src_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_ipv6_dst_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_src_port INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_dst_port INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_seqNo INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_ackNo INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_data_offset INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_res INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_cwr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_ece INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_urg INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_ack INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_psh INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_rst INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_syn INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_fin INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_window INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_tcp_urgentPtr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_udp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_udp_src_port INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_udp_dst_port INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_udp_payload_length INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_udp_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp_type INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp_code INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_cpu_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_cpu_task INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_cpu_ingress_port INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_cpu_ethertype INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_cpu_table_id INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_type INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_code INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_checksum INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_na_ns_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_na_ns_router INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_na_ns_solicitated INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_na_ns_override INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_na_ns_reserved INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_na_ns_target_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_option_link_layer_addr_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_option_link_layer_addr_type INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_option_link_layer_addr_ll_length INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_icmp6_option_link_layer_addr_mac_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_isValid INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_hw_type INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_protocol INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_hw_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_protocol_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_opcode INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_src_mac_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_src_ipv4_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_dst_mac_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_p_arp_dst_ipv4_addr INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_ingress_port INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_task INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_switch_task INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_icmp6_na_ns INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_icmp6 INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_icmp INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_ipv4 INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_udp_v4 INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_udp_v6 INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_tcp_v4 INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_chk_tcp_v6 INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_length_without_ip_header INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_cast_length INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_v4sum INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_v6sum INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_headerdiff INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_user_metadata_table_id INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_digest_data_unused INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_dma_q_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_nf3_q_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_nf2_q_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_nf1_q_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_nf0_q_size INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_send_dig_to_cpu INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_drop INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_dst_port INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_src_port INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_sume_metadata_pkt_len INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_start_0_compute_control_increment_offset INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_5 INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_5_ErrorCheck INFO: [VRFC 10-311] analyzing module TopParser_t_accept INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_increment_offset INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v" into library work INFO: [VRFC 10-311] analyzing module TopParser_t INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v" into library work INFO: [VRFC 10-311] analyzing module glbl INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv" into library work INFO: [VRFC 10-311] analyzing module xpm_fifo_base INFO: [VRFC 10-311] analyzing module xpm_fifo_rst INFO: [VRFC 10-311] analyzing module xpm_counter_updn INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit INFO: [VRFC 10-311] analyzing module xpm_fifo_sync INFO: [VRFC 10-311] analyzing module xpm_fifo_async INFO: [VRFC 10-311] analyzing module xpm_fifo_axis INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv" into library work INFO: [VRFC 10-311] analyzing module xpm_memory_base INFO: [VRFC 10-311] analyzing module asym_bwe_bb INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram INFO: [VRFC 10-311] analyzing module xpm_memory_dprom INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram INFO: [VRFC 10-311] analyzing module xpm_memory_spram INFO: [VRFC 10-311] analyzing module xpm_memory_sprom INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv" into library work INFO: [VRFC 10-311] analyzing module xpm_cdc_single INFO: [VRFC 10-311] analyzing module xpm_cdc_gray INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request.v" into library work INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request.vp" into library work INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp" into library work ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37] INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.v" into library work INFO: [VRFC 10-311] analyzing module S_CONTROLLER_SimpleSumeSwitch INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.vp" into library work INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_Engine INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_EngineStage_0 INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_realmain_dummy_table_for_netpfga_0_req_lookup_request_key INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_nextSection INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_increment_offset INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v" into library work INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" into library work INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch_tb INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v" into library work INFO: [VRFC 10-311] analyzing module TB_System_Stim INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" into library work INFO: [VRFC 10-311] analyzing module Check INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v" into library work INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_INGRESS INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp" into library work INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp" into library work INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v" into library work INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_EGRESS INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v" into library work INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_dummy_table_for_netpfga_0_t.HDL/realmain_dummy_table_for_netpfga_0_t.vp" into library work INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t_Wrap INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t_IntTop INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t_Lookup INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t_Hash_Lookup INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t_RamR1RW1 INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t_Cam INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t_Update INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t_Hash_Update INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t_Randmod4 INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t_Randmod4_Rnd INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t_Randmod5 INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t_Randmod5_Rnd INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t_csr INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_dummy_table_for_netpfga_0_t.HDL/realmain_dummy_table_for_netpfga_0_t.v" into library work INFO: [VRFC 10-311] analyzing module realmain_dummy_table_for_netpfga_0_t INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_dummy_table_for_netpfga_0_t.HDL/xpm_memory.sv" into library work INFO: [VRFC 10-311] analyzing module xpm_memory_base INFO: [VRFC 10-311] analyzing module asym_bwe_bb INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram INFO: [VRFC 10-311] analyzing module xpm_memory_dprom INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram INFO: [VRFC 10-311] analyzing module xpm_memory_spram INFO: [VRFC 10-311] analyzing module xpm_memory_sprom INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_dummy_table_for_netpfga_0_t.HDL/xpm_cdc.sv" into library work INFO: [VRFC 10-311] analyzing module xpm_cdc_single INFO: [VRFC 10-311] analyzing module xpm_cdc_gray INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v" into library work INFO: [VRFC 10-311] analyzing module glbl INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v" into library work INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopDeparser INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v" into library work INFO: [VRFC 10-311] analyzing module S_SYNCER_for__OUT_ INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_fifo.sv" into library work INFO: [VRFC 10-311] analyzing module xpm_fifo_base INFO: [VRFC 10-311] analyzing module xpm_fifo_rst INFO: [VRFC 10-311] analyzing module xpm_counter_updn INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit INFO: [VRFC 10-311] analyzing module xpm_fifo_sync INFO: [VRFC 10-311] analyzing module xpm_fifo_async INFO: [VRFC 10-311] analyzing module xpm_fifo_axis INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv" into library work INFO: [VRFC 10-311] analyzing module xpm_memory_base INFO: [VRFC 10-311] analyzing module asym_bwe_bb INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram INFO: [VRFC 10-311] analyzing module xpm_memory_dprom INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram INFO: [VRFC 10-311] analyzing module xpm_memory_spram INFO: [VRFC 10-311] analyzing module xpm_memory_sprom INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v" into library work INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopParser INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv" into library work INFO: [VRFC 10-311] analyzing module xpm_cdc_single INFO: [VRFC 10-311] analyzing module xpm_cdc_gray INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_TopDeparser INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser + true + mkdir -p xsim.dir/xsc + find -name '*.c' + xargs /opt/Xilinx/Vivado/2018.2/bin/xsc -mt off -v 1 Turned off multi-threading. Running compilation flow /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/CAM.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" -DXILINX_SIMULATOR /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/user.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -DXILINX_SIMULATOR ./Testbench/user.c: In function ‘register_write_control’: ./Testbench/user.c:37:5: warning: implicit declaration of function ‘SV_write_control’ [-Wimplicit-function-declaration] SV_write_control(&sv_addr, &sv_data); ^~~~~~~~~~~~~~~~ ./Testbench/user.c: In function ‘register_read_control’: ./Testbench/user.c:51:5: warning: implicit declaration of function ‘SV_read_control’ [-Wimplicit-function-declaration] SV_read_control(&sv_addr, &sv_data); ^~~~~~~~~~~~~~~ ./Testbench/user.c: In function ‘CAM_Init’: ./Testbench/user.c:88:76: warning: passing argument 9 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types] if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level)) ^~~~~~~~~~~~~~ In file included from ./Testbench/user.c:7:0: ./Testbench/CAM.h:169:5: note: expected ‘void (*)(addr_t, uint32_t) {aka void (*)(long long unsigned int, unsigned int)}’ but argument is of type ‘void (*)(uint32_t, uint32_t) {aka void (*)(unsigned int, unsigned int)}’ int CAM_Init_ValidateContext( ^~~~~~~~~~~~~~~~~~~~~~~~ ./Testbench/user.c:88:92: warning: passing argument 10 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types] if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level)) ^~~~~~~~~~~~~ In file included from ./Testbench/user.c:7:0: ./Testbench/CAM.h:169:5: note: expected ‘uint32_t (*)(addr_t) {aka unsigned int (*)(long long unsigned int)}’ but argument is of type ‘uint32_t (*)(uint32_t) {aka unsigned int (*)(unsigned int)}’ int CAM_Init_ValidateContext( ^~~~~~~~~~~~~~~~~~~~~~~~ Done compilation Linking with command: /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ Running command : /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ Done linking: "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" + /opt/Xilinx/Vivado/2018.2/bin/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl Vivado Simulator 2018.2 Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl Multi-threading is on. Using 6 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module work.S_RESETTER_line Compiling module work.S_RESETTER_lookup Compiling module work.S_RESETTER_control Compiling module work.TopParser_t_EngineStage_0_ErrorC... Compiling module work.TopParser_t_EngineStage_0_Extrac... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_TopPar... Compiling module work.TopParser_t_start_compute_contro... Compiling module work.TopParser_t_start_compute_contro... Compiling module work.TopParser_t_start Compiling module work.TopParser_t_reject_compute_contr... Compiling module work.TopParser_t_reject_compute_contr... Compiling module work.TopParser_t_reject Compiling module work.TopParser_t_EngineStage_0_TupleF... Compiling module work.TopParser_t_EngineStage_0 Compiling module work.TopParser_t_EngineStage_1_ErrorC... Compiling module work.TopParser_t_EngineStage_1_Extrac... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4_comp... Compiling module work.TopParser_t_RealParser_ipv4 Compiling module work.TopParser_t_RealParser_ipv6_comp... Compiling module work.TopParser_t_RealParser_ipv6_comp... Compiling module work.TopParser_t_RealParser_ipv6_comp... Compiling module work.TopParser_t_RealParser_ipv6_comp... Compiling module work.TopParser_t_RealParser_ipv6_comp... Compiling module work.TopParser_t_RealParser_ipv6_comp... Compiling module work.TopParser_t_RealParser_ipv6_comp... Compiling module work.TopParser_t_RealParser_ipv6_comp... Compiling module work.TopParser_t_RealParser_ipv6_comp... Compiling module work.TopParser_t_RealParser_ipv6_comp... Compiling module work.TopParser_t_RealParser_ipv6_comp... Compiling module work.TopParser_t_RealParser_ipv6_comp... Compiling module work.TopParser_t_RealParser_ipv6_comp... Compiling module work.TopParser_t_RealParser_ipv6 Compiling module work.TopParser_t_RealParser_arp_compu... Compiling module work.TopParser_t_RealParser_arp_compu... Compiling module work.TopParser_t_RealParser_arp_compu... Compiling module work.TopParser_t_RealParser_arp_compu... Compiling module work.TopParser_t_RealParser_arp_compu... Compiling module work.TopParser_t_RealParser_arp_compu... Compiling module work.TopParser_t_RealParser_arp_compu... Compiling module work.TopParser_t_RealParser_arp_compu... Compiling module work.TopParser_t_RealParser_arp_compu... Compiling module work.TopParser_t_RealParser_arp_compu... Compiling module work.TopParser_t_RealParser_arp_compu... Compiling module work.TopParser_t_RealParser_arp_compu... Compiling module work.TopParser_t_RealParser_arp_compu... Compiling module work.TopParser_t_RealParser_arp Compiling module work.TopParser_t_EngineStage_1_TupleF... Compiling module work.TopParser_t_EngineStage_1 Compiling module work.TopParser_t_EngineStage_2_ErrorC... Compiling module work.TopParser_t_EngineStage_2_Extrac... Compiling module work.TopParser_t_RealParser_icmp6_com... Compiling module work.TopParser_t_RealParser_icmp6_com... Compiling module work.TopParser_t_RealParser_icmp6_com... Compiling module work.TopParser_t_RealParser_icmp6_com... Compiling module work.TopParser_t_RealParser_icmp6_com... Compiling module work.TopParser_t_RealParser_icmp6_com... Compiling module work.TopParser_t_RealParser_icmp6_com... Compiling module work.TopParser_t_RealParser_icmp6 Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp_compu... Compiling module work.TopParser_t_RealParser_tcp Compiling module work.TopParser_t_RealParser_udp_compu... Compiling module work.TopParser_t_RealParser_udp_compu... Compiling module work.TopParser_t_RealParser_udp_compu... Compiling module work.TopParser_t_RealParser_udp_compu... Compiling module work.TopParser_t_RealParser_udp_compu... Compiling module work.TopParser_t_RealParser_udp_compu... Compiling module work.TopParser_t_RealParser_udp_compu... Compiling module work.TopParser_t_RealParser_udp_compu... Compiling module work.TopParser_t_RealParser_udp Compiling module work.TopParser_t_RealParser_icmp_comp... Compiling module work.TopParser_t_RealParser_icmp_comp... Compiling module work.TopParser_t_RealParser_icmp_comp... Compiling module work.TopParser_t_RealParser_icmp_comp... Compiling module work.TopParser_t_RealParser_icmp_comp... Compiling module work.TopParser_t_RealParser_icmp_comp... Compiling module work.TopParser_t_RealParser_icmp_comp... Compiling module work.TopParser_t_RealParser_icmp Compiling module work.TopParser_t_EngineStage_2_TupleF... Compiling module work.TopParser_t_EngineStage_2 Compiling module work.TopParser_t_EngineStage_3_ErrorC... Compiling module work.TopParser_t_EngineStage_3_Extrac... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_RealParser_icmp6_nei... Compiling module work.TopParser_t_EngineStage_3_TupleF... Compiling module work.TopParser_t_EngineStage_3 Compiling module work.TopParser_t_EngineStage_4_ErrorC... Compiling module work.TopParser_t_start_0_compute_p_et... Compiling module work.TopParser_t_start_0_compute_p_et... Compiling module work.TopParser_t_start_0_compute_p_et... Compiling module work.TopParser_t_start_0_compute_p_et... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_ip... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_tc... Compiling module work.TopParser_t_start_0_compute_p_ud... Compiling module work.TopParser_t_start_0_compute_p_ud... Compiling module work.TopParser_t_start_0_compute_p_ud... Compiling module work.TopParser_t_start_0_compute_p_ud... Compiling module work.TopParser_t_start_0_compute_p_ud... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_cp... Compiling module work.TopParser_t_start_0_compute_p_cp... Compiling module work.TopParser_t_start_0_compute_p_cp... Compiling module work.TopParser_t_start_0_compute_p_cp... Compiling module work.TopParser_t_start_0_compute_p_cp... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ic... Compiling module work.TopParser_t_start_0_compute_p_ar... Compiling module work.TopParser_t_start_0_compute_p_ar... Compiling module work.TopParser_t_start_0_compute_p_ar... Compiling module work.TopParser_t_start_0_compute_p_ar... Compiling module work.TopParser_t_start_0_compute_p_ar... Compiling module work.TopParser_t_start_0_compute_p_ar... Compiling module work.TopParser_t_start_0_compute_p_ar... Compiling module work.TopParser_t_start_0_compute_p_ar... Compiling module work.TopParser_t_start_0_compute_p_ar... Compiling module work.TopParser_t_start_0_compute_p_ar... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_user... Compiling module work.TopParser_t_start_0_compute_dige... Compiling module work.TopParser_t_start_0_compute_sume... Compiling module work.TopParser_t_start_0_compute_sume... Compiling module work.TopParser_t_start_0_compute_sume... Compiling module work.TopParser_t_start_0_compute_sume... Compiling module work.TopParser_t_start_0_compute_sume... Compiling module work.TopParser_t_start_0_compute_sume... Compiling module work.TopParser_t_start_0_compute_sume... Compiling module work.TopParser_t_start_0_compute_sume... Compiling module work.TopParser_t_start_0_compute_sume... Compiling module work.TopParser_t_start_0_compute_sume... Compiling module work.TopParser_t_start_0_compute_cont... Compiling module work.TopParser_t_start_0_compute_cont... Compiling module work.TopParser_t_start_0 Compiling module work.TopParser_t_EngineStage_4 Compiling module work.TopParser_t_EngineStage_5_ErrorC... Compiling module work.TopParser_t_accept_compute_contr... Compiling module work.TopParser_t_accept_compute_contr... Compiling module work.TopParser_t_accept Compiling module work.TopParser_t_EngineStage_5 Compiling module work.TopParser_t_Engine Compiling module work.TopParser_t Compiling module work.TopPipe_lvl_t_setup_compute_real... Compiling module work.TopPipe_lvl_t_setup_compute_cont... Compiling module work.TopPipe_lvl_t_setup_compute_cont... Compiling module work.TopPipe_lvl_t_setup Compiling module work.TopPipe_lvl_t_EngineStage_0 Compiling module work.TopPipe_lvl_t_Engine Compiling module work.TopPipe_lvl_t Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.xpm_memory_base(MEMORY_SIZE=864,... Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=86... Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.realmain_dummy_table_for_netpfga... Compiling module work.TopPipe_lvl_0_t_realmain_dummy_t... Compiling module work.TopPipe_lvl_0_t_realmain_dummy_t... Compiling module work.TopPipe_lvl_0_t_realmain_dummy_t... Compiling module work.TopPipe_lvl_0_t_EngineStage_0 Compiling module work.TopPipe_lvl_0_t_realmain_select_... Compiling module work.TopPipe_lvl_0_t_realmain_select_... Compiling module work.TopPipe_lvl_0_t_realmain_select_... Compiling module work.TopPipe_lvl_0_t_realmain_send_to... Compiling module work.TopPipe_lvl_0_t_realmain_send_to... Compiling module work.TopPipe_lvl_0_t_realmain_send_to... Compiling module work.TopPipe_lvl_0_t_EngineStage_1 Compiling module work.TopPipe_lvl_0_t_act_19_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_19_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_19_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_19_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_19_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_19_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_19_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_19_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_19_sec Compiling module work.TopPipe_lvl_0_t_EngineStage_2 Compiling module work.TopPipe_lvl_0_t_condition_sec_12... Compiling module work.TopPipe_lvl_0_t_condition_sec_12... Compiling module work.TopPipe_lvl_0_t_condition_sec_12 Compiling module work.TopPipe_lvl_0_t_EngineStage_3 Compiling module work.TopPipe_lvl_0_t_condition_sec_11... Compiling module work.TopPipe_lvl_0_t_condition_sec_11... Compiling module work.TopPipe_lvl_0_t_condition_sec_11 Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s... Compiling module work.TopPipe_lvl_0_t_EngineStage_4 Compiling module work.TopPipe_lvl_0_t_condition_sec_4_... Compiling module work.TopPipe_lvl_0_t_condition_sec_4_... Compiling module work.TopPipe_lvl_0_t_condition_sec_4 Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_nat46_s... Compiling module work.TopPipe_lvl_0_t_realmain_set_egr... Compiling module work.TopPipe_lvl_0_t_realmain_set_egr... Compiling module work.TopPipe_lvl_0_t_realmain_set_egr... Compiling module work.TopPipe_lvl_0_t_realmain_set_egr... Compiling module work.TopPipe_lvl_0_t_EngineStage_5 Compiling module work.TopPipe_lvl_0_t_condition_sec_10... Compiling module work.TopPipe_lvl_0_t_condition_sec_10... Compiling module work.TopPipe_lvl_0_t_condition_sec_10 Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_EngineStage_6 Compiling module work.TopPipe_lvl_0_t_act_0_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_0_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_0_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_0_sec Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_EngineStage_7 Compiling module work.TopPipe_lvl_0_t_act_10_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_10_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_10_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_10_sec Compiling module work.TopPipe_lvl_0_t_condition_sec_3_... Compiling module work.TopPipe_lvl_0_t_condition_sec_3_... Compiling module work.TopPipe_lvl_0_t_condition_sec_3 Compiling module work.TopPipe_lvl_0_t_EngineStage_8 Compiling module work.TopPipe_lvl_0_t_act_sec_compute_... Compiling module work.TopPipe_lvl_0_t_act_sec_compute_... Compiling module work.TopPipe_lvl_0_t_act_sec_compute_... Compiling module work.TopPipe_lvl_0_t_act_sec Compiling module work.TopPipe_lvl_0_t_condition_sec_9_... Compiling module work.TopPipe_lvl_0_t_condition_sec_9_... Compiling module work.TopPipe_lvl_0_t_condition_sec_9 Compiling module work.TopPipe_lvl_0_t_EngineStage_9 Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_2_sec Compiling module work.TopPipe_lvl_0_t_act_9_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_9_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_9_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_9_sec Compiling module work.TopPipe_lvl_0_t_EngineStage_10 Compiling module work.TopPipe_lvl_0_t_act_12_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_12_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_12_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_12_sec Compiling module work.TopPipe_lvl_0_t_condition_sec_2_... Compiling module work.TopPipe_lvl_0_t_condition_sec_2_... Compiling module work.TopPipe_lvl_0_t_condition_sec_2 Compiling module work.TopPipe_lvl_0_t_EngineStage_11 Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_1_sec Compiling module work.TopPipe_lvl_0_t_condition_sec_8_... Compiling module work.TopPipe_lvl_0_t_condition_sec_8_... Compiling module work.TopPipe_lvl_0_t_condition_sec_8 Compiling module work.TopPipe_lvl_0_t_EngineStage_12 Compiling module work.TopPipe_lvl_0_t_act_11_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_11_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_11_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_11_sec Compiling module work.TopPipe_lvl_0_t_act_3_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_3_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_3_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_3_sec Compiling module work.TopPipe_lvl_0_t_EngineStage_13 Compiling module work.TopPipe_lvl_0_t_act_13_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_13_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_13_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_13_sec Compiling module work.TopPipe_lvl_0_t_condition_sec_1_... Compiling module work.TopPipe_lvl_0_t_condition_sec_1_... Compiling module work.TopPipe_lvl_0_t_condition_sec_1 Compiling module work.TopPipe_lvl_0_t_EngineStage_14 Compiling module work.TopPipe_lvl_0_t_condition_sec_7_... Compiling module work.TopPipe_lvl_0_t_condition_sec_7_... Compiling module work.TopPipe_lvl_0_t_condition_sec_7 Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_EngineStage_15 Compiling module work.TopPipe_lvl_0_t_act_5_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_5_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_5_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_5_sec Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_realmain_delta_p... Compiling module work.TopPipe_lvl_0_t_EngineStage_16 Compiling module work.TopPipe_lvl_0_t_act_15_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_15_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_15_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_15_sec Compiling module work.TopPipe_lvl_0_t_condition_sec_0_... Compiling module work.TopPipe_lvl_0_t_condition_sec_0_... Compiling module work.TopPipe_lvl_0_t_condition_sec_0 Compiling module work.TopPipe_lvl_0_t_EngineStage_17 Compiling module work.TopPipe_lvl_0_t_act_4_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_4_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_4_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_4_sec Compiling module work.TopPipe_lvl_0_t_condition_sec_6_... Compiling module work.TopPipe_lvl_0_t_condition_sec_6_... Compiling module work.TopPipe_lvl_0_t_condition_sec_6 Compiling module work.TopPipe_lvl_0_t_EngineStage_18 Compiling module work.TopPipe_lvl_0_t_act_14_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_14_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_14_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_14_sec Compiling module work.TopPipe_lvl_0_t_act_7_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_7_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_7_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_7_sec Compiling module work.TopPipe_lvl_0_t_EngineStage_19 Compiling module work.TopPipe_lvl_0_t_act_17_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_17_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_17_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_17_sec Compiling module work.TopPipe_lvl_0_t_condition_sec_co... Compiling module work.TopPipe_lvl_0_t_condition_sec_co... Compiling module work.TopPipe_lvl_0_t_condition_sec Compiling module work.TopPipe_lvl_0_t_EngineStage_20 Compiling module work.TopPipe_lvl_0_t_act_6_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_6_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_6_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_6_sec Compiling module work.TopPipe_lvl_0_t_condition_sec_5_... Compiling module work.TopPipe_lvl_0_t_condition_sec_5_... Compiling module work.TopPipe_lvl_0_t_condition_sec_5 Compiling module work.TopPipe_lvl_0_t_EngineStage_21 Compiling module work.TopPipe_lvl_0_t_act_16_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_16_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_16_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_16_sec Compiling module work.TopPipe_lvl_0_t_act_8_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_8_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_8_sec_comput... Compiling module work.TopPipe_lvl_0_t_act_8_sec Compiling module work.TopPipe_lvl_0_t_EngineStage_22 Compiling module work.TopPipe_lvl_0_t_act_18_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_18_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_18_sec_compu... Compiling module work.TopPipe_lvl_0_t_act_18_sec Compiling module work.TopPipe_lvl_0_t_realmain_set_egr... Compiling module work.TopPipe_lvl_0_t_realmain_set_egr... Compiling module work.TopPipe_lvl_0_t_realmain_set_egr... Compiling module work.TopPipe_lvl_0_t_realmain_set_egr... Compiling module work.TopPipe_lvl_0_t_EngineStage_23 Compiling module work.TopPipe_lvl_0_t_realmain_set_egr... Compiling module work.TopPipe_lvl_0_t_realmain_set_egr... Compiling module work.TopPipe_lvl_0_t_realmain_set_egr... Compiling module work.TopPipe_lvl_0_t_realmain_set_egr... Compiling module work.TopPipe_lvl_0_t_EngineStage_24 Compiling module work.TopPipe_lvl_0_t_sink_compute_con... Compiling module work.TopPipe_lvl_0_t_sink_compute_con... Compiling module work.TopPipe_lvl_0_t_sink Compiling module work.TopPipe_lvl_0_t_EngineStage_25 Compiling module work.TopPipe_lvl_0_t_Engine Compiling module work.TopPipe_lvl_0_t Compiling module work.TopDeparser_t_EngineStage_0_Erro... Compiling module work.TopDeparser_t_extract_headers_se... Compiling module work.TopDeparser_t_extract_headers_se... Compiling module work.TopDeparser_t_extract_headers_se... Compiling module work.TopDeparser_t_extract_headers_se... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0_Edit... Compiling module work.TopDeparser_t_EngineStage_0 Compiling module work.TopDeparser_t_EngineStage_1_Erro... Compiling module work.TopDeparser_t_act_20_sec_compute... Compiling module work.TopDeparser_t_act_20_sec_compute... Compiling module work.TopDeparser_t_act_20_sec Compiling module work.TopDeparser_t_EngineStage_1 Compiling module work.TopDeparser_t_EngineStage_2_Erro... Compiling module work.TopDeparser_t_emit_10_compute_co... Compiling module work.TopDeparser_t_emit_10_compute__S... Compiling module work.TopDeparser_t_emit_10_compute__S... Compiling module work.TopDeparser_t_emit_10_compute__S... Compiling module work.TopDeparser_t_emit_10_compute_co... Compiling module work.TopDeparser_t_emit_10_compute_co... Compiling module work.TopDeparser_t_emit_10 Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2_Edit... Compiling module work.TopDeparser_t_EngineStage_2 Compiling module work.TopDeparser_t_EngineStage_3_Erro... Compiling module work.TopDeparser_t_emit_9_compute_con... Compiling module work.TopDeparser_t_emit_9_compute__ST... Compiling module work.TopDeparser_t_emit_9_compute__ST... Compiling module work.TopDeparser_t_emit_9_compute__ST... Compiling module work.TopDeparser_t_emit_9_compute__ST... Compiling module work.TopDeparser_t_emit_9_compute_con... Compiling module work.TopDeparser_t_emit_9_compute_con... Compiling module work.TopDeparser_t_emit_9 Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3_Edit... Compiling module work.TopDeparser_t_EngineStage_3 Compiling module work.TopDeparser_t_EngineStage_4_Erro... Compiling module work.TopDeparser_t_emit_8_compute_con... Compiling module work.TopDeparser_t_emit_8_compute__ST... Compiling module work.TopDeparser_t_emit_8_compute__ST... Compiling module work.TopDeparser_t_emit_8_compute__ST... Compiling module work.TopDeparser_t_emit_8_compute__ST... Compiling module work.TopDeparser_t_emit_8_compute__ST... Compiling module work.TopDeparser_t_emit_8_compute__ST... Compiling module work.TopDeparser_t_emit_8_compute__ST... Compiling module work.TopDeparser_t_emit_8_compute__ST... Compiling module work.TopDeparser_t_emit_8_compute__ST... Compiling module work.TopDeparser_t_emit_8_compute__ST... Compiling module work.TopDeparser_t_emit_8_compute__ST... Compiling module work.TopDeparser_t_emit_8_compute__ST... Compiling module work.TopDeparser_t_emit_8_compute__ST... Compiling module work.TopDeparser_t_emit_8_compute_con... Compiling module work.TopDeparser_t_emit_8_compute_con... Compiling module work.TopDeparser_t_emit_8 Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4_Edit... Compiling module work.TopDeparser_t_EngineStage_4 Compiling module work.TopDeparser_t_EngineStage_5_Erro... Compiling module work.TopDeparser_t_emit_7_compute_con... Compiling module work.TopDeparser_t_emit_7_compute__ST... Compiling module work.TopDeparser_t_emit_7_compute__ST... Compiling module work.TopDeparser_t_emit_7_compute__ST... Compiling module work.TopDeparser_t_emit_7_compute__ST... Compiling module work.TopDeparser_t_emit_7_compute__ST... Compiling module work.TopDeparser_t_emit_7_compute__ST... Compiling module work.TopDeparser_t_emit_7_compute__ST... Compiling module work.TopDeparser_t_emit_7_compute__ST... Compiling module work.TopDeparser_t_emit_7_compute_con... Compiling module work.TopDeparser_t_emit_7_compute_con... Compiling module work.TopDeparser_t_emit_7 Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5_Edit... Compiling module work.TopDeparser_t_EngineStage_5 Compiling module work.TopDeparser_t_EngineStage_6_Erro... Compiling module work.TopDeparser_t_emit_6_compute_con... Compiling module work.TopDeparser_t_emit_6_compute__ST... Compiling module work.TopDeparser_t_emit_6_compute__ST... Compiling module work.TopDeparser_t_emit_6_compute__ST... Compiling module work.TopDeparser_t_emit_6_compute__ST... Compiling module work.TopDeparser_t_emit_6_compute__ST... Compiling module work.TopDeparser_t_emit_6_compute__ST... Compiling module work.TopDeparser_t_emit_6_compute__ST... Compiling module work.TopDeparser_t_emit_6_compute__ST... Compiling module work.TopDeparser_t_emit_6_compute__ST... Compiling module work.TopDeparser_t_emit_6_compute_con... Compiling module work.TopDeparser_t_emit_6_compute_con... Compiling module work.TopDeparser_t_emit_6 Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6_Edit... Compiling module work.TopDeparser_t_EngineStage_6 Compiling module work.TopDeparser_t_EngineStage_7_Erro... Compiling module work.TopDeparser_t_emit_5_compute_con... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute__ST... Compiling module work.TopDeparser_t_emit_5_compute_con... Compiling module work.TopDeparser_t_emit_5_compute_con... Compiling module work.TopDeparser_t_emit_5 Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7_Edit... Compiling module work.TopDeparser_t_EngineStage_7 Compiling module work.TopDeparser_t_EngineStage_8_Erro... Compiling module work.TopDeparser_t_emit_4_compute_con... Compiling module work.TopDeparser_t_emit_4_compute__ST... Compiling module work.TopDeparser_t_emit_4_compute__ST... Compiling module work.TopDeparser_t_emit_4_compute__ST... Compiling module work.TopDeparser_t_emit_4_compute__ST... Compiling module work.TopDeparser_t_emit_4_compute_con... Compiling module work.TopDeparser_t_emit_4_compute_con... Compiling module work.TopDeparser_t_emit_4 Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8_Edit... Compiling module work.TopDeparser_t_EngineStage_8 Compiling module work.TopDeparser_t_EngineStage_9_Erro... Compiling module work.TopDeparser_t_emit_3_compute_con... Compiling module work.TopDeparser_t_emit_3_compute__ST... Compiling module work.TopDeparser_t_emit_3_compute__ST... Compiling module work.TopDeparser_t_emit_3_compute__ST... Compiling module work.TopDeparser_t_emit_3_compute_con... Compiling module work.TopDeparser_t_emit_3_compute_con... Compiling module work.TopDeparser_t_emit_3 Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9_Edit... Compiling module work.TopDeparser_t_EngineStage_9 Compiling module work.TopDeparser_t_EngineStage_10_Err... Compiling module work.TopDeparser_t_emit_2_compute_con... Compiling module work.TopDeparser_t_emit_2_compute__ST... Compiling module work.TopDeparser_t_emit_2_compute__ST... Compiling module work.TopDeparser_t_emit_2_compute__ST... Compiling module work.TopDeparser_t_emit_2_compute_con... Compiling module work.TopDeparser_t_emit_2_compute_con... Compiling module work.TopDeparser_t_emit_2 Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10_Edi... Compiling module work.TopDeparser_t_EngineStage_10 Compiling module work.TopDeparser_t_EngineStage_11_Err... Compiling module work.TopDeparser_t_emit_1_compute_con... Compiling module work.TopDeparser_t_emit_1_compute__ST... Compiling module work.TopDeparser_t_emit_1_compute__ST... Compiling module work.TopDeparser_t_emit_1_compute__ST... Compiling module work.TopDeparser_t_emit_1_compute__ST... Compiling module work.TopDeparser_t_emit_1_compute__ST... Compiling module work.TopDeparser_t_emit_1_compute_con... Compiling module work.TopDeparser_t_emit_1_compute_con... Compiling module work.TopDeparser_t_emit_1 Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11_Edi... Compiling module work.TopDeparser_t_EngineStage_11 Compiling module work.TopDeparser_t_EngineStage_12_Err... Compiling module work.TopDeparser_t_emit_0_compute_con... Compiling module work.TopDeparser_t_emit_0_compute__ST... Compiling module work.TopDeparser_t_emit_0_compute__ST... Compiling module work.TopDeparser_t_emit_0_compute__ST... Compiling module work.TopDeparser_t_emit_0_compute_con... Compiling module work.TopDeparser_t_emit_0_compute_con... Compiling module work.TopDeparser_t_emit_0 Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12_Edi... Compiling module work.TopDeparser_t_EngineStage_12 Compiling module work.TopDeparser_t_Engine Compiling module work.TopDeparser_t Compiling module work.xpm_cdc_sync_rst(DEST_SYNC_FF=2,... Compiling module work.xpm_fifo_rst(COMMON_CLOCK=0) Compiling module work.xpm_fifo_reg_bit Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9... Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8... Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT... Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=8) Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT... Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=9) Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.S_BRIDGER_for_realmain_dummy_tab... Compiling module work.S_PROTOCOL_ADAPTER_INGRESS Compiling module work.S_PROTOCOL_ADAPTER_EGRESS Compiling module work.xpm_fifo_rst_default Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1... Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9... Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_counter_updn(COUNTER_WIDTH=2... Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1... Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.S_SYNCER_for_TopParser Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1... Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.S_SYNCER_for_S_SYNCER_for_S_SYNC... Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1... Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8... Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7... Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT... Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=7) Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.S_SYNCER_for_S_SYNCER_for_TopDep... Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1... Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1... Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1... Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT... Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=10) Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.S_SYNCER_for_TopDeparser Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... Compiling module work.S_SYNCER_for__OUT_ Compiling module work.S_CONTROLLER_SimpleSumeSwitch Compiling module work.SimpleSumeSwitch Compiling module work.TB_System_Stim Compiling module work.Check Compiling module work.SimpleSumeSwitch_tb Compiling module work.glbl Built simulation snapshot work.SimpleSumeSwitch_tb#work.glbl ****** Webtalk v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-186] '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Mon Jul 29 16:30:53 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2018.2/doc/webtalk_introduction.html. INFO: [Common 17-206] Exiting Webtalk at Mon Jul 29 16:30:53 2019... + /opt/Xilinx/Vivado/2018.2/bin/xsim --runall SimpleSumeSwitch_tb#work.glbl ****** xsim v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsim_script.tcl # xsim {work.SimpleSumeSwitch_tb#work.glbl} -autoloadwcfg -runall Vivado Simulator 2018.2 Time resolution is 1 ps run -all Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_dummy_table_for_netpfga_0.realmain_dummy_table_for_netpfga_0_t_Wrap_inst.realmain_dummy_table_for_netpfga_0_t_IntTop_inst.realmain_dummy_table_for_netpfga_0_t_Lookup_inst.realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_792 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_dummy_table_for_netpfga_0.realmain_dummy_table_for_netpfga_0_t_Wrap_inst.realmain_dummy_table_for_netpfga_0_t_IntTop_inst.realmain_dummy_table_for_netpfga_0_t_Lookup_inst.realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_792 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_dummy_table_for_netpfga_0.realmain_dummy_table_for_netpfga_0_t_Wrap_inst.realmain_dummy_table_for_netpfga_0_t_IntTop_inst.realmain_dummy_table_for_netpfga_0_t_Lookup_inst.realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_792 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_dummy_table_for_netpfga_0.realmain_dummy_table_for_netpfga_0_t_Wrap_inst.realmain_dummy_table_for_netpfga_0_t_IntTop_inst.realmain_dummy_table_for_netpfga_0_t_Lookup_inst.realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_792 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_dummy_table_for_netpfga_0.realmain_dummy_table_for_netpfga_0_t_Wrap_inst.realmain_dummy_table_for_netpfga_0_t_IntTop_inst.realmain_dummy_table_for_netpfga_0_t_Lookup_inst.realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_792 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6553 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.du6df7ou4c9jzix9kt8y8sp35_875.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6646 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.rc2oqgemebaubffc_998.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/rc2oqgemebaubffc_998/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6676 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.s8zvr35avia82az9e4ga7z_2508.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6740 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.d4cl8nwtlfqqa3qq1emn6smhnhrj_2144.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6824 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.ow8vk1v7n14yey1jc5d040hf1440r1x_695.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6646 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.xtsdogepbxcg3t8fqtbed8as0e1l_2610.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xtsdogepbxcg3t8fqtbed8as0e1l_2610/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6676 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.emsxcy8c153tkouy17br04f_2299.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_7005 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v2x1yvitwpecodsxcz4bwdpizcg445_375.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_7089 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.owseb8koh0tm5b2cm23kfowmsv_348.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_7173 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.l7152fs74u8zwxog2cx_2460.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6740 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.lci0djz2hlarkew5g4z4wemft697fr_2582.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6824 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.xpemdowtjrj47j8atnb65h4v07_1130.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_7425 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.vxh8gue8epq6gxze_685.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6646 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.zmtz6gstdn71pkc38oscb260fx_746.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/zmtz6gstdn71pkc38oscb260fx_746/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6676 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.oggsepfdbfvc08g925kumcu8ai081hf_2487.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_7612 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.wdeecdhsjseok1s3v750r3jb_550.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_7173 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.h2gi6oqvy2ath2fk_362.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_7780 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.wneadextejr1frvvs0h8_344.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_7005 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.wip2u61mji55unuwjs6ipl7grolkp_1787.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6740 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.d7gumo82gk6md4n6jh72oukr_1045.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_7089 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.vbsfwqsy6fejb9tjlqq1_2668.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8116 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.y0o0b5b83atg8om0jqdqe2p3pwoxl_1489.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6824 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.v25jqojnept4a2izwn4c0gio6doe0h_1269.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_7425 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.ueoy8q1oq92abqdr6cavsnehcsseh_7.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8374 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.xt6i6t0dtbr9k9ux4848l_2541.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/xt6i6t0dtbr9k9ux4848l_2541/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8404 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.dkcs1lf2vu5dwmt01vw9eqs5xby_452.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8468 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.c1szjispkb2i6ti1o_2213.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8554 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.gp2sxhuvbjmdw26h21zj5zo4h94_979.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8638 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.osugxrkciuq7h54lwjvabg_1385.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8722 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.s01rsqufj7k6k4vnqmz3teozsv22_143.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8806 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8890 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.qyfmxlhxtgqyj78i3mu2sw5_2306.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_8973 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.ehndy8vbflb0gxuke3lnsjm_77.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/ehndy8vbflb0gxuke3lnsjm_77/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6676 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.a6l5ilsonpwsue0o_2404.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_7173 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.a1j85vyq4aadbgoq5b7orqtbwpa_1948.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6740 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv [SW] CAM_Init() - start [SW] CAM_Init() - done [SW] CAM_EnableDevice() - start SV_write_control()- start SV_write_control()- done SV_read_control()- start SV_read_control()- done SV_write_control()- start SV_write_control()- done [SW] CAM_EnableDevice() - done [2280754] INFO: finished packet stimulus file [4251632] ERROR: tuple mismatch for packet 1 expected < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 > actual < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000004010000 > $finish called at time : 4251632 ps : File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" Line 120 exit INFO: [Common 17-206] Exiting xsim at Mon Jul 29 16:31:07 2019... + grep ^expected /home/nico/master-thesis/netpfga/log/compile-2019-07-29-162950 + sed -e s/.*= + grep ^actual /home/nico/master-thesis/netpfga/log/compile-2019-07-29-162950 + sed -e s/.*= + date Mon Jul 29 16:31:07 CEST 2019 + cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4 + make config_writes /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata + date Mon Jul 29 16:31:07 CEST 2019 + cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4 + make uninstall_sdnet rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip + make install_sdnet rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip cp -r nf_sume_sdnet_ip /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/ mkdir /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/hdl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper/ cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/tcl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/Makefile /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ make -C /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip' rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip vivado -mode batch -source nf_sume_sdnet.tcl ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source nf_sume_sdnet.tcl # set design nf_sume_sdnet # set top nf_sume_sdnet # set device xc7vx690t-3-ffg1761 # set proj_dir ./ip_proj # set ip_version 1.00 # set lib_name NetFPGA # create_project -name ${design} -force -dir "./${proj_dir}" -part ${device} # set_property source_mgmt_mode All [current_project] # set_property top ${top} [current_fileset] # set_property ip_repo_paths $::env(SUME_FOLDER)/lib/hw/ [current_fileset] # update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'. WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'. # puts "nf_sume_sdnet" nf_sume_sdnet # read_verilog "./wrapper/sume_to_sdnet.v" # read_verilog "./wrapper/nf_sume_sdnet.v" # read_verilog "./wrapper/changeEndian.v" # add_files -scan_for_includes ./SimpleSumeSwitch/ # import_files -force INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1' # update_compile_order -fileset sources_1 update_compile_order: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1261.445 ; gain = 5.000 ; free physical = 8353 ; free virtual = 29124 # update_compile_order -fileset sim_1 update_compile_order: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1264.445 ; gain = 3.000 ; free physical = 8349 ; free virtual = 29120 # ipx::package_project WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/wrapper/changeEndian.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM_INST0.h'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/dpi.h'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM.h'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.h'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request.vp'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v'. INFO: [IP_Flow 19-5169] Module 'nf_sume_sdnet' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager. INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 'axis_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'S_AXI'. INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'S_AXI_ARESETN'. INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'axis_resetn'. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. ipx::package_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:18 . Memory (MB): peak = 1341.086 ; gain = 49.000 ; free physical = 8331 ; free virtual = 29102 # set_property name ${design} [ipx::current_core] # set_property library ${lib_name} [ipx::current_core] # set_property vendor_display_name {NetFPGA} [ipx::current_core] # set_property company_url {http://www.netfpga.org} [ipx::current_core] # set_property vendor {NetFPGA} [ipx::current_core] # set_property supported_families {{virtex7} {Production}} [ipx::current_core] # set_property taxonomy {{/NetFPGA/Generic}} [ipx::current_core] # set_property version ${ip_version} [ipx::current_core] # set_property display_name ${design} [ipx::current_core] # set_property description ${design} [ipx::current_core] # ipx::add_user_parameter {C_M_AXIS_DATA_WIDTH} [ipx::current_core] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property display_name {C_M_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value {256} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]] # ipx::add_user_parameter {C_S_AXIS_DATA_WIDTH} [ipx::current_core] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property display_name {C_S_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value {256} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]] # ipx::add_user_parameter {C_M_AXIS_TUSER_WIDTH} [ipx::current_core] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property display_name {C_M_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value {128} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]] # ipx::add_user_parameter {C_S_AXIS_TUSER_WIDTH} [ipx::current_core] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property display_name {C_S_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value {128} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]] # ipx::add_user_parameter {C_S_AXI_DATA_WIDTH} [ipx::current_core] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property display_name {C_S_AXI_DATA_WIDTH} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value {32} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_format {long} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]] # ipx::add_user_parameter {C_S_AXI_ADDR_WIDTH} [ipx::current_core] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property display_name {C_S_AXI_ADDR_WIDTH} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value {12} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_format {long} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]] # ipx::add_user_parameter {SDNET_ADDR_WIDTH} [ipx::current_core] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_resolve_type {user} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property display_name {SDNET_ADDR_WIDTH} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value {11} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]] WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead # set_property value_format {long} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]] # ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagesynthesis -of_objects [ipx::current_core]] # ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagebehavioralsimulation -of_objects [ipx::current_core]] # ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects [ipx::current_core]] # ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects [ipx::current_core]] # update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'. WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.) # ipx::infer_user_parameters [ipx::current_core] # ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nf_sume_sdnet_v1_0.tcl" does not have the current IP _v format. If the IP name or version was changed recently, recreate this file to update the file format. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. # ipx::save_core [ipx::current_core] # update_ip_catalog # close_project INFO: [Common 17-206] Exiting Vivado at Mon Jul 29 16:31:55 2019... make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip' + date Mon Jul 29 16:31:56 CEST 2019 + cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default + make rm -f config_writes.py* rm -f *.pyc cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py ./ + date Mon Jul 29 16:31:56 CEST 2019 + cd /home/nico/projects/P4-NetFPGA + ./tools/scripts/nf_test.py sim --major switch --minor default make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test' vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_defines.tcl ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_defines.tcl # set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 # set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF # set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 # set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 # set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF # set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 # set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 # set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF # set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 # set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 # set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF # set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 # set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 # set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF # set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 # set M00_BASEADDR 0x44000000 # set M00_HIGHADDR 0x44000FFF # set M00_SIZEADDR 0x1000 # set M01_BASEADDR 0x44010000 # set M01_HIGHADDR 0x44010FFF # set M01_SIZEADDR 0x1000 # set M02_BASEADDR 0x44020000 # set M02_HIGHADDR 0x44020FFF # set M02_SIZEADDR 0x1000 # set M03_BASEADDR 0x44030000 # set M03_HIGHADDR 0x44030FFF # set M03_SIZEADDR 0x1000 # set M04_BASEADDR 0x44040000 # set M04_HIGHADDR 0x44040FFF # set M04_SIZEADDR 0x1000 # set M05_BASEADDR 0x44050000 # set M05_HIGHADDR 0x44050FFF # set M05_SIZEADDR 0x1000 # set M06_BASEADDR 0x44060000 # set M06_HIGHADDR 0x44060FFF # set M06_SIZEADDR 0x1000 # set M07_BASEADDR 0x44070000 # set M07_HIGHADDR 0x44070FFF # set M07_SIZEADDR 0x1000 # set M08_BASEADDR 0x44080000 # set M08_HIGHADDR 0x44080FFF # set M08_SIZEADDR 0x1000 # set IDENTIFIER_BASEADDR $M00_BASEADDR # set IDENTIFIER_HIGHADDR $M00_HIGHADDR # set IDENTIFIER_SIZEADDR $M00_SIZEADDR # set INPUT_ARBITER_BASEADDR $M01_BASEADDR # set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR # set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR # set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR # set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR # set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR # set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR # set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR # set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR # set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR # set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR # set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR # set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR # set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR # set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR # set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR # set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR # set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR # set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR # set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR # set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR # set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR # set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR # set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR INFO: [Common 17-206] Exiting Vivado at Mon Jul 29 16:32:02 2019... vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/export_registers.tcl ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/export_registers.tcl # set DEF_LIST { # {MICROBLAZE_AXI_IIC 0 0 ""} \ # {MICROBLAZE_UARTLITE 0 0 ""} \ # {MICROBLAZE_DLMB_BRAM 0 0 ""} \ # {MICROBLAZE_ILMB_BRAM 0 0 ""} \ # {MICROBLAZE_AXI_INTC 0 0 ""} \ # {INPUT_ARBITER 0 1 input_arbiter_v1_0_0/data/input_arbiter_regs_defines.txt} \ # {OUTPUT_QUEUES 0 1 output_queues_v1_0_0/data/output_queues_regs_defines.txt} \ # {OUTPUT_PORT_LOOKUP 0 1 switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.txt} \ # {NF_10G_INTERFACE0 0 1 nf_10ge_interface_shared_v1_0_0/data/nf_10g_interface_shared_regs_defines.txt} \ # {NF_10G_INTERFACE1 1 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ # {NF_10G_INTERFACE2 2 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ # {NF_10G_INTERFACE3 3 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ # {NF_RIFFA_DMA 0 1 nf_riffa_dma_v1_0_0/data/nf_riffa_dma_regs_defines.txt} \ # # # } # set target_path $::env(NF_DESIGN_DIR)/sw/embedded/src/ # set target_file $target_path/sume_register_defines.h # proc write_header { target_file } { # # # creat a blank header file # # do a fresh rewrite in case the file already exits # file delete -force $target_file # open $target_file "w" # set h_file [open $target_file "w"] # # # puts $h_file "//-" # puts $h_file "// Copyright (c) 2015 University of Cambridge" # puts $h_file "// All rights reserved." # puts $h_file "//" # puts $h_file "// This software was developed by Stanford University and the University of Cambridge Computer Laboratory " # puts $h_file "// under National Science Foundation under Grant No. CNS-0855268," # puts $h_file "// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and" # puts $h_file "// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 (\"MRC2\"), " # puts $h_file "// as part of the DARPA MRC research programme." # puts $h_file "//" # puts $h_file "// @NETFPGA_LICENSE_HEADER_START@" # puts $h_file "//" # puts $h_file "// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor" # puts $h_file "// license agreements. See the NOTICE file distributed with this work for" # puts $h_file "// additional information regarding copyright ownership. NetFPGA licenses this" # puts $h_file "// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the" # puts $h_file "// \"License\"); you may not use this file except in compliance with the" # puts $h_file "// License. You may obtain a copy of the License at:" # puts $h_file "//" # puts $h_file "// http://www.netfpga-cic.org" # puts $h_file "//" # puts $h_file "// Unless required by applicable law or agreed to in writing, Work distributed" # puts $h_file "// under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR" # puts $h_file "// CONDITIONS OF ANY KIND, either express or implied. See the License for the" # puts $h_file "// specific language governing permissions and limitations under the License." # puts $h_file "//" # puts $h_file "// @NETFPGA_LICENSE_HEADER_END@" # puts $h_file "/////////////////////////////////////////////////////////////////////////////////" # puts $h_file "// This is an automatically generated header definitions file" # puts $h_file "/////////////////////////////////////////////////////////////////////////////////" # puts $h_file "" # # close $h_file # # }; # proc write_core {target_file prefix id has_registers lib_name} { # # # set h_file [open $target_file "a"] # # #First, read the memory map information from the reference_project defines file # source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl # set public_repo_dir $::env(SUME_FOLDER)/lib/hw/ # # # set baseaddr [set $prefix\_BASEADDR] # set highaddr [set $prefix\_HIGHADDR] # set sizeaddr [set $prefix\_SIZEADDR] # # puts $h_file "//######################################################" # puts $h_file "//# Definitions for $prefix" # puts $h_file "//######################################################" # # puts $h_file "#define SUME_$prefix\_BASEADDR $baseaddr" # puts $h_file "#define SUME_$prefix\_HIGHADDR $highaddr" # puts $h_file "#define SUME_$prefix\_SIZEADDR $sizeaddr" # puts $h_file "" # # #Second, read the registers information from the library defines file # if $has_registers { # set lib_path "$public_repo_dir/std/cores/$lib_name" # set regs_h_define_file $lib_path # set regs_h_define_file_read [open $regs_h_define_file r] # set regs_h_define_file_data [read $regs_h_define_file_read] # close $regs_h_define_file_read # set regs_h_define_file_data_line [split $regs_h_define_file_data "\n"] # # foreach read_line $regs_h_define_file_data_line { # if {[regexp "#define" $read_line]} { # puts $h_file "#define SUME_[lindex $read_line 2]\_$id\_[lindex $read_line 3]\_[lindex $read_line 4] [lindex $read_line 5]" # } # } # } # puts $h_file "" # close $h_file # }; # write_header $target_file # foreach lib_item $DEF_LIST { # write_core $target_file [lindex $lib_item 0] [lindex $lib_item 1] [lindex $lib_item 2] [lindex $lib_item 3] # } ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR INFO: [Common 17-206] Exiting Vivado at Mon Jul 29 16:32:09 2019... cd ../sw/embedded/src && cp /home/nico/projects/P4-NetFPGA/tools/scripts/xparam2regdefines.py . && python xparam2regdefines.py cd ../sw/embedded/src && rm -f xparam2regdefines.py && mv reg_defines.h ../ cd ../sw/embedded && cp /home/nico/projects/P4-NetFPGA/tools/scripts/python_parser.py . && python python_parser.py cd ../sw/embedded && rm -f python_parser.py && mv reg_defines.py ../../test/reg_defines_simple_sume_switch.py make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test' make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test' rm -rf proj_* vivado*.* *.*~ .Xil* /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/ rm -rf *[0-9]_{stim,expected,log}.axi rm -f *.axi rm -f portconfig.sim rm -f seed rm -f *.log rm -f ../test/Makefile rm -rf ../test/*.log rm -rf ../test/*.axi rm -rf ../test/seed rm -rf ../test/*.sim rm -rf ../test/proj_* rm -rf ../test/ip_repo rm -f ../test/vivado*.* rm -f ../test/*_*_*/reg_defines_simple_sume_switch.py rm -f ../test/*_*_*/reg_defines_simple_sume_switch.pyc rm -f ../hw/create_ip/id_rom16x32.coe cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh echo 16028002 >> rom_data.txt echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt grep: ../../../RELEASE_NOTES: No such file or directory echo 00000204 >> rom_data.txt echo 0000FFFF >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py 16 mv -f id_rom16x32.coe ../hw/create_ip/ mv -f rom_data.txt ../hw/create_ip/ cp -f /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_defines_simple_sume_switch.py /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/reg_defines_simple_sume_switch.py vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl -tclargs sim_switch_default ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl # set design $::env(NF_PROJECT_NAME) # set top top_sim # set sim_top top_tb # set device xc7vx690t-3-ffg1761 # set proj_dir ./project # set public_repo_dir $::env(SUME_FOLDER)/lib/hw/ # set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/ # set repo_dir ./ip_repo # set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc # set project_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_general.xdc # set nf_10g_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_10g.xdc # set test_name [lindex $argv 0] # source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR # create_project -name ${design} -force -dir "$::env(NF_DESIGN_DIR)/hw/${proj_dir}" -part ${device} # set_property source_mgmt_mode DisplayOnly [current_project] # set_property top ${top} [current_fileset] # puts "Creating User Datapath reference project" Creating User Datapath reference project # create_fileset -constrset -quiet constraints # file copy ${public_repo_dir}/ ${repo_dir} # set_property ip_repo_paths ${repo_dir} [current_fileset] # add_files -fileset constraints -norecurse ${bit_settings} # add_files -fileset constraints -norecurse ${project_constraints} # add_files -fileset constraints -norecurse ${nf_10g_constraints} # set_property is_enabled true [get_files ${project_constraints}] # set_property is_enabled true [get_files ${bit_settings}] # set_property is_enabled true [get_files ${project_constraints}] # update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/ip_repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'. # create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip # set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci] # reset_target all [get_ips nf_sume_sdnet_ip] # generate_target all [get_ips nf_sume_sdnet_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_sume_sdnet_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_sume_sdnet_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_sume_sdnet_ip'... # create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip # set_property -dict [list CONFIG.C_BASEADDR $INPUT_ARBITER_BASEADDR] [get_ips input_arbiter_ip] # set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci] # reset_target all [get_ips input_arbiter_ip] # generate_target all [get_ips input_arbiter_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'input_arbiter_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'input_arbiter_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'input_arbiter_ip'... # create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip # set_property -dict [list CONFIG.C_BASEADDR $OUTPUT_QUEUES_BASEADDR] [get_ips sss_output_queues_ip] # set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci] # reset_target all [get_ips sss_output_queues_ip] # generate_target all [get_ips sss_output_queues_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'sss_output_queues_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'sss_output_queues_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'sss_output_queues_ip'... # create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip INFO: [Device 21-403] Loading part xc7vx690tffg1761-3 create_ip: Time (s): cpu = 00:00:23 ; elapsed = 00:01:00 . Memory (MB): peak = 1696.844 ; gain = 390.395 ; free physical = 8951 ; free virtual = 28789 # set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {1024} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip] # set_property generate_synth_checkpoint false [get_files identifier_ip.xci] # reset_target all [get_ips identifier_ip] # generate_target all [get_ips identifier_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'identifier_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'identifier_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'identifier_ip'... INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'identifier_ip'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'identifier_ip'... # create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip # set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip] WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '5.000' to '5.0' has been ignored for IP 'clk_wiz_ip' # set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci] # reset_target all [get_ips clk_wiz_ip] # generate_target all [get_ips clk_wiz_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz_ip'... INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz_ip'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz_ip'... # create_ip -name barrier -vendor NetFPGA -library NetFPGA -module_name barrier_ip # reset_target all [get_ips barrier_ip] # generate_target all [get_ips barrier_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'barrier_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'barrier_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'barrier_ip'... # create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip0 # set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_0_log.axi] [get_ips axis_sim_record_ip0] # reset_target all [get_ips axis_sim_record_ip0] # generate_target all [get_ips axis_sim_record_ip0] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip0'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip0'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip0'... # create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip1 # set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_1_log.axi] [get_ips axis_sim_record_ip1] # reset_target all [get_ips axis_sim_record_ip1] # generate_target all [get_ips axis_sim_record_ip1] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip1'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip1'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip1'... # create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip2 # set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_2_log.axi] [get_ips axis_sim_record_ip2] # reset_target all [get_ips axis_sim_record_ip2] # generate_target all [get_ips axis_sim_record_ip2] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip2'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip2'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip2'... # create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip3 # set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_3_log.axi] [get_ips axis_sim_record_ip3] # reset_target all [get_ips axis_sim_record_ip3] # generate_target all [get_ips axis_sim_record_ip3] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip3'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip3'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip3'... # create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip4 # set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/dma_0_log.axi] [get_ips axis_sim_record_ip4] # reset_target all [get_ips axis_sim_record_ip4] # generate_target all [get_ips axis_sim_record_ip4] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip4'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip4'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip4'... # create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip0 # set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_0_stim.axi] [get_ips axis_sim_stim_ip0] # generate_target all [get_ips axis_sim_stim_ip0] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip0'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip0'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip0'... # create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip1 # set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_1_stim.axi] [get_ips axis_sim_stim_ip1] # generate_target all [get_ips axis_sim_stim_ip1] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip1'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip1'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip1'... # create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip2 # set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_2_stim.axi] [get_ips axis_sim_stim_ip2] # generate_target all [get_ips axis_sim_stim_ip2] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip2'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip2'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip2'... # create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip3 # set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_3_stim.axi] [get_ips axis_sim_stim_ip3] # generate_target all [get_ips axis_sim_stim_ip3] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip3'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip3'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip3'... # create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip4 # set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/dma_0_stim.axi] [get_ips axis_sim_stim_ip4] # generate_target all [get_ips axis_sim_stim_ip4] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip4'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip4'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip4'... # create_ip -name axi_sim_transactor -vendor NetFPGA -library NetFPGA -module_name axi_sim_transactor_ip # set_property -dict [list CONFIG.STIM_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.axi CONFIG.EXPECT_FILE $::env(NF_DESIGN_DIR)/test/reg_expect.axi CONFIG.LOG_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.log] [get_ips axi_sim_transactor_ip] # reset_target all [get_ips axi_sim_transactor_ip] # generate_target all [get_ips axi_sim_transactor_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_sim_transactor_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_sim_transactor_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_sim_transactor_ip'... # update_ip_catalog # source $::env(NF_DESIGN_DIR)/hw/tcl/control_sub_sim.tcl ## set scripts_vivado_version 2018.2 ## set current_vivado_version [version -short] ## if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { ## puts "" ## puts "ERROR: This script was created for Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script." ## ## return 1 ## } ## set design_name control_sub ## if { [get_projects -quiet] eq "" } { ## puts "ERROR: Please open or create a project!" ## return 1 ## } ## set errMsg "" ## set nRet 0 ## set cur_design [current_bd_design -quiet] ## set list_cells [get_bd_cells -quiet] ## if { ${design_name} eq "" } { ## # USE CASES: ## # 1) Design_name not set ## ## set errMsg "ERROR: Please set the variable to a non-empty value." ## set nRet 1 ## ## } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { ## # USE CASES: ## # 2): Current design opened AND is empty AND names same. ## # 3): Current design opened AND is empty AND names diff; design_name NOT in project. ## # 4): Current design opened AND is empty AND names diff; design_name exists in project. ## ## if { $cur_design ne $design_name } { ## puts "INFO: Changing value of from <$design_name> to <$cur_design> since current design is empty." ## set design_name [get_property NAME $cur_design] ## } ## puts "INFO: Constructing design in IPI design <$cur_design>..." ## ## } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { ## # USE CASES: ## # 5) Current design opened AND has components AND same names. ## ## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." ## set nRet 1 ## } elseif { [get_files -quiet ${design_name}.bd] ne "" } { ## # USE CASES: ## # 6) Current opened design, has components, but diff names, design_name exists in project. ## # 7) No opened design, design_name exists in project. ## ## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." ## set nRet 2 ## ## } else { ## # USE CASES: ## # 8) No opened design, design_name not in project. ## # 9) Current opened design, has components, but diff names, design_name not in project. ## ## puts "INFO: Currently there is no design <$design_name> in project, so creating one..." ## ## create_bd_design $design_name ## ## puts "INFO: Making design <$design_name> as current_bd_design." ## current_bd_design $design_name ## ## } INFO: Currently there is no design in project, so creating one... Wrote : INFO: Making design as current_bd_design. ## puts "INFO: Currently the variable is equal to \"$design_name\"." INFO: Currently the variable is equal to "control_sub". ## if { $nRet != 0 } { ## puts $errMsg ## return $nRet ## } ## proc create_root_design { parentCell } { ## ## if { $parentCell eq "" } { ## set parentCell [get_bd_cells /] ## } ## ## # Get object for parentCell ## set parentObj [get_bd_cells $parentCell] ## if { $parentObj == "" } { ## puts "ERROR: Unable to find parent cell <$parentCell>!" ## return ## } ## ## # Make sure parentObj is hier blk ## set parentType [get_property TYPE $parentObj] ## if { $parentType ne "hier" } { ## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." ## return ## } ## ## # Save current instance; Restore later ## set oldCurInst [current_bd_instance .] ## ## # Set parent object as current ## current_bd_instance $parentObj ## ## ## # Create interface ports ## set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M00_AXI ## set M01_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M01_AXI ## set M02_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M02_AXI ## set M03_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M03_AXI ## set M04_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M04_AXI ## set M05_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M05_AXI ## set M06_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M06_AXI ## set M07_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M07_AXI ## set S00_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.ARUSER_WIDTH {0} CONFIG.AWUSER_WIDTH {0} CONFIG.BUSER_WIDTH {0} CONFIG.CLK_DOMAIN {} CONFIG.DATA_WIDTH {32} CONFIG.FREQ_HZ {100000000} CONFIG.ID_WIDTH {0} CONFIG.MAX_BURST_LENGTH {256} CONFIG.NUM_READ_OUTSTANDING {2} CONFIG.NUM_WRITE_OUTSTANDING {2} CONFIG.PHASE {0.000} CONFIG.PROTOCOL {AXI4} CONFIG.READ_WRITE_MODE {READ_WRITE} CONFIG.RUSER_WIDTH {0} CONFIG.SUPPORTS_NARROW_BURST {1} CONFIG.WUSER_WIDTH {0} ] $S00_AXI ## ## # Create ports ## set axi_lite_aclk [ create_bd_port -dir I -type clk axi_lite_aclk ] ## set axi_lite_areset [ create_bd_port -dir I -type rst axi_lite_areset ] ## set core_clk [ create_bd_port -dir I -type clk core_clk ] ## set_property -dict [ list CONFIG.FREQ_HZ {200000000} ] $core_clk ## set core_resetn [ create_bd_port -dir I -type rst core_resetn ] ## ## ## ## ## # Create instance: axi_interconnect_0, and set properties ## set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] ## set_property -dict [ list CONFIG.NUM_MI {8} CONFIG.TRANSLATION_MODE {0} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M00_HAS_REGSLICE {3} CONFIG.M00_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M01_HAS_REGSLICE {3} CONFIG.M01_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M02_HAS_REGSLICE {3} CONFIG.M02_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M03_HAS_REGSLICE {3} CONFIG.M03_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M04_HAS_REGSLICE {3} CONFIG.M04_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M05_HAS_REGSLICE {3} CONFIG.M05_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M06_HAS_REGSLICE {3} CONFIG.M06_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M07_HAS_REGSLICE {3} CONFIG.M07_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.S00_HAS_REGSLICE {3} CONFIG.S00_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## ## ## # Add AXI clock converter ## create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ## connect_bd_intf_net [get_bd_intf_ports S00_AXI] [get_bd_intf_pins axi_clock_converter_0/S_AXI] ## connect_bd_intf_net [get_bd_intf_pins axi_clock_converter_0/M_AXI] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S00_AXI] ## ## # Create interface connections ## connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports M01_AXI] [get_bd_intf_pins axi_interconnect_0/M01_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports M02_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports M03_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports M04_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_ports M05_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_ports M06_AXI] [get_bd_intf_pins axi_interconnect_0/M06_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_ports M07_AXI] [get_bd_intf_pins axi_interconnect_0/M07_AXI] ## ## # Create port connections ## connect_bd_net -net axi_lite_aclk_1 [get_bd_ports axi_lite_aclk] [get_bd_pins axi_clock_converter_0/s_axi_aclk] ## connect_bd_net -net core_clk_1 [get_bd_ports core_clk] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] ## connect_bd_net -net axi_lite_areset_1 [get_bd_ports axi_lite_areset] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] ## connect_bd_net -net core_resetn_1 [get_bd_ports core_resetn] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] ## ## # Create address segments ## source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl ## assign_bd_address [get_bd_addr_segs {M00_AXI/Reg }] ## set_property offset $M00_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}] ## set_property range $M00_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}] ## ## assign_bd_address [get_bd_addr_segs {M01_AXI/Reg }] ## set_property offset $M01_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}] ## set_property range $M01_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}] ## ## ## assign_bd_address [get_bd_addr_segs {M02_AXI/Reg }] ## set_property offset $M02_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}] ## set_property range $M02_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}] ## ## assign_bd_address [get_bd_addr_segs {M03_AXI/Reg }] ## set_property offset $M03_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}] ## set_property range $M03_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}] ## ## ## # Restore current instance ## current_bd_instance $oldCurInst ## ## save_bd_design ## } ## create_root_design "" CRITICAL WARNING: [BD 41-737] Cannot set the parameter TRANSLATION_MODE on /axi_interconnect_0. It is read-only. ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR is being mapped into at <0x44A00000 [ 64K ]> is being mapped into at <0x44A00000 [ 64K ]> is being mapped into at <0x44A00000 [ 64K ]> is being mapped into at <0x44A00000 [ 64K ]> Wrote : # read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/axi_clocking.v" # read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/nf_datapath.v" # read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_sim.v" # read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_tb.v" # update_compile_order -fileset sources_1 # update_compile_order -fileset sim_1 # set_property top ${sim_top} [get_filesets sim_1] # set_property include_dirs ${proj_dir} [get_filesets sim_1] # set_property simulator_language Mixed [current_project] # set_property verilog_define { {SIMULATION=1} } [get_filesets sim_1] # set_property -name xsim.more_options -value {-testplusarg TESTNAME=basic_test} -objects [get_filesets sim_1] # set_property runtime {} [get_filesets sim_1] # set_property target_simulator xsim [current_project] # set_property compxlib.xsim_compiled_library_dir {} [current_project] # set_property top_lib xil_defaultlib [get_filesets sim_1] # update_compile_order -fileset sim_1 update_compile_order: Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 2035.992 ; gain = 8.004 ; free physical = 8802 ; free virtual = 28676 loading libsume.. Traceback (most recent call last): File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py", line 42, in import config_writes File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py", line 7 ^ IndentationError: expected an indented block while executing "exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py" invoked from within "set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]" (file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 177) INFO: [Common 17-206] Exiting Vivado at Mon Jul 29 16:33:45 2019... Makefile:120: recipe for target 'sim' failed make: *** [sim] Error 1 make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test' cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_stim.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_expected.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_stim.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_expected.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_stim.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_expected.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_stim.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_expected.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_expected.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.log': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_expect.axi': No such file or directory cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.axi': No such file or directory NetFPGA environment: Root dir: /home/nico/projects/P4-NetFPGA Project name: simple_sume_switch Project dir: /tmp/nico/test/simple_sume_switch Work dir: /tmp/nico 512 === Work directory is /tmp/nico/test/simple_sume_switch === Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default === Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim'] + date Mon Jul 29 16:33:46 CEST 2019 + [ = no ] + cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch + make make -C hw distclean make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw' rm -rf proj_* vivado*.* *.*~ .Xil* /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/ rm -rf *[0-9]_{stim,expected,log}.axi rm -f *.axi rm -f portconfig.sim rm -f seed rm -f *.log rm -f ../test/Makefile rm -rf ../test/*.log rm -rf ../test/*.axi rm -rf ../test/seed rm -rf ../test/*.sim rm -rf ../test/proj_* rm -rf ../test/ip_repo rm -f ../test/vivado*.* rm -f ../test/*_*_*/reg_defines_simple_sume_switch.py rm -f ../test/*_*_*/reg_defines_simple_sume_switch.pyc rm -rfv project;\ rm -rfv ../sw/embedded/project;\ rm -rfv vivado*;\ rm -rfv *.log;\ rm -rfv .Xil;\ rm -rfv ..rej;\ rm -rfv .srcs;\ rm -rfv webtalk*;\ rm -rfv *.*~;\ rm -rfv ip_repo;\ rm -rfv ip_proj;\ rm -rfv std;\ make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw' make -C sw/embedded/ distclean make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded' rm -rf `find . -name "SDK_Workspace"` rm -rf `find . -name "*.log"` rm -rf `find . -name "*.jou"` make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded' rm -rfv vivado*;\ make -C hw project make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw' rm -f ../hw/create_ip/id_rom16x32.coe cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh echo 16028002 >> rom_data.txt echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt grep: ../../../RELEASE_NOTES: No such file or directory echo 00000204 >> rom_data.txt echo 0000FFFF >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py 16 mv -f id_rom16x32.coe ../hw/create_ip/ mv -f rom_data.txt ../hw/create_ip/ echo "Create reference project under folder /project";\ if test -d project/; then\ echo "Project already exists"; \ else \ vivado -mode batch -source tcl/simple_sume_switch.tcl;\ if [ -f patch/simple_sume_switch.patch ]; then\ patch -p1 < patch/simple_sume_switch.patch;\ fi;\ fi;\ Create reference project under folder /project ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source tcl/simple_sume_switch.tcl # set design $::env(NF_PROJECT_NAME) # set top top # set device xc7vx690t-3-ffg1761 # set proj_dir ./project # set public_repo_dir $::env(SUME_FOLDER)/lib/hw/ # set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/ # set repo_dir ./ip_repo # set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc # set project_constraints ./constraints/nf_sume_general.xdc # set nf_10g_constraints ./constraints/nf_sume_10g.xdc # source ./tcl/$::env(NF_PROJECT_NAME)_defines.tcl ## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ## set M00_BASEADDR 0x44000000 ## set M00_HIGHADDR 0x44000FFF ## set M00_SIZEADDR 0x1000 ## set M01_BASEADDR 0x44010000 ## set M01_HIGHADDR 0x44010FFF ## set M01_SIZEADDR 0x1000 ## set M02_BASEADDR 0x44020000 ## set M02_HIGHADDR 0x44020FFF ## set M02_SIZEADDR 0x1000 ## set M03_BASEADDR 0x44030000 ## set M03_HIGHADDR 0x44030FFF ## set M03_SIZEADDR 0x1000 ## set M04_BASEADDR 0x44040000 ## set M04_HIGHADDR 0x44040FFF ## set M04_SIZEADDR 0x1000 ## set M05_BASEADDR 0x44050000 ## set M05_HIGHADDR 0x44050FFF ## set M05_SIZEADDR 0x1000 ## set M06_BASEADDR 0x44060000 ## set M06_HIGHADDR 0x44060FFF ## set M06_SIZEADDR 0x1000 ## set M07_BASEADDR 0x44070000 ## set M07_HIGHADDR 0x44070FFF ## set M07_SIZEADDR 0x1000 ## set M08_BASEADDR 0x44080000 ## set M08_HIGHADDR 0x44080FFF ## set M08_SIZEADDR 0x1000 ## set IDENTIFIER_BASEADDR $M00_BASEADDR ## set IDENTIFIER_HIGHADDR $M00_HIGHADDR ## set IDENTIFIER_SIZEADDR $M00_SIZEADDR ## set INPUT_ARBITER_BASEADDR $M01_BASEADDR ## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR # source ./tcl/export_registers.tcl ## set DEF_LIST { ## {MICROBLAZE_AXI_IIC 0 0 ""} \ ## {MICROBLAZE_UARTLITE 0 0 ""} \ ## {MICROBLAZE_DLMB_BRAM 0 0 ""} \ ## {MICROBLAZE_ILMB_BRAM 0 0 ""} \ ## {MICROBLAZE_AXI_INTC 0 0 ""} \ ## {INPUT_ARBITER 0 1 input_arbiter_v1_0_0/data/input_arbiter_regs_defines.txt} \ ## {OUTPUT_QUEUES 0 1 output_queues_v1_0_0/data/output_queues_regs_defines.txt} \ ## {OUTPUT_PORT_LOOKUP 0 1 switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.txt} \ ## {NF_10G_INTERFACE0 0 1 nf_10ge_interface_shared_v1_0_0/data/nf_10g_interface_shared_regs_defines.txt} \ ## {NF_10G_INTERFACE1 1 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ ## {NF_10G_INTERFACE2 2 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ ## {NF_10G_INTERFACE3 3 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ ## {NF_RIFFA_DMA 0 1 nf_riffa_dma_v1_0_0/data/nf_riffa_dma_regs_defines.txt} \ ## ## ## } ## set target_path $::env(NF_DESIGN_DIR)/sw/embedded/src/ ## set target_file $target_path/sume_register_defines.h ## proc write_header { target_file } { ## ## # creat a blank header file ## # do a fresh rewrite in case the file already exits ## file delete -force $target_file ## open $target_file "w" ## set h_file [open $target_file "w"] ## ## ## puts $h_file "//-" ## puts $h_file "// Copyright (c) 2015 University of Cambridge" ## puts $h_file "// All rights reserved." ## puts $h_file "//" ## puts $h_file "// This software was developed by Stanford University and the University of Cambridge Computer Laboratory " ## puts $h_file "// under National Science Foundation under Grant No. CNS-0855268," ## puts $h_file "// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and" ## puts $h_file "// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 (\"MRC2\"), " ## puts $h_file "// as part of the DARPA MRC research programme." ## puts $h_file "//" ## puts $h_file "// @NETFPGA_LICENSE_HEADER_START@" ## puts $h_file "//" ## puts $h_file "// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor" ## puts $h_file "// license agreements. See the NOTICE file distributed with this work for" ## puts $h_file "// additional information regarding copyright ownership. NetFPGA licenses this" ## puts $h_file "// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the" ## puts $h_file "// \"License\"); you may not use this file except in compliance with the" ## puts $h_file "// License. You may obtain a copy of the License at:" ## puts $h_file "//" ## puts $h_file "// http://www.netfpga-cic.org" ## puts $h_file "//" ## puts $h_file "// Unless required by applicable law or agreed to in writing, Work distributed" ## puts $h_file "// under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR" ## puts $h_file "// CONDITIONS OF ANY KIND, either express or implied. See the License for the" ## puts $h_file "// specific language governing permissions and limitations under the License." ## puts $h_file "//" ## puts $h_file "// @NETFPGA_LICENSE_HEADER_END@" ## puts $h_file "/////////////////////////////////////////////////////////////////////////////////" ## puts $h_file "// This is an automatically generated header definitions file" ## puts $h_file "/////////////////////////////////////////////////////////////////////////////////" ## puts $h_file "" ## ## close $h_file ## ## }; ## proc write_core {target_file prefix id has_registers lib_name} { ## ## ## set h_file [open $target_file "a"] ## ## #First, read the memory map information from the reference_project defines file ## source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl ## set public_repo_dir $::env(SUME_FOLDER)/lib/hw/ ## ## ## set baseaddr [set $prefix\_BASEADDR] ## set highaddr [set $prefix\_HIGHADDR] ## set sizeaddr [set $prefix\_SIZEADDR] ## ## puts $h_file "//######################################################" ## puts $h_file "//# Definitions for $prefix" ## puts $h_file "//######################################################" ## ## puts $h_file "#define SUME_$prefix\_BASEADDR $baseaddr" ## puts $h_file "#define SUME_$prefix\_HIGHADDR $highaddr" ## puts $h_file "#define SUME_$prefix\_SIZEADDR $sizeaddr" ## puts $h_file "" ## ## #Second, read the registers information from the library defines file ## if $has_registers { ## set lib_path "$public_repo_dir/std/cores/$lib_name" ## set regs_h_define_file $lib_path ## set regs_h_define_file_read [open $regs_h_define_file r] ## set regs_h_define_file_data [read $regs_h_define_file_read] ## close $regs_h_define_file_read ## set regs_h_define_file_data_line [split $regs_h_define_file_data "\n"] ## ## foreach read_line $regs_h_define_file_data_line { ## if {[regexp "#define" $read_line]} { ## puts $h_file "#define SUME_[lindex $read_line 2]\_$id\_[lindex $read_line 3]\_[lindex $read_line 4] [lindex $read_line 5]" ## } ## } ## } ## puts $h_file "" ## close $h_file ## }; ## write_header $target_file ## foreach lib_item $DEF_LIST { ## write_core $target_file [lindex $lib_item 0] [lindex $lib_item 1] [lindex $lib_item 2] [lindex $lib_item 3] ## } ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR # create_project -name ${design} -force -dir "./${proj_dir}" -part ${device} # set_property source_mgmt_mode DisplayOnly [current_project] # set_property top ${top} [current_fileset] # puts "Creating User Datapath reference project" Creating User Datapath reference project # create_fileset -constrset -quiet constraints # file copy ${public_repo_dir}/ ${repo_dir} # set_property ip_repo_paths ${repo_dir} [current_fileset] # add_files -fileset constraints -norecurse ${bit_settings} # add_files -fileset constraints -norecurse ${project_constraints} # add_files -fileset constraints -norecurse ${nf_10g_constraints} # set_property is_enabled true [get_files ${project_constraints}] # set_property is_enabled true [get_files ${bit_settings}] # set_property is_enabled true [get_files ${nf_10g_constraints}] # set_property constrset constraints [get_runs synth_1] # set_property constrset constraints [get_runs impl_1] # update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'. # create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip # set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci] # reset_target all [get_ips input_arbiter_ip] # generate_target all [get_ips input_arbiter_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'input_arbiter_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'input_arbiter_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'input_arbiter_ip'... # create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip # set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci] # reset_target all [get_ips sss_output_queues_ip] # generate_target all [get_ips sss_output_queues_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'sss_output_queues_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'sss_output_queues_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'sss_output_queues_ip'... # source ./tcl/control_sub.tcl ## set scripts_vivado_version 2018.2 ## set current_vivado_version [version -short] ## if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { ## puts "" ## puts "ERROR: This script was created for Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script." ## ## return 1 ## } ## set design_name control_sub ## if { [get_projects -quiet] eq "" } { ## puts "ERROR: Please open or create a project!" ## return 1 ## } ## set errMsg "" ## set nRet 0 ## set cur_design [current_bd_design -quiet] ## set list_cells [get_bd_cells -quiet] ## if { ${design_name} eq "" } { ## # USE CASES: ## # 1) Design_name not set ## ## set errMsg "ERROR: Please set the variable to a non-empty value." ## set nRet 1 ## ## } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { ## # USE CASES: ## # 2): Current design opened AND is empty AND names same. ## # 3): Current design opened AND is empty AND names diff; design_name NOT in project. ## # 4): Current design opened AND is empty AND names diff; design_name exists in project. ## ## if { $cur_design ne $design_name } { ## puts "INFO: Changing value of from <$design_name> to <$cur_design> since current design is empty." ## set design_name [get_property NAME $cur_design] ## } ## puts "INFO: Constructing design in IPI design <$cur_design>..." ## ## } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { ## # USE CASES: ## # 5) Current design opened AND has components AND same names. ## ## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." ## set nRet 1 ## } elseif { [get_files -quiet ${design_name}.bd] ne "" } { ## # USE CASES: ## # 6) Current opened design, has components, but diff names, design_name exists in project. ## # 7) No opened design, design_name exists in project. ## ## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." ## set nRet 2 ## ## } else { ## # USE CASES: ## # 8) No opened design, design_name not in project. ## # 9) Current opened design, has components, but diff names, design_name not in project. ## ## puts "INFO: Currently there is no design <$design_name> in project, so creating one..." ## ## create_bd_design $design_name ## ## puts "INFO: Making design <$design_name> as current_bd_design." ## current_bd_design $design_name ## ## } INFO: Currently there is no design in project, so creating one... Wrote : INFO: Making design as current_bd_design. ## puts "INFO: Currently the variable is equal to \"$design_name\"." INFO: Currently the variable is equal to "control_sub". ## if { $nRet != 0 } { ## puts $errMsg ## return $nRet ## } ## proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } { ## ## if { $parentCell eq "" || $nameHier eq "" } { ## puts "ERROR: create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!" ## return ## } ## ## # Get object for parentCell ## set parentObj [get_bd_cells $parentCell] ## if { $parentObj == "" } { ## puts "ERROR: Unable to find parent cell <$parentCell>!" ## return ## } ## ## # Make sure parentObj is hier blk ## set parentType [get_property TYPE $parentObj] ## if { $parentType ne "hier" } { ## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." ## return ## } ## ## # Save current instance; Restore later ## set oldCurInst [current_bd_instance .] ## ## # Set parent object as current ## current_bd_instance $parentObj ## ## # Create cell and set as current instance ## set hier_obj [create_bd_cell -type hier $nameHier] ## current_bd_instance $hier_obj ## ## # Create interface pins ## create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB ## create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB ## ## # Create pins ## create_bd_pin -dir I -type clk LMB_Clk ## create_bd_pin -dir I -from 0 -to 0 -type rst LMB_Rst ## ## # Create instance: dlmb_bram_if_cntlr, and set properties ## set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ] ## set_property -dict [ list CONFIG.C_ECC {0} ] $dlmb_bram_if_cntlr ## ## # Create instance: dlmb_v10, and set properties ## set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ] ## ## # Create instance: ilmb_bram_if_cntlr, and set properties ## set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ] ## set_property -dict [ list CONFIG.C_ECC {0} ] $ilmb_bram_if_cntlr ## ## # Create instance: ilmb_v10, and set properties ## set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ] ## ## # Create instance: lmb_bram, and set properties ## set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ] ## set_property -dict [ list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller} ] $lmb_bram ## ## # Create interface connections ## connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M] ## connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0] ## connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA] ## connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M] ## connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0] ## connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB] ## ## # Create port connections ## connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk] ## connect_bd_net -net microblaze_0_LMB_Rst [get_bd_pins LMB_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst] ## ## # Restore current instance ## current_bd_instance $oldCurInst ## } ## proc create_hier_cell_mbsys { parentCell nameHier } { ## ## if { $parentCell eq "" || $nameHier eq "" } { ## puts "ERROR: create_hier_cell_mbsys() - Empty argument(s)!" ## return ## } ## ## # Get object for parentCell ## set parentObj [get_bd_cells $parentCell] ## if { $parentObj == "" } { ## puts "ERROR: Unable to find parent cell <$parentCell>!" ## return ## } ## ## # Make sure parentObj is hier blk ## set parentType [get_property TYPE $parentObj] ## if { $parentType ne "hier" } { ## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." ## return ## } ## ## # Save current instance; Restore later ## set oldCurInst [current_bd_instance .] ## ## # Set parent object as current ## current_bd_instance $parentObj ## ## # Create cell and set as current instance ## set hier_obj [create_bd_cell -type hier $nameHier] ## current_bd_instance $hier_obj ## ## # Create interface pins ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ## ## # Create pins ## create_bd_pin -dir I -type clk Clk ## create_bd_pin -dir I -from 0 -to 0 In0 ## create_bd_pin -dir I -from 0 -to 0 In1 ## create_bd_pin -dir I dcm_locked ## create_bd_pin -dir I -type rst ext_reset_in ## create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn ## ## # Create instance: mdm_1, and set properties ## set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ] ## ## # Create instance: microblaze_0, and set properties ## set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:10.0 microblaze_0 ] ## set_property -dict [ list CONFIG.C_DEBUG_ENABLED {1} CONFIG.C_D_AXI {1} CONFIG.C_D_LMB {1} CONFIG.C_I_LMB {1} ] $microblaze_0 ## ## # Create instance: microblaze_0_axi_intc, and set properties ## set microblaze_0_axi_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 microblaze_0_axi_intc ] ## set_property -dict [ list CONFIG.C_HAS_FAST {1} ] $microblaze_0_axi_intc ## ## # Create instance: microblaze_0_axi_periph, and set properties ## set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ] ## set_property -dict [ list CONFIG.NUM_MI {3} ] $microblaze_0_axi_periph ## ## # Create instance: microblaze_0_local_memory ## create_hier_cell_microblaze_0_local_memory $hier_obj microblaze_0_local_memory ## ## # Create instance: microblaze_0_xlconcat, and set properties ## set microblaze_0_xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 microblaze_0_xlconcat ] ## ## # Create instance: rst_clk_wiz_1_100M, and set properties ## set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ] ## ## # Create interface connections ## connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins M01_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI] ## connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins M02_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI] ## connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI] ## connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG] ## connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB] ## connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB] ## connect_bd_intf_net -intf_net microblaze_0_intc_axi [get_bd_intf_pins microblaze_0_axi_intc/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI] ## connect_bd_intf_net -intf_net microblaze_0_interrupt [get_bd_intf_pins microblaze_0/INTERRUPT] [get_bd_intf_pins microblaze_0_axi_intc/interrupt] ## ## # Create port connections ## connect_bd_net -net In0_1 [get_bd_pins In0] [get_bd_pins microblaze_0_xlconcat/In0] ## connect_bd_net -net In1_1 [get_bd_pins In1] [get_bd_pins microblaze_0_xlconcat/In1] ## connect_bd_net -net clk_wiz_1_locked [get_bd_pins dcm_locked] [get_bd_pins rst_clk_wiz_1_100M/dcm_locked] ## connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/mb_debug_sys_rst] ## connect_bd_net -net microblaze_0_Clk [get_bd_pins Clk] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_intc/processor_clk] [get_bd_pins microblaze_0_axi_intc/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk] ## connect_bd_net -net microblaze_0_intr [get_bd_pins microblaze_0_axi_intc/intr] [get_bd_pins microblaze_0_xlconcat/dout] ## connect_bd_net -net reset_1 [get_bd_pins ext_reset_in] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in] ## connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/LMB_Rst] [get_bd_pins rst_clk_wiz_1_100M/bus_struct_reset] ## connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn] ## connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins microblaze_0_axi_intc/processor_rst] [get_bd_pins rst_clk_wiz_1_100M/mb_reset] ## connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins peripheral_aresetn] [get_bd_pins microblaze_0_axi_intc/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn] ## ## # Restore current instance ## current_bd_instance $oldCurInst ## } ## proc create_hier_cell_nf_mbsys { parentCell nameHier } { ## ## if { $parentCell eq "" || $nameHier eq "" } { ## puts "ERROR: create_hier_cell_nf_mbsys() - Empty argument(s)!" ## return ## } ## ## # Get object for parentCell ## set parentObj [get_bd_cells $parentCell] ## if { $parentObj == "" } { ## puts "ERROR: Unable to find parent cell <$parentCell>!" ## return ## } ## ## # Make sure parentObj is hier blk ## set parentType [get_property TYPE $parentObj] ## if { $parentType ne "hier" } { ## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." ## return ## } ## ## # Save current instance; Restore later ## set oldCurInst [current_bd_instance .] ## ## # Set parent object as current ## current_bd_instance $parentObj ## ## # Create cell and set as current instance ## set hier_obj [create_bd_cell -type hier $nameHier] ## current_bd_instance $hier_obj ## ## # Create interface pins ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fpga ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart ## ## # Create pins ## create_bd_pin -dir O -from 1 -to 0 iic_reset ## create_bd_pin -dir I -type rst reset ## create_bd_pin -dir I -type clk sysclk ## ## # Create instance: axi_iic_0, and set properties ## set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ] ## set_property -dict [ list CONFIG.C_GPO_WIDTH {2} CONFIG.C_SCL_INERTIAL_DELAY {5} CONFIG.C_SDA_INERTIAL_DELAY {5} ] $axi_iic_0 ## ## # Create instance: axi_uartlite_0, and set properties ## set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ] ## set_property -dict [ list CONFIG.C_BAUDRATE {115200} ] $axi_uartlite_0 ## ## # Create instance: clk_wiz_1, and set properties ## set clk_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_1 ] ## # set_property -dict [ list CONFIG.PRIM_IN_FREQ {200.000} CONFIG.PRIM_SOURCE {No_buffer} ] $clk_wiz_1 ## ## # config 100MHz input clk ## set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} CONFIG.PRIM_SOURCE {No_buffer} \ ## CONFIG.CLKIN1_JITTER_PS {100.0} CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} \ ## CONFIG.MMCM_CLKIN1_PERIOD {10.0} CONFIG.CLKOUT1_JITTER {130.958} \ ## CONFIG.CLKOUT1_PHASE_ERROR {98.575}] $clk_wiz_1 ## ## ## # Create instance: mbsys ## create_hier_cell_mbsys $hier_obj mbsys ## ## # Create interface connections ## connect_bd_intf_net -intf_net axi_iic_0_IIC [get_bd_intf_pins iic_fpga] [get_bd_intf_pins axi_iic_0/IIC] ## connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_pins uart] [get_bd_intf_pins axi_uartlite_0/UART] ## connect_bd_intf_net -intf_net mbsys_M01_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins mbsys/M01_AXI] ## connect_bd_intf_net -intf_net mbsys_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins mbsys/M02_AXI] ## ## # Create port connections ## connect_bd_net -net axi_iic_0_gpo [get_bd_pins iic_reset] [get_bd_pins axi_iic_0/gpo] ## connect_bd_net -net axi_iic_0_iic2intc_irpt [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins mbsys/In0] ## connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins mbsys/In1] ## connect_bd_net -net clk_wiz_1_locked [get_bd_pins clk_wiz_1/locked] [get_bd_pins mbsys/dcm_locked] ## connect_bd_net -net mbsys_peripheral_aresetn [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins mbsys/peripheral_aresetn] ## connect_bd_net -net microblaze_0_Clk [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins clk_wiz_1/clk_out1] [get_bd_pins mbsys/Clk] ## connect_bd_net -net reset_1 [get_bd_pins reset] [get_bd_pins clk_wiz_1/reset] [get_bd_pins mbsys/ext_reset_in] ## connect_bd_net -net sysclk_1 [get_bd_pins sysclk] [get_bd_pins clk_wiz_1/clk_in1] ## ## # Restore current instance ## current_bd_instance $oldCurInst ## } ## proc create_hier_cell_dma_sub { parentCell nameHier } { ## ## if { $parentCell eq "" || $nameHier eq "" } { ## puts "ERROR: create_hier_cell_dma_sub() - Empty argument(s)!" ## return ## } ## ## # Get object for parentCell ## set parentObj [get_bd_cells $parentCell] ## if { $parentObj == "" } { ## puts "ERROR: Unable to find parent cell <$parentCell>!" ## return ## } ## ## # Make sure parentObj is hier blk ## set parentType [get_property TYPE $parentObj] ## if { $parentType ne "hier" } { ## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." ## return ## } ## ## # Save current instance; Restore later ## set oldCurInst [current_bd_instance .] ## ## # Set parent object as current ## current_bd_instance $parentObj ## ## # Create cell and set as current instance ## set hier_obj [create_bd_cell -type hier $nameHier] ## current_bd_instance $hier_obj ## ## # Create interface pins ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma_tx ## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_7x_mgt ## create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma_rx ## ## # Create pins ## create_bd_pin -dir I -type clk axi_lite_aclk ## create_bd_pin -dir I -type rst axi_lite_aresetn ## create_bd_pin -dir I -type clk axis_datapath_aclk ## create_bd_pin -dir I -type rst axis_datapath_aresetn ## create_bd_pin -dir I -type clk sys_clk ## create_bd_pin -dir I -type rst sys_reset ## ## create_bd_pin -dir I -type clk M00_ACLK ## create_bd_pin -dir I -type rst M00_ARESETN ## create_bd_pin -dir I -type clk M01_ACLK ## create_bd_pin -dir I -type rst M01_ARESETN ## create_bd_pin -dir I -type clk M02_ACLK ## create_bd_pin -dir I -type rst M02_ARESETN ## create_bd_pin -dir I -type clk M03_ACLK ## create_bd_pin -dir I -type rst M03_ARESETN ## create_bd_pin -dir I -type clk M04_ACLK ## create_bd_pin -dir I -type rst M04_ARESETN ## create_bd_pin -dir I -type clk M05_ACLK ## create_bd_pin -dir I -type rst M05_ARESETN ## create_bd_pin -dir I -type clk M06_ACLK ## create_bd_pin -dir I -type rst M06_ARESETN ## create_bd_pin -dir I -type clk M07_ACLK ## create_bd_pin -dir I -type rst M07_ARESETN ## ## # Create instance: axi_interconnect_0, and set properties ## set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] ## set_property -dict [ list CONFIG.NUM_MI {9} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M00_HAS_REGSLICE {3} CONFIG.M00_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M01_HAS_REGSLICE {3} CONFIG.M01_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M02_HAS_REGSLICE {3} CONFIG.M02_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M03_HAS_REGSLICE {3} CONFIG.M03_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M04_HAS_REGSLICE {3} CONFIG.M04_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M05_HAS_REGSLICE {3} CONFIG.M05_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M06_HAS_REGSLICE {3} CONFIG.M06_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M07_HAS_REGSLICE {3} CONFIG.M07_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.M08_HAS_REGSLICE {3} CONFIG.M08_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## set_property -dict [list CONFIG.S00_HAS_REGSLICE {3} CONFIG.S00_HAS_DATA_FIFO {1} ] $axi_interconnect_0 ## ## # AXIS: clock domain crossing FIFO, TX (PCIe->FPGA) user_fifo_reset (user_clk) ## set pcie_reset_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic pcie_reset_inv] ## set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {not}] [get_bd_cells pcie_reset_inv] ## ## # Create instance: axis_dwidth_converter ## set axis_dwidth_dma_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_dma_tx] ## set_property -dict [list CONFIG.HAS_TKEEP.VALUE_SRC USER CONFIG.HAS_TLAST.VALUE_SRC USER \ ## CONFIG.HAS_TSTRB.VALUE_SRC USER CONFIG.S_TDATA_NUM_BYTES.VALUE_SRC USER \ ## CONFIG.TUSER_BITS_PER_BYTE.VALUE_SRC USER] $axis_dwidth_dma_tx ## ## set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {16} CONFIG.M_TDATA_NUM_BYTES {32} \ ## CONFIG.TUSER_BITS_PER_BYTE {8} CONFIG.HAS_TLAST {1} CONFIG.HAS_TSTRB {0} \ ## CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1}] $axis_dwidth_dma_tx ## ## ## ## set axis_dwidth_dma_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_dma_rx] ## ## set_property -dict [list CONFIG.HAS_TKEEP.VALUE_SRC USER CONFIG.HAS_TLAST.VALUE_SRC USER \ ## CONFIG.HAS_TSTRB.VALUE_SRC USER CONFIG.S_TDATA_NUM_BYTES.VALUE_SRC USER \ ## CONFIG.TUSER_BITS_PER_BYTE.VALUE_SRC USER] $axis_dwidth_dma_rx ## ## set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {32} CONFIG.M_TDATA_NUM_BYTES {16} \ ## CONFIG.TUSER_BITS_PER_BYTE {8} CONFIG.HAS_TLAST {1} CONFIG.HAS_TSTRB {0} \ ## CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1}] $axis_dwidth_dma_rx ## ## # Create instance: axis_fifo_10g_rx, and set properties ## set axis_fifo_10g_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_fifo_10g_rx] ## set_property -dict [list CONFIG.TDATA_NUM_BYTES {16} CONFIG.TUSER_WIDTH {128} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32}] $axis_fifo_10g_rx ## ## # Create instance: axis_fifo_10g_tx, and set properties ## set axis_fifo_10g_tx [create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_fifo_10g_tx] ## set_property -dict [list CONFIG.TDATA_NUM_BYTES {16} CONFIG.TUSER_WIDTH {128} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32}] $axis_fifo_10g_tx ## ## # Create instance: nf_riffa_dma_1, and set properties ## set nf_riffa_dma_1 [ create_bd_cell -type ip -vlnv NetFPGA:NetFPGA:nf_riffa_dma:1.0 nf_riffa_dma_1 ] ## ## # Create instance: axi_clock_converter_0, and set properties ## set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ] ## ## # Create instance: pcie3_7x_1, and set properties ## set pcie3_7x_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:pcie3_7x:4.3 pcie3_7x_1 ] ## set_property -dict [ list CONFIG.PF0_DEVICE_ID {7028} \ ## CONFIG.PF0_INTERRUPT_PIN {NONE} CONFIG.PF1_DEVICE_ID {7011} \ ## CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {5.0_GT/s} CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ ## CONFIG.axisten_freq {250} CONFIG.axisten_if_enable_client_tag {false} \ ## CONFIG.axisten_if_width {128_bit} CONFIG.cfg_ctl_if {false} \ ## CONFIG.cfg_ext_if {false} CONFIG.cfg_mgmt_if {false} \ ## CONFIG.cfg_tx_msg_if {false} CONFIG.en_ext_clk {false} \ ## CONFIG.extended_tag_field {true} CONFIG.gen_x0y0 {false} \ ## CONFIG.mode_selection {Advanced} CONFIG.pcie_blk_locn {X0Y1} \ ## CONFIG.per_func_status_if {false} CONFIG.pf0_bar0_size {1} \ ## CONFIG.pf0_dev_cap_max_payload {128_bytes} CONFIG.rcv_msg_if {false} \ ## CONFIG.tx_fc_if {false} CONFIG.xlnx_ref_board {None} \ ## ] $pcie3_7x_1 ## ## # Create interface connections ## connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins M01_AXI] [get_bd_intf_pins axi_interconnect_0/M01_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins M02_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins M03_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins M04_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins M05_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins M06_AXI] [get_bd_intf_pins axi_interconnect_0/M06_AXI] ## connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins M07_AXI] [get_bd_intf_pins axi_interconnect_0/M07_AXI] ## ## connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_dma_rx [get_bd_intf_pins s_axis_dma_rx] [get_bd_intf_pins axis_dwidth_dma_rx/S_AXIS] ## connect_bd_intf_net -intf_net nf_riffa_dma_1_fifo_dwidth_rx [get_bd_intf_pins axis_fifo_10g_rx/S_AXIS] [get_bd_intf_pins axis_dwidth_dma_rx/M_AXIS] ## connect_bd_intf_net -intf_net axis_fifo_10g_rx_M_AXIS [get_bd_intf_pins axis_fifo_10g_rx/M_AXIS] [get_bd_intf_pins nf_riffa_dma_1/s_axis_xge_rx] ## ## ## connect_bd_intf_net -intf_net nf_riffa_dma_1_m_axis_dma_tx [get_bd_intf_pins m_axis_dma_tx] [get_bd_intf_pins axis_dwidth_dma_tx/M_AXIS] ## connect_bd_intf_net -intf_net nf_riffa_dma_1_fifo_dwidth_tx [get_bd_intf_pins axis_fifo_10g_tx/M_AXIS] [get_bd_intf_pins axis_dwidth_dma_tx/S_AXIS] ## connect_bd_intf_net -intf_net nf_riffa_dma_1_dwidth_conv_tx [get_bd_intf_pins axis_fifo_10g_tx/S_AXIS] [get_bd_intf_pins nf_riffa_dma_1/m_axis_xge_tx] ## ## ## ## connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_interrupt [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_interrupt] ## connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_msi [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt_msi] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_msi] ## connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_status [get_bd_intf_pins nf_riffa_dma_1/cfg] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_status] ## connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie_cfg_fc [get_bd_intf_pins nf_riffa_dma_1/cfg_fc] [get_bd_intf_pins pcie3_7x_1/pcie_cfg_fc] ## connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_cc [get_bd_intf_pins nf_riffa_dma_1/s_axis_cc] [get_bd_intf_pins pcie3_7x_1/s_axis_cc] ## connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_rq [get_bd_intf_pins nf_riffa_dma_1/s_axis_rq] [get_bd_intf_pins pcie3_7x_1/s_axis_rq] ## connect_bd_intf_net -intf_net pcie3_7x_1_m_axis_cq [get_bd_intf_pins nf_riffa_dma_1/m_axis_cq] [get_bd_intf_pins pcie3_7x_1/m_axis_cq] ## connect_bd_intf_net -intf_net pcie3_7x_1_m_axis_rc [get_bd_intf_pins nf_riffa_dma_1/m_axis_rc] [get_bd_intf_pins pcie3_7x_1/m_axis_rc] ## connect_bd_intf_net -intf_net pcie3_7x_1_pcie_7x_mgt [get_bd_intf_pins pcie_7x_mgt] [get_bd_intf_pins pcie3_7x_1/pcie_7x_mgt] ## connect_bd_intf_net -intf_net s00_axi_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins nf_riffa_dma_1/m_axi_lite] ## ## #Clock converter connections ## connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins nf_riffa_dma_1/s_axi_lite] ## connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M08_AXI] ## set_property -dict [ list CONFIG.FREQ_HZ {250000000} ] [get_bd_intf_pins nf_riffa_dma_1/s_axi_lite] ## ## ## ## # Create port connections ## connect_bd_net -net axi_lite_clk_1 [get_bd_pins axi_lite_aclk] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins nf_riffa_dma_1/m_axi_lite_aclk] ## ## ## connect_bd_net -net M00_ACLK_i [get_bd_pins M00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] ## connect_bd_net -net M01_ACLK_i [get_bd_pins M01_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] ## connect_bd_net -net M02_ACLK_i [get_bd_pins M02_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] ## connect_bd_net -net M03_ACLK_i [get_bd_pins M03_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] ## connect_bd_net -net M04_ACLK_i [get_bd_pins M04_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] ## connect_bd_net -net M05_ACLK_i [get_bd_pins M05_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] ## connect_bd_net -net M06_ACLK_i [get_bd_pins M06_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] ## connect_bd_net -net M07_ACLK_i [get_bd_pins M07_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] ## ## connect_bd_net -net axi_lite_rstn_1 [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_lite_aresetn] [get_bd_pins nf_riffa_dma_1/m_axi_lite_aresetn] ## ## ## connect_bd_net -net M00_ARESETN_i [get_bd_pins M00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] ## connect_bd_net -net M01_ARESETN_i [get_bd_pins M01_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] ## connect_bd_net -net M02_ARESETN_i [get_bd_pins M02_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] ## connect_bd_net -net M03_ARESETN_i [get_bd_pins M03_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] ## connect_bd_net -net M04_ARESETN_i [get_bd_pins M04_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] ## connect_bd_net -net M05_ARESETN_i [get_bd_pins M05_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] ## connect_bd_net -net M06_ARESETN_i [get_bd_pins M06_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] ## connect_bd_net -net M07_ARESETN_i [get_bd_pins M07_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] ## ## connect_bd_net -net axis_10g_clk_1 [get_bd_pins axis_datapath_aclk] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axis_dwidth_dma_rx/aclk] [get_bd_pins axis_dwidth_dma_tx/aclk] [get_bd_pins axis_fifo_10g_rx/s_axis_aclk] [get_bd_pins axis_fifo_10g_tx/m_axis_aclk] ## ## connect_bd_net -net axis_rx_sys_reset_0_peripheral_aresetn [get_bd_pins axis_datapath_aresetn] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axis_dwidth_dma_rx/aresetn] [get_bd_pins axis_dwidth_dma_tx/aresetn] [get_bd_pins axis_fifo_10g_rx/s_axis_aresetn] [get_bd_pins axis_fifo_10g_tx/m_axis_aresetn] ## ## connect_bd_net -net axis_tx_sys_reset_0_peripheral_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axis_fifo_10g_rx/m_axis_aresetn] [get_bd_pins axis_fifo_10g_tx/s_axis_aresetn] [get_bd_pins pcie_reset_inv/Res] ## ## connect_bd_net -net pcie3_7x_1_user_clk [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axis_fifo_10g_rx/m_axis_aclk] [get_bd_pins axis_fifo_10g_tx/s_axis_aclk] [get_bd_pins nf_riffa_dma_1/user_clk] [get_bd_pins pcie3_7x_1/user_clk] ## ## connect_bd_net -net pcie3_7x_1_user_lnk_up [get_bd_pins nf_riffa_dma_1/user_lnk_up] [get_bd_pins pcie3_7x_1/user_lnk_up] ## connect_bd_net -net pcie3_7x_1_user_reset [get_bd_pins pcie_reset_inv/Op1] [get_bd_pins nf_riffa_dma_1/user_reset] [get_bd_pins pcie3_7x_1/user_reset] ## connect_bd_net -net sys_clk_1 [get_bd_pins sys_clk] [get_bd_pins pcie3_7x_1/sys_clk] ## connect_bd_net -net sys_reset_1 [get_bd_pins sys_reset] [get_bd_pins pcie3_7x_1/sys_reset] ## ## # Restore current instance ## current_bd_instance $oldCurInst ## } ## proc create_root_design { parentCell } { ## ## if { $parentCell eq "" } { ## set parentCell [get_bd_cells /] ## } ## ## # Get object for parentCell ## set parentObj [get_bd_cells $parentCell] ## if { $parentObj == "" } { ## puts "ERROR: Unable to find parent cell <$parentCell>!" ## return ## } ## ## # Make sure parentObj is hier blk ## set parentType [get_property TYPE $parentObj] ## if { $parentType ne "hier" } { ## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." ## return ## } ## ## # Save current instance; Restore later ## set oldCurInst [current_bd_instance .] ## ## # Set parent object as current ## current_bd_instance $parentObj ## ## ## # Create interface ports ## set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M00_AXI ## set M01_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M01_AXI ## set M02_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M02_AXI ## set M03_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M03_AXI ## set M04_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M04_AXI ## set M05_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M05_AXI ## set M06_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M06_AXI ## set M07_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI ] ## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M07_AXI ## set iic_fpga [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fpga ] ## set m_axis_dma_tx [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma_tx ] ## set pcie_7x_mgt [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_7x_mgt ] ## set s_axis_dma_rx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma_rx ] ## set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} CONFIG.HAS_TREADY {1} CONFIG.HAS_TSTRB {0} CONFIG.LAYERED_METADATA {undef} CONFIG.PHASE {0.000} CONFIG.TDATA_NUM_BYTES {32} CONFIG.TDEST_WIDTH {0} CONFIG.TID_WIDTH {0} CONFIG.TUSER_WIDTH {128} ] $s_axis_dma_rx ## set uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart ] ## ## # Create ports ## set axi_lite_aclk [ create_bd_port -dir I -type clk axi_lite_aclk ] ## set axi_lite_aresetn [ create_bd_port -dir I -type rst axi_lite_aresetn ] ## set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}] $axi_lite_aresetn ## set axis_datapath_aclk [ create_bd_port -dir I -type clk axis_datapath_aclk ] ## set axis_datapath_aresetn [ create_bd_port -dir I -type rst axis_datapath_aresetn ] ## set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $axis_datapath_aresetn ## set iic_reset [ create_bd_port -dir O -from 1 -to 0 iic_reset ] ## set sys_clk [ create_bd_port -dir I -type clk sys_clk ] ## set_property -dict [ list CONFIG.FREQ_HZ {100000000} ] $sys_clk ## set sys_reset [ create_bd_port -dir I -type rst sys_reset ] ## set_property -dict [ list CONFIG.POLARITY {ACTIVE_HIGH} ] $sys_reset ## ## ## ## # Create instance: dma_sub ## create_hier_cell_dma_sub [current_bd_instance .] dma_sub ## ## # Create instance: nf_mbsys ## create_hier_cell_nf_mbsys [current_bd_instance .] nf_mbsys ## ## # Create interface connections ## connect_bd_intf_net -intf_net dma_sub_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins dma_sub/M00_AXI] ## connect_bd_intf_net -intf_net dma_sub_M01_AXI [get_bd_intf_ports M01_AXI] [get_bd_intf_pins dma_sub/M01_AXI] ## connect_bd_intf_net -intf_net dma_sub_M02_AXI [get_bd_intf_ports M02_AXI] [get_bd_intf_pins dma_sub/M02_AXI] ## connect_bd_intf_net -intf_net dma_sub_M03_AXI [get_bd_intf_ports M03_AXI] [get_bd_intf_pins dma_sub/M03_AXI] ## connect_bd_intf_net -intf_net dma_sub_M04_AXI [get_bd_intf_ports M04_AXI] [get_bd_intf_pins dma_sub/M04_AXI] ## connect_bd_intf_net -intf_net dma_sub_M05_AXI [get_bd_intf_ports M05_AXI] [get_bd_intf_pins dma_sub/M05_AXI] ## connect_bd_intf_net -intf_net dma_sub_M06_AXI [get_bd_intf_ports M06_AXI] [get_bd_intf_pins dma_sub/M06_AXI] ## connect_bd_intf_net -intf_net dma_sub_M07_AXI [get_bd_intf_ports M07_AXI] [get_bd_intf_pins dma_sub/M07_AXI] ## connect_bd_intf_net -intf_net dma_sub_m_axis_dma_tx [get_bd_intf_ports m_axis_dma_tx] [get_bd_intf_pins dma_sub/m_axis_dma_tx] ## connect_bd_intf_net -intf_net dma_sub_pcie_7x_mgt [get_bd_intf_ports pcie_7x_mgt] [get_bd_intf_pins dma_sub/pcie_7x_mgt] ## connect_bd_intf_net -intf_net nf_mbsys_iic_fpga [get_bd_intf_ports iic_fpga] [get_bd_intf_pins nf_mbsys/iic_fpga] ## connect_bd_intf_net -intf_net nf_mbsys_uart [get_bd_intf_ports uart] [get_bd_intf_pins nf_mbsys/uart] ## connect_bd_intf_net -intf_net s_axis_dma_rx_1 [get_bd_intf_ports s_axis_dma_rx] [get_bd_intf_pins dma_sub/s_axis_dma_rx] ## ## # Create port connections ## connect_bd_net -net axi_lite_aclk_1 [get_bd_ports axi_lite_aclk] [get_bd_pins dma_sub/axi_lite_aclk] ## connect_bd_net -net axi_lite_aresetn_1 [get_bd_ports axi_lite_aresetn] [get_bd_pins dma_sub/axi_lite_aresetn] ## connect_bd_net -net axis_datapath_aclk_1 [get_bd_ports axis_datapath_aclk] [get_bd_pins dma_sub/axis_datapath_aclk] [get_bd_pins dma_sub/M00_ACLK] [get_bd_pins dma_sub/M01_ACLK] [get_bd_pins dma_sub/M02_ACLK] [get_bd_pins dma_sub/M03_ACLK] [get_bd_pins dma_sub/M04_ACLK] [get_bd_pins dma_sub/M05_ACLK] [get_bd_pins dma_sub/M06_ACLK] [get_bd_pins dma_sub/M07_ACLK] ## connect_bd_net -net axis_datapath_aresetn_1 [get_bd_ports axis_datapath_aresetn] [get_bd_pins dma_sub/axis_datapath_aresetn] [get_bd_pins dma_sub/M00_ARESETN] [get_bd_pins dma_sub/M01_ARESETN] [get_bd_pins dma_sub/M02_ARESETN] [get_bd_pins dma_sub/M03_ARESETN] [get_bd_pins dma_sub/M04_ARESETN] [get_bd_pins dma_sub/M05_ARESETN] [get_bd_pins dma_sub/M06_ARESETN] [get_bd_pins dma_sub/M07_ARESETN] ## connect_bd_net -net nf_mbsys_iic_reset [get_bd_ports iic_reset] [get_bd_pins nf_mbsys/iic_reset] ## connect_bd_net -net sys_clk_1 [get_bd_ports sys_clk] [get_bd_pins dma_sub/sys_clk] [get_bd_pins nf_mbsys/sysclk] ## connect_bd_net -net sys_reset_1 [get_bd_ports sys_reset] [get_bd_pins dma_sub/sys_reset] [get_bd_pins nf_mbsys/reset] ## ## ## # Create address segments ## source ./tcl/$::env(NF_PROJECT_NAME)_defines.tcl ## create_bd_addr_seg -range $M00_SIZEADDR -offset $M00_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg ## create_bd_addr_seg -range $M01_SIZEADDR -offset $M01_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M01_AXI/Reg] SEG_M01_AXI_Reg ## create_bd_addr_seg -range $M02_SIZEADDR -offset $M02_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M02_AXI/Reg] SEG_M02_AXI_Reg ## create_bd_addr_seg -range $M03_SIZEADDR -offset $M03_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M03_AXI/Reg] SEG_M03_AXI_Reg ## create_bd_addr_seg -range $M04_SIZEADDR -offset $M04_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M04_AXI/Reg] SEG_M04_AXI_Reg ## create_bd_addr_seg -range $M05_SIZEADDR -offset $M05_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M05_AXI/Reg] SEG_M05_AXI_Reg ## create_bd_addr_seg -range $M06_SIZEADDR -offset $M06_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M06_AXI/Reg] SEG_M06_AXI_Reg ## create_bd_addr_seg -range $M07_SIZEADDR -offset $M07_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M07_AXI/Reg] SEG_M07_AXI_Reg ## create_bd_addr_seg -range $M08_SIZEADDR -offset $M08_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs dma_sub/nf_riffa_dma_1/s_axi_lite/reg0] SEG_nf_riffa_dma_1_reg0 ## ## create_bd_addr_seg -range $MICROBLAZE_AXI_IIC_SIZEADDR -offset $MICROBLAZE_AXI_IIC_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg ## create_bd_addr_seg -range $MICROBLAZE_UARTLITE_SIZEADDR -offset $MICROBLAZE_UARTLITE_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg ## create_bd_addr_seg -range $MICROBLAZE_DLMB_BRAM_SIZEADDR -offset $MICROBLAZE_DLMB_BRAM_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem ## create_bd_addr_seg -range $MICROBLAZE_ILMB_BRAM_SIZEADDR -offset $MICROBLAZE_ILMB_BRAM_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Instruction] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem ## create_bd_addr_seg -range $MICROBLAZE_AXI_INTC_SIZEADDR -offset $MICROBLAZE_AXI_INTC_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_axi_intc/s_axi/Reg] SEG_microblaze_0_axi_intc_Reg ## ## ## # Restore current instance ## current_bd_instance $oldCurInst ## ## save_bd_design ## } ## create_root_design "" CRITICAL WARNING: [BD 41-737] Cannot set the parameter FREQ_HZ on /dma_sub/nf_riffa_dma_1/s_axi_lite. It is read-only. create_bd_cell: Time (s): cpu = 00:00:23 ; elapsed = 00:00:59 . Memory (MB): peak = 1708.625 ; gain = 286.730 ; free physical = 8951 ; free virtual = 28748 WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '10.000' to '10.0' has been ignored for IP 'nf_mbsys/clk_wiz_1' INFO: [Device 21-403] Loading part xc7vx690tffg1761-3 ### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 ### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF ### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 ### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 ### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF ### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 ### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 ### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF ### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 ### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 ### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF ### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 ### set M00_BASEADDR 0x44000000 ### set M00_HIGHADDR 0x44000FFF ### set M00_SIZEADDR 0x1000 ### set M01_BASEADDR 0x44010000 ### set M01_HIGHADDR 0x44010FFF ### set M01_SIZEADDR 0x1000 ### set M02_BASEADDR 0x44020000 ### set M02_HIGHADDR 0x44020FFF ### set M02_SIZEADDR 0x1000 ### set M03_BASEADDR 0x44030000 ### set M03_HIGHADDR 0x44030FFF ### set M03_SIZEADDR 0x1000 ### set M04_BASEADDR 0x44040000 ### set M04_HIGHADDR 0x44040FFF ### set M04_SIZEADDR 0x1000 ### set M05_BASEADDR 0x44050000 ### set M05_HIGHADDR 0x44050FFF ### set M05_SIZEADDR 0x1000 ### set M06_BASEADDR 0x44060000 ### set M06_HIGHADDR 0x44060FFF ### set M06_SIZEADDR 0x1000 ### set M07_BASEADDR 0x44070000 ### set M07_HIGHADDR 0x44070FFF ### set M07_SIZEADDR 0x1000 ### set M08_BASEADDR 0x44080000 ### set M08_HIGHADDR 0x44080FFF ### set M08_SIZEADDR 0x1000 ### set IDENTIFIER_BASEADDR $M00_BASEADDR ### set IDENTIFIER_HIGHADDR $M00_HIGHADDR ### set IDENTIFIER_SIZEADDR $M00_SIZEADDR ### set INPUT_ARBITER_BASEADDR $M01_BASEADDR ### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR ### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR ### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR ### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR ### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR ### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR ### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR ### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR ### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR ### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR ### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR ### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR ### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR ### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR ### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR ### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR ### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR ### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR ### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR ### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR ### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR ### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR ### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR Wrote : # create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip # set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci] # reset_target all [get_ips nf_sume_sdnet_ip] # generate_target all [get_ips nf_sume_sdnet_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_sume_sdnet_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_sume_sdnet_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_sume_sdnet_ip'... # source ./create_ip/nf_10ge_interface.tcl ## set sharedLogic "FALSE" ## set tdataWidth 256 ## set convWidth [expr $tdataWidth/8] ## if { $sharedLogic eq "True" || $sharedLogic eq "TRUE" || $sharedLogic eq "true" } { ## set supportLevel 1 ## } else { ## set supportLevel 0 ## } ## create_ip -name axi_10g_ethernet -vendor xilinx.com -library ip -version 3.1 -module_name axi_10g_ethernet_nonshared WARNING: [IP_Flow 19-4832] The IP name 'axi_10g_ethernet_nonshared' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues. ## set_property -dict [list CONFIG.Management_Interface {false}] [get_ips axi_10g_ethernet_nonshared] WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}' ## set_property -dict [list CONFIG.base_kr {BASE-R}] [get_ips axi_10g_ethernet_nonshared] WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}' ## set_property -dict [list CONFIG.SupportLevel $supportLevel] [get_ips axi_10g_ethernet_nonshared] ## set_property -dict [list CONFIG.autonegotiation {0}] [get_ips axi_10g_ethernet_nonshared] ## set_property -dict [list CONFIG.fec {0}] [get_ips axi_10g_ethernet_nonshared] ## set_property -dict [list CONFIG.Statistics_Gathering {0}] [get_ips axi_10g_ethernet_nonshared] ## set_property generate_synth_checkpoint false [get_files axi_10g_ethernet_nonshared.xci] ## reset_target all [get_ips axi_10g_ethernet_nonshared] ## generate_target all [get_ips axi_10g_ethernet_nonshared] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_10g_ethernet_nonshared'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_10g_ethernet_nonshared'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_10g_ethernet_nonshared'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axi_10g_ethernet_nonshared'... WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license. WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license. WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license. WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license. Exporting to file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/hw_handoff/axi_10g_ethernet_nonshared.hwh Generated Block Design Tcl file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/hw_handoff/axi_10g_ethernet_nonshared_bd.tcl Generated Hardware Definition File /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/synth/axi_10g_ethernet_nonshared.hwdef generate_target: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1949.988 ; gain = 44.473 ; free physical = 8682 ; free virtual = 28532 ## create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_status ## set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] [get_ips fifo_generator_status] ## set_property -dict [list CONFIG.Performance_Options {First_Word_Fall_Through}] [get_ips fifo_generator_status] ## set_property -dict [list CONFIG.Input_Data_Width {458} CONFIG.Input_Depth {16}] [get_ips fifo_generator_status] ## set_property -dict [list CONFIG.Reset_Pin {false}] [get_ips fifo_generator_status] ## set_property -dict [list CONFIG.Output_Data_Width {458} CONFIG.Output_Depth {16}] [get_ips fifo_generator_status] ## set_property -dict [list CONFIG.Full_Flags_Reset_Value {0}] [get_ips fifo_generator_status] ## set_property -dict [list CONFIG.Use_Dout_Reset {false}] [get_ips fifo_generator_status] ## set_property -dict [list CONFIG.Data_Count_Width {4}] [get_ips fifo_generator_status] ## set_property -dict [list CONFIG.Write_Data_Count_Width {4}] [get_ips fifo_generator_status] ## set_property -dict [list CONFIG.Read_Data_Count_Width {4}] [get_ips fifo_generator_status] ## set_property -dict [list CONFIG.Full_Threshold_Assert_Value {15}] [get_ips fifo_generator_status] ## set_property -dict [list CONFIG.Full_Threshold_Negate_Value {14}] [get_ips fifo_generator_status] ## set_property -dict [list CONFIG.Empty_Threshold_Assert_Value {4}] [get_ips fifo_generator_status] ## set_property -dict [list CONFIG.Empty_Threshold_Negate_Value {5}] [get_ips fifo_generator_status] ## set_property generate_synth_checkpoint false [get_files fifo_generator_status.xci] ## reset_target all [get_ips fifo_generator_status] ## generate_target all [get_ips fifo_generator_status] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fifo_generator_status'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_generator_status'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fifo_generator_status'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fifo_generator_status'... ## create_ip -name util_vector_logic -vendor xilinx.com -library ip -version 2.0 -module_name inverter_0 WARNING: [Coretcl 2-1618] The 'xilinx.com:ip:util_vector_logic:2.0' IP is intended for use in IPI only. ## set_property -dict [list CONFIG.C_SIZE {1}] [get_ips inverter_0] ## set_property -dict [list CONFIG.C_OPERATION {not}] [get_ips inverter_0] ## set_property generate_synth_checkpoint false [get_files inverter_0.xci] ## reset_target all [get_ips inverter_0] ## generate_target all [get_ips inverter_0] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'inverter_0'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'inverter_0'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'inverter_0'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'inverter_0'... ## create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_1_9 ## set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM} CONFIG.Performance_Options {First_Word_Fall_Through} CONFIG.Input_Data_Width {1} CONFIG.Input_Depth {16} CONFIG.Output_Data_Width {1} CONFIG.Output_Depth {16} CONFIG.Data_Count_Width {4} CONFIG.Write_Data_Count_Width {4} CONFIG.Read_Data_Count_Width {4} CONFIG.Full_Threshold_Assert_Value {13} CONFIG.Full_Threshold_Negate_Value {12}] [get_ips fifo_generator_1_9] WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Assert_Value' from '15' to '13' has been ignored for IP 'fifo_generator_1_9' WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Negate_Value' from '14' to '12' has been ignored for IP 'fifo_generator_1_9' ## set_property generate_synth_checkpoint false [get_files fifo_generator_1_9.xci] ## reset_target all [get_ips fifo_generator_1_9] ## generate_target all [get_ips fifo_generator_1_9] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fifo_generator_1_9'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_generator_1_9'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fifo_generator_1_9'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fifo_generator_1_9'... # create_ip -name nf_10ge_interface -vendor NetFPGA -library NetFPGA -module_name nf_10g_interface_ip # set_property generate_synth_checkpoint false [get_files nf_10g_interface_ip.xci] # reset_target all [get_ips nf_10g_interface_ip] # generate_target all [get_ips nf_10g_interface_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_10g_interface_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_10g_interface_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_10g_interface_ip'... generate_target: Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1993.797 ; gain = 38.785 ; free physical = 8596 ; free virtual = 28524 # source ./create_ip/nf_10ge_interface_shared.tcl ## set sharedLogic "TRUE" ## set tdataWidth 256 ## set convWidth [expr $tdataWidth/8] ## if { $sharedLogic eq "True" || $sharedLogic eq "TRUE" || $sharedLogic eq "true" } { ## set supportLevel 1 ## } else { ## set supportLevel 0 ## } ## create_ip -name axi_10g_ethernet -vendor xilinx.com -library ip -version 3.1 -module_name axi_10g_ethernet_shared ## set_property -dict [list CONFIG.Management_Interface {false}] [get_ips axi_10g_ethernet_shared] WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}' ## set_property -dict [list CONFIG.base_kr {BASE-R}] [get_ips axi_10g_ethernet_shared] WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}' ## set_property -dict [list CONFIG.SupportLevel $supportLevel] [get_ips axi_10g_ethernet_shared] WARNING: [BD 41-1306] The connection to interface pin /xpcs/refclk_p is being overridden by the user. This pin will not be connected as a part of interface connection refclk_diff_port WARNING: [BD 41-1306] The connection to interface pin /xpcs/refclk_n is being overridden by the user. This pin will not be connected as a part of interface connection refclk_diff_port WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}' ## set_property -dict [list CONFIG.autonegotiation {0}] [get_ips axi_10g_ethernet_shared] ## set_property -dict [list CONFIG.fec {0}] [get_ips axi_10g_ethernet_shared] ## set_property -dict [list CONFIG.Statistics_Gathering {0}] [get_ips axi_10g_ethernet_shared] ## set_property generate_synth_checkpoint false [get_files axi_10g_ethernet_shared.xci] ## reset_target all [get_ips axi_10g_ethernet_shared] ## generate_target all [get_ips axi_10g_ethernet_shared] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_10g_ethernet_shared'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_10g_ethernet_shared'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_10g_ethernet_shared'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axi_10g_ethernet_shared'... WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license. WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license. WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license. WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license. Exporting to file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/hw_handoff/axi_10g_ethernet_shared.hwh Generated Block Design Tcl file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/hw_handoff/axi_10g_ethernet_shared_bd.tcl Generated Hardware Definition File /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/synth/axi_10g_ethernet_shared.hwdef generate_target: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 2009.129 ; gain = 15.328 ; free physical = 8540 ; free virtual = 28473 # create_ip -name nf_10ge_interface_shared -vendor NetFPGA -library NetFPGA -module_name nf_10g_interface_shared_ip WARNING: [IP_Flow 19-4832] The IP name 'nf_10g_interface_shared_ip' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues. # set_property generate_synth_checkpoint false [get_files nf_10g_interface_shared_ip.xci] # reset_target all [get_ips nf_10g_interface_shared_ip] # generate_target all [get_ips nf_10g_interface_shared_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_10g_interface_shared_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_10g_interface_shared_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_10g_interface_shared_ip'... generate_target: Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 2046.656 ; gain = 37.527 ; free physical = 8520 ; free virtual = 28473 # create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip # set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip] WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '5.000' to '5.0' has been ignored for IP 'clk_wiz_ip' # set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci] # reset_target all [get_ips clk_wiz_ip] # generate_target all [get_ips clk_wiz_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz_ip'... INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz_ip'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz_ip'... # create_ip -name proc_sys_reset -vendor xilinx.com -library ip -version 5.0 -module_name proc_sys_reset_ip # set_property -dict [list CONFIG.C_EXT_RESET_HIGH {0} CONFIG.C_AUX_RESET_HIGH {0}] [get_ips proc_sys_reset_ip] # set_property -dict [list CONFIG.C_NUM_PERP_RST {1} CONFIG.C_NUM_PERP_ARESETN {1}] [get_ips proc_sys_reset_ip] # set_property generate_synth_checkpoint false [get_files proc_sys_reset_ip.xci] # reset_target all [get_ips proc_sys_reset_ip] # generate_target all [get_ips proc_sys_reset_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'proc_sys_reset_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'proc_sys_reset_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'proc_sys_reset_ip'... INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'proc_sys_reset_ip'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'proc_sys_reset_ip'... # create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip # set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {4096} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip] # set_property generate_synth_checkpoint false [get_files identifier_ip.xci] # reset_target all [get_ips identifier_ip] # generate_target all [get_ips identifier_ip] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'identifier_ip'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'identifier_ip'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'identifier_ip'... INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'identifier_ip'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'identifier_ip'... # read_verilog "./hdl/axi_clocking.v" # read_verilog "./hdl/nf_datapath.v" # read_verilog "./hdl/top.v" # create_run -flow {Vivado Synthesis 2018} synth Run is defaulting to srcset: sources_1 Run is defaulting to constrset: constraints Run is defaulting to part: xc7vx690tffg1761-3 # create_run impl -parent_run synth -flow {Vivado Implementation 2018} Run is defaulting to parent run srcset: sources_1 Run is defaulting to parent run constrset: constraints Run is defaulting to parent run part: xc7vx690tffg1761-3 # set_property steps.phys_opt_design.is_enabled true [get_runs impl_1] # set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE ExploreWithHoldFix [get_runs impl_1] # set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1] # set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.is_enabled true [get_runs impl_1] # set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1] # set_property SEVERITY {Warning} [get_drc_checks UCIO-1] # launch_runs synth INFO: [xilinx.com:ip:axi_intc:4.1-1] /nf_mbsys/mbsys/microblaze_0_axi_intc: The AXI INTC core has been configured to operate with synchronous clocks. INFO: [xilinx.com:ip:axi_intc:4.1-1] /nf_mbsys/mbsys/microblaze_0_axi_intc: The AXI INTC core has been configured to operate with synchronous clocks. Wrote : VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/sim/control_sub.v VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hdl/control_sub_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/axi_iic_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/axi_uartlite_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/clk_wiz_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/mdm_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_axi_intc . INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_xlconcat . INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/rst_clk_wiz_1_100M . INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr . INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10 . INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr . INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10 . INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram . INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_axi_periph/xbar . INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/pcie_reset_inv . INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_dwidth_dma_tx . INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_dwidth_dma_rx . INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_fifo_10g_rx . INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_fifo_10g_tx . INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/nf_riffa_dma_1 . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_clock_converter_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/pcie3_7x_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/xbar . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/s00_couplers/auto_cc . Exporting to file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hw_handoff/control_sub.hwh Generated Block Design Tcl file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hw_handoff/control_sub_bd.tcl Generated Hardware Definition File /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.hwdef [Mon Jul 29 16:36:20 2019] Launched control_sub_m07_data_fifo_0_synth_1, control_sub_ilmb_v10_0_synth_1, control_sub_lmb_bram_0_synth_1, control_sub_axis_fifo_10g_tx_0_synth_1, control_sub_axis_fifo_10g_rx_0_synth_1, control_sub_axis_dwidth_dma_rx_0_synth_1, control_sub_xbar_1_synth_1, control_sub_pcie_reset_inv_0_synth_1, control_sub_axis_dwidth_dma_tx_0_synth_1, control_sub_mdm_1_0_synth_1, control_sub_clk_wiz_1_0_synth_1, control_sub_axi_uartlite_0_0_synth_1, control_sub_axi_iic_0_0_synth_1, control_sub_microblaze_0_0_synth_1, control_sub_microblaze_0_axi_intc_0_synth_1, control_sub_microblaze_0_xlconcat_0_synth_1, control_sub_rst_clk_wiz_1_100M_0_synth_1, control_sub_dlmb_bram_if_cntlr_0_synth_1, control_sub_dlmb_v10_0_synth_1, control_sub_ilmb_bram_if_cntlr_0_synth_1, control_sub_nf_riffa_dma_1_0_synth_1, control_sub_axi_clock_converter_0_0_synth_1, control_sub_pcie3_7x_1_0_synth_1, control_sub_xbar_0_synth_1, control_sub_m08_data_fifo_0_synth_1, control_sub_m06_data_fifo_0_synth_1, control_sub_m05_data_fifo_0_synth_1, control_sub_m04_data_fifo_0_synth_1, control_sub_m03_data_fifo_0_synth_1, control_sub_m02_data_fifo_0_synth_1, control_sub_m01_data_fifo_0_synth_1, control_sub_m00_data_fifo_0_synth_1, control_sub_s00_data_fifo_0_synth_1, control_sub_auto_cc_0_synth_1... Run output will be captured here: control_sub_m07_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m07_data_fifo_0_synth_1/runme.log control_sub_ilmb_v10_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_ilmb_v10_0_synth_1/runme.log control_sub_lmb_bram_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_lmb_bram_0_synth_1/runme.log control_sub_axis_fifo_10g_tx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_fifo_10g_tx_0_synth_1/runme.log control_sub_axis_fifo_10g_rx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_fifo_10g_rx_0_synth_1/runme.log control_sub_axis_dwidth_dma_rx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_dwidth_dma_rx_0_synth_1/runme.log control_sub_xbar_1_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_xbar_1_synth_1/runme.log control_sub_pcie_reset_inv_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_pcie_reset_inv_0_synth_1/runme.log control_sub_axis_dwidth_dma_tx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_dwidth_dma_tx_0_synth_1/runme.log control_sub_mdm_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_mdm_1_0_synth_1/runme.log control_sub_clk_wiz_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_clk_wiz_1_0_synth_1/runme.log control_sub_axi_uartlite_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_uartlite_0_0_synth_1/runme.log control_sub_axi_iic_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_iic_0_0_synth_1/runme.log control_sub_microblaze_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_0_synth_1/runme.log control_sub_microblaze_0_axi_intc_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_axi_intc_0_synth_1/runme.log control_sub_microblaze_0_xlconcat_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_xlconcat_0_synth_1/runme.log control_sub_rst_clk_wiz_1_100M_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_rst_clk_wiz_1_100M_0_synth_1/runme.log control_sub_dlmb_bram_if_cntlr_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_dlmb_bram_if_cntlr_0_synth_1/runme.log control_sub_dlmb_v10_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_dlmb_v10_0_synth_1/runme.log control_sub_ilmb_bram_if_cntlr_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_ilmb_bram_if_cntlr_0_synth_1/runme.log control_sub_nf_riffa_dma_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_nf_riffa_dma_1_0_synth_1/runme.log control_sub_axi_clock_converter_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_clock_converter_0_0_synth_1/runme.log control_sub_pcie3_7x_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_pcie3_7x_1_0_synth_1/runme.log control_sub_xbar_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_xbar_0_synth_1/runme.log control_sub_m08_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m08_data_fifo_0_synth_1/runme.log control_sub_m06_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m06_data_fifo_0_synth_1/runme.log control_sub_m05_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m05_data_fifo_0_synth_1/runme.log control_sub_m04_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m04_data_fifo_0_synth_1/runme.log control_sub_m03_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m03_data_fifo_0_synth_1/runme.log control_sub_m02_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log control_sub_m01_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m01_data_fifo_0_synth_1/runme.log control_sub_m00_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m00_data_fifo_0_synth_1/runme.log control_sub_s00_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_s00_data_fifo_0_synth_1/runme.log control_sub_auto_cc_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_auto_cc_0_synth_1/runme.log [Mon Jul 29 16:36:20 2019] Launched synth... Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/runme.log launch_runs: Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2879.363 ; gain = 832.703 ; free physical = 8284 ; free virtual = 28327 # wait_on_run synth [Mon Jul 29 16:36:20 2019] Waiting for synth to finish... *** Running vivado with args -log top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source top.tcl -notrace Command: synth_design -top top -part xc7vx690tffg1761-3 Starting synth_design WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design. /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/identifier_ip.xci Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx690t' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29782 WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_single [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_gray [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_handshake [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:469] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_pulse [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:715] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_array_single [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_sync_rst [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1055] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_async_rst [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1171] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_base [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_rst [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_counter_updn [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_reg_vec [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_reg_bit [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1755] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_reg_pipe_bit [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1774] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_sync [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_async [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_axis [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2076] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_base [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] WARNING: [Synth 8-2490] overwriting previous definition of module asym_bwe_bb [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6541] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_dpdistram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6600] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_dprom [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6734] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_sdpram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6888] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_spram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7043] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_sprom [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7189] WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_tdpram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325] WARNING: [Synth 8-2507] parameter declaration becomes local in small_fifo with formal parameter declaration list [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:67] WARNING: [Synth 8-2507] parameter declaration becomes local in sss_small_fifo with formal parameter declaration list [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_small_fifo.v:69] WARNING: [Synth 8-2306] macro REG_ID_DEFAULT redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues_cpu_regs_defines.v:44] WARNING: [Synth 8-2306] macro REG_ID_DEFAULT redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs_defines.v:44] WARNING: [Synth 8-2306] macro REG_PKTIN_ADDR redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs_defines.v:75] WARNING: [Synth 8-2306] macro REG_PKTOUT_ADDR redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs_defines.v:80] --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:26 . Memory (MB): peak = 1491.453 ; gain = 160.371 ; free physical = 7673 ; free virtual = 27838 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'top' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:43] Parameter C_DATA_WIDTH bound to: 256 - type: integer Parameter C_TUSER_WIDTH bound to: 128 - type: integer Parameter IF_SFP0 bound to: 8'b00000001 Parameter IF_SFP1 bound to: 8'b00000100 Parameter IF_SFP2 bound to: 8'b00010000 Parameter IF_SFP3 bound to: 8'b01000000 INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:152] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:153] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:154] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:155] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:156] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:157] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:166] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:167] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:168] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:169] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:170] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:171] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:180] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:181] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:182] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:183] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:184] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:185] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:194] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:195] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:196] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:197] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:198] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:199] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:259] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:260] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:261] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:262] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:263] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:264] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:265] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:266] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:267] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:268] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:269] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:270] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:271] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:272] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:273] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:274] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:275] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:276] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:277] INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:431] INFO: [Synth 8-6157] synthesizing module 'OBUF' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:27275] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-6155] done synthesizing module 'OBUF' (1#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:27275] INFO: [Synth 8-6157] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19473] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-6155] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19473] INFO: [Synth 8-6157] synthesizing module 'IBUFDS_GTE2' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19625] Parameter CLKCM_CFG bound to: TRUE - type: string Parameter CLKRCV_TRST bound to: TRUE - type: string Parameter CLKSWING_CFG bound to: 2'b11 INFO: [Synth 8-6155] done synthesizing module 'IBUFDS_GTE2' (3#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19625] INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:22660] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (4#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:22660] INFO: [Synth 8-6157] synthesizing module 'axi_clocking' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/axi_clocking.v:44] INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: FALSE - type: string Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (5#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] INFO: [Synth 8-6157] synthesizing module 'clk_wiz_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.v:70] INFO: [Synth 8-6157] synthesizing module 'clk_wiz_ip_clk_wiz' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:68] INFO: [Synth 8-5534] Detected attribute (* KEEP = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:126] INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:126] INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: float Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float Parameter CLKOUT0_DIVIDE_F bound to: 5.000000 - type: float Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT4_CASCADE bound to: FALSE - type: string Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string Parameter COMPENSATION bound to: ZHOLD - type: string Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 Parameter IS_PSEN_INVERTED bound to: 1'b0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.010000 - type: float Parameter REF_JITTER2 bound to: 0.010000 - type: float Parameter SS_EN bound to: FALSE - type: string Parameter SS_MODE bound to: CENTER_HIGH - type: string Parameter SS_MOD_PERIOD bound to: 10000 - type: integer Parameter STARTUP_WAIT bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (6#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] INFO: [Synth 8-6157] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] INFO: [Synth 8-6155] done synthesizing module 'BUFG' (7#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] INFO: [Synth 8-6157] synthesizing module 'BUFGCE' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:619] Parameter CE_TYPE bound to: SYNC - type: string Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_I_INVERTED bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'BUFGCE' (8#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:619] INFO: [Synth 8-6157] synthesizing module 'BUFH' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:808] INFO: [Synth 8-6155] done synthesizing module 'BUFH' (9#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:808] INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_ip_clk_wiz' (10#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:68] INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_ip' (11#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.v:70] INFO: [Synth 8-6155] done synthesizing module 'axi_clocking' (12#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/axi_clocking.v:44] INFO: [Synth 8-638] synthesizing module 'proc_sys_reset_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/synth/proc_sys_reset_ip.vhd:74] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer Parameter C_EXT_RESET_HIGH bound to: 1'b0 Parameter C_AUX_RESET_HIGH bound to: 1'b0 Parameter C_NUM_BUS_RST bound to: 1 - type: integer Parameter C_NUM_PERP_RST bound to: 1 - type: integer Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/synth/proc_sys_reset_ip.vhd:129] INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer Parameter C_EXT_RESET_HIGH bound to: 1'b0 Parameter C_AUX_RESET_HIGH bound to: 1'b0 Parameter C_NUM_BUS_RST bound to: 1 - type: integer Parameter C_NUM_PERP_RST bound to: 1 - type: integer Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer Parameter INIT bound to: 1'b1 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1392] Parameter INIT bound to: 1'b1 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1408] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1434] Parameter INIT bound to: 1'b1 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1457] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1481] INFO: [Synth 8-638] synthesizing module 'lpf' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816] Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer Parameter C_EXT_RESET_HIGH bound to: 1'b0 Parameter C_AUX_RESET_HIGH bound to: 1'b0 INFO: [Synth 8-3491] module 'SRL16' declared at '/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:50695' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:868] INFO: [Synth 8-6157] synthesizing module 'SRL16' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:50695] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-6155] done synthesizing module 'SRL16' (13#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:50695] INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 0 - type: integer Parameter C_VECTOR_WIDTH bound to: 2 - type: integer Parameter C_MTBF_STAGES bound to: 4 - type: integer Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:514] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:545] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:554] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:564] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:574] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:584] INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (14#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-256] done synthesizing module 'lpf' (15#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816] INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301] INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125] Parameter C_SIZE bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (16#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125] INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (17#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301] INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (18#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323] INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset_ip' (19#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/synth/proc_sys_reset_ip.vhd:74] INFO: [Synth 8-6157] synthesizing module 'nf_datapath' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:44] Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer Parameter C_BASEADDR bound to: 0 - type: integer Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter NUM_QUEUES bound to: 5 - type: integer Parameter DIGEST_WIDTH bound to: 80 - type: integer Parameter C_AXIS_TUSER_DIGEST_WIDTH bound to: 304 - type: integer Parameter Q_SIZE_WIDTH bound to: 16 - type: integer INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:194] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:195] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:196] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:197] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:198] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:199] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:201] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:202] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:203] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:204] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:205] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:206] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:209] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:210] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:211] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:212] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:213] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:321] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:322] INFO: [Synth 8-6157] synthesizing module 'input_arbiter_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/synth/input_arbiter_ip.v:57] INFO: [Synth 8-6157] synthesizing module 'input_arbiter' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter.v:55] Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter NUM_QUEUES bound to: 5 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer Parameter C_BASEADDR bound to: 0 - type: integer Parameter NUM_QUEUES_WIDTH bound to: 3 - type: integer Parameter NUM_STATES bound to: 1 - type: integer Parameter IDLE bound to: 0 - type: integer Parameter WR_PKT bound to: 1 - type: integer Parameter MAX_PKT_SIZE bound to: 2000 - type: integer Parameter IN_FIFO_DEPTH_BIT bound to: 6 - type: integer INFO: [Synth 8-6157] synthesizing module 'fallthrough_small_fifo' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/fallthrough_small_fifo.v:46] Parameter WIDTH bound to: 417 - type: integer Parameter MAX_DEPTH_BITS bound to: 6 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer INFO: [Synth 8-6157] synthesizing module 'small_fifo' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:44] Parameter WIDTH bound to: 417 - type: integer Parameter MAX_DEPTH_BITS bound to: 6 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer Parameter MAX_DEPTH bound to: 64 - type: integer INFO: [Synth 8-6155] done synthesizing module 'small_fifo' (20#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:44] INFO: [Synth 8-6155] done synthesizing module 'fallthrough_small_fifo' (21#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/fallthrough_small_fifo.v:46] INFO: [Synth 8-6157] synthesizing module 'input_arbiter_cpu_regs' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter_cpu_regs.v:42] Parameter C_BASE_ADDRESS bound to: 0 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter_cpu_regs.v:305] INFO: [Synth 8-6155] done synthesizing module 'input_arbiter_cpu_regs' (22#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter_cpu_regs.v:42] INFO: [Synth 8-6155] done synthesizing module 'input_arbiter' (23#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter.v:55] INFO: [Synth 8-6155] done synthesizing module 'input_arbiter_ip' (24#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/synth/input_arbiter_ip.v:57] INFO: [Synth 8-6157] synthesizing module 'nf_sume_sdnet_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/synth/nf_sume_sdnet_ip.v:57] INFO: [Synth 8-6157] synthesizing module 'nf_sume_sdnet' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:44] Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_M_AXIS_TUSER_WIDTH bound to: 304 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer Parameter SDNET_ADDR_WIDTH bound to: 12 - type: integer Parameter DIGEST_WIDTH bound to: 256 - type: integer INFO: [Synth 8-6157] synthesizing module 'sume_to_sdnet' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/sume_to_sdnet.v:41] Parameter FIRST bound to: 0 - type: integer Parameter WAIT bound to: 1 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/sume_to_sdnet.v:72] INFO: [Synth 8-6155] done synthesizing module 'sume_to_sdnet' (25#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/sume_to_sdnet.v:41] INFO: [Synth 8-6157] synthesizing module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:36] INFO: [Synth 8-6157] synthesizing module 'S_RESETTER_line' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v:40] INFO: [Synth 8-6155] done synthesizing module 'S_RESETTER_line' (26#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v:40] INFO: [Synth 8-6157] synthesizing module 'S_RESETTER_lookup' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v:40] INFO: [Synth 8-6155] done synthesizing module 'S_RESETTER_lookup' (27#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v:40] INFO: [Synth 8-6157] synthesizing module 'S_RESETTER_control' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v:40] INFO: [Synth 8-6155] done synthesizing module 'S_RESETTER_control' (28#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v:40] INFO: [Synth 8-6157] synthesizing module 'TopParser_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v:282] INFO: [Synth 8-6155] done synthesizing module 'TopParser_t' (318#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v:282] INFO: [Synth 8-6157] synthesizing module 'TopPipe_lvl_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v:185] INFO: [Synth 8-6155] done synthesizing module 'TopPipe_lvl_t' (325#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v:185] INFO: [Synth 8-6157] synthesizing module 'realmain_dummy_table_for_netpfga_0_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_dummy_table_for_netpfga_0_t.HDL/realmain_dummy_table_for_netpfga_0_t.v:36] Parameter K bound to: 48 - type: integer Parameter V bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_memory_tdpram' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325] INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:467] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (327#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_tdpram' (328#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg Warning: Trying to implement RAM in registers. Block RAM or DRAM implementation is not possible for one or more of the following reasons : 1: Invalid write to RAM. 2: Unable to determine number of words or word size in RAM. 3: No valid read/write found for RAM. RAM dissolved into registers WARNING: [Synth 8-4767] Trying to implement RAM 'CamPtrBck_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons. Reason is one or more of the following : 1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process. 2: Unable to determine number of words or word size in RAM. 3: No valid read/write found for RAM. RAM "CamPtrBck_reg" dissolved into registers WARNING: [Synth 8-4767] Trying to implement RAM 'CamPtrFwd_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons. Reason is one or more of the following : 1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process. 2: Unable to determine number of words or word size in RAM. 3: No valid read/write found for RAM. RAM "CamPtrFwd_reg" dissolved into registers INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'realmain_dummy_table_for_netpfga_0_t' (341#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_dummy_table_for_netpfga_0_t.HDL/realmain_dummy_table_for_netpfga_0_t.v:36] INFO: [Synth 8-6157] synthesizing module 'TopPipe_lvl_0_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v:186] INFO: [Synth 8-6155] done synthesizing module 'TopPipe_lvl_0_t' (581#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v:186] INFO: [Synth 8-6157] synthesizing module 'TopDeparser_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v:169] INFO: [Synth 8-6155] done synthesizing module 'TopDeparser_t' (1041#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v:169] INFO: [Synth 8-6157] synthesizing module 'S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request.v:36] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: 1651663213 - type: integer Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 48 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 128 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: std - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 48 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 3 - type: integer Parameter DOUT_RESET_VALUE bound to: 48 - type: integer Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 48 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 128 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 48 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 3 - type: integer Parameter DOUT_RESET_VALUE bound to: 48 - type: integer Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 12288 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 128 - type: integer Parameter PE_THRESH_ADJ bound to: 3 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 12288 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 48 - type: integer Parameter READ_DATA_WIDTH_A bound to: 48 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 48 - type: integer Parameter ADDR_WIDTH_A bound to: 8 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 48 - type: integer Parameter READ_DATA_WIDTH_B bound to: 48 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 48 - type: integer Parameter ADDR_WIDTH_B bound to: 8 - type: integer Parameter READ_RESET_VALUE_B bound to: 48 - type: integer Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 48 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 48 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 48 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 48 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 48 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 48 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 48 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized0' (1041#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 2 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:358] WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (1042#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733] Parameter REG_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec' (1043#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 2 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 9 - type: integer WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized0' (1043#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733] Parameter REG_WIDTH bound to: 9 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized0' (1043#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1638] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1663] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1055] Parameter DEST_SYNC_FF bound to: 2 - type: integer Parameter INIT bound to: 32'sb00000000000000000000000000000000 Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter DEF_VAL bound to: 1'b0 INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1107] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (1044#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1055] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst' (1045#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_bit' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1755] Parameter RST_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_bit' (1046#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1755] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] Parameter COUNTER_WIDTH bound to: 9 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn' (1047#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter RESET_VALUE bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized0' (1047#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter RESET_VALUE bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized1' (1047#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (1048#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async' (1049#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request' (1050#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request.v:36] INFO: [Synth 8-6157] synthesizing module 'S_PROTOCOL_ADAPTER_INGRESS' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:36] Parameter IDLE bound to: 1 - type: integer Parameter RX_SOF bound to: 2 - type: integer Parameter RX_SOF_EOF bound to: 3 - type: integer Parameter RX_PKT bound to: 4 - type: integer INFO: [Synth 8-4471] merging register 'tuple_out_control_VALID_reg' into 'packet_out_SOF_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:182] WARNING: [Synth 8-6014] Unused sequential element tuple_out_control_VALID_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:182] INFO: [Synth 8-6155] done synthesizing module 'S_PROTOCOL_ADAPTER_INGRESS' (1051#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:36] INFO: [Synth 8-6157] synthesizing module 'S_PROTOCOL_ADAPTER_EGRESS' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v:36] INFO: [Synth 8-6155] done synthesizing module 'S_PROTOCOL_ADAPTER_EGRESS' (1052#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v:36] INFO: [Synth 8-6157] synthesizing module 'S_SYNCER_for_TopParser' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:40] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 129 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 266 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 1 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126] INFO: [Common 17-14] Message 'Synth 8-6104' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter COMMON_CLOCK bound to: 1 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 129 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 266 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 136192 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 129 - type: integer Parameter PE_THRESH_ADJ bound to: 129 - type: integer Parameter PF_THRESH_MIN bound to: 3 - type: integer Parameter PF_THRESH_MAX bound to: 509 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 509 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 136192 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 266 - type: integer Parameter READ_DATA_WIDTH_A bound to: 266 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 266 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 266 - type: integer Parameter READ_DATA_WIDTH_B bound to: 266 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 266 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 266 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 266 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 266 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 266 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 266 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 266 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 266 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized1' (1052#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478] Parameter COMMON_CLOCK bound to: 1 - type: integer Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst__parameterized0' (1052#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] Parameter COUNTER_WIDTH bound to: 10 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (1052#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] Parameter COUNTER_WIDTH bound to: 9 - type: integer Parameter RESET_VALUE bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized3' (1052#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] Parameter COUNTER_WIDTH bound to: 9 - type: integer Parameter RESET_VALUE bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized4' (1052#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Common 17-14] Message 'Synth 8-5772' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized0' (1052#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync' (1053#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800] Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 129 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: FWFT - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter P_COMMON_CLOCK bound to: 1 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 1 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 1 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 129 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 1 - type: integer Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 512 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 127 - type: integer Parameter PE_THRESH_ADJ bound to: 127 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 507 - type: integer Parameter PE_THRESH_MIN bound to: 5 - type: integer Parameter PE_THRESH_MAX bound to: 507 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 2 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 512 - type: integer Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer Parameter CLOCKING_MODE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 1 - type: integer Parameter READ_DATA_WIDTH_A bound to: 1 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 1 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 1 - type: integer Parameter READ_DATA_WIDTH_B bound to: 1 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 1 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 2 - type: integer Parameter WRITE_MODE_B bound to: 1 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 1 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 1 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 1 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 1 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 1 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: yes - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 5 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 1 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] WARNING: [Synth 8-6014] Unused sequential element gen_rd_b.gen_doutb_pipe.enb_pipe_reg[0] was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:2588] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized2' (1053#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] Parameter COUNTER_WIDTH bound to: 2 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized5' (1053#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707] INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized1' (1053#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized0' (1053#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 66 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 128 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 66 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 128 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 32768 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 66 - type: integer Parameter PE_THRESH_ADJ bound to: 66 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 32768 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 128 - type: integer Parameter READ_DATA_WIDTH_A bound to: 128 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 128 - type: integer Parameter ADDR_WIDTH_A bound to: 8 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 128 - type: integer Parameter READ_DATA_WIDTH_B bound to: 128 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 128 - type: integer Parameter ADDR_WIDTH_B bound to: 8 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 128 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 128 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 128 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 128 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 128 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 128 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 128 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized3' (1053#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized2' (1053#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized0' (1053#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 22 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 65 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 22 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 22 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 65 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 22 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 1 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 5632 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 65 - type: integer Parameter PE_THRESH_ADJ bound to: 65 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 5632 - type: integer Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 22 - type: integer Parameter READ_DATA_WIDTH_A bound to: 22 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 22 - type: integer Parameter ADDR_WIDTH_A bound to: 8 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 22 - type: integer Parameter READ_DATA_WIDTH_B bound to: 22 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 22 - type: integer Parameter ADDR_WIDTH_B bound to: 8 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 1 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 22 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 22 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 22 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 22 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 22 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 22 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: yes - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 22 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized4' (1053#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized3' (1053#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized1' (1053#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] WARNING: [Synth 8-6014] Unused sequential element igatv5k4uchzxfyhakx7xoh81j_712_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:353] WARNING: [Synth 8-6014] Unused sequential element geqmuor4j0p9855hofziq5j55bzerz6_861_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:341] WARNING: [Synth 8-6014] Unused sequential element ix7fiyk7gaud6cnffws5lsb_671_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:355] WARNING: [Synth 8-6014] Unused sequential element a3wzy0f8qhp10av5e1s_747_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:292] INFO: [Synth 8-6155] done synthesizing module 'S_SYNCER_for_TopParser' (1054#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:40] INFO: [Synth 8-6157] synthesizing module 'S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:40] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 135 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 266 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 1 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 1 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 135 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 266 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 136192 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 135 - type: integer Parameter PE_THRESH_ADJ bound to: 135 - type: integer Parameter PF_THRESH_MIN bound to: 3 - type: integer Parameter PF_THRESH_MAX bound to: 509 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 509 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized4' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized1' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800] Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 135 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: FWFT - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter P_COMMON_CLOCK bound to: 1 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 1 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 1 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 135 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 1 - type: integer Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 512 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 133 - type: integer Parameter PE_THRESH_ADJ bound to: 133 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 507 - type: integer Parameter PE_THRESH_MIN bound to: 5 - type: integer Parameter PE_THRESH_MAX bound to: 507 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 2 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218] INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized5' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized2' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 65 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1403 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized6' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 65 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1403 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 359168 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 65 - type: integer Parameter PE_THRESH_ADJ bound to: 65 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 359168 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 1403 - type: integer Parameter READ_DATA_WIDTH_A bound to: 1403 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 1403 - type: integer Parameter ADDR_WIDTH_A bound to: 8 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 1403 - type: integer Parameter READ_DATA_WIDTH_B bound to: 1403 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 1403 - type: integer Parameter ADDR_WIDTH_B bound to: 8 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 1403 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 1403 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 1403 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 1403 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 1403 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 1403 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 1403 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized5' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized6' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized2' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 65 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 160 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized7' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 65 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 160 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 40960 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 65 - type: integer Parameter PE_THRESH_ADJ bound to: 65 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized6' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 40960 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 160 - type: integer Parameter READ_DATA_WIDTH_A bound to: 160 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 160 - type: integer Parameter ADDR_WIDTH_A bound to: 8 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 160 - type: integer Parameter READ_DATA_WIDTH_B bound to: 160 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 160 - type: integer Parameter ADDR_WIDTH_B bound to: 8 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 160 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 160 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 160 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 160 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 160 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 160 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 160 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized6' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized7' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized3' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 65 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 256 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized8' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 65 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 256 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 65536 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 65 - type: integer Parameter PE_THRESH_ADJ bound to: 65 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized7' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 65536 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 256 - type: integer Parameter READ_DATA_WIDTH_A bound to: 256 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 256 - type: integer Parameter ADDR_WIDTH_A bound to: 8 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 256 - type: integer Parameter READ_DATA_WIDTH_B bound to: 256 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 256 - type: integer Parameter ADDR_WIDTH_B bound to: 8 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 256 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 256 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 256 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 256 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 256 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 256 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 256 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized7' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized8' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized4' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 65 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 128 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized9' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 65 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 128 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 32768 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 65 - type: integer Parameter PE_THRESH_ADJ bound to: 65 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized9' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized5' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized6' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 65 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized10' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 65 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 1 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 8192 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 65 - type: integer Parameter PE_THRESH_ADJ bound to: 65 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized8' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 8192 - type: integer Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 8 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 8 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 1 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: yes - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized8' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized10' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized6' (1054#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] WARNING: [Synth 8-6014] Unused sequential element oy52as4ywzcv58mwrwsvx34tmim4_754_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:557] WARNING: [Synth 8-6014] Unused sequential element su32wvutz7f44ich6_152_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:545] WARNING: [Synth 8-6014] Unused sequential element tfyefshg7578smjdc2_842_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:559] WARNING: [Synth 8-6014] Unused sequential element k5i0hklbecrb8yfrxnw07w3i5dh8cid8_772_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:452] INFO: [Synth 8-6155] done synthesizing module 'S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser' (1055#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:40] INFO: [Synth 8-6157] synthesizing module 'S_SYNCER_for_S_SYNCER_for_TopDeparser' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:40] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 167 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 266 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 1 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized11' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 1 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 167 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 266 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 136192 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 167 - type: integer Parameter PE_THRESH_ADJ bound to: 167 - type: integer Parameter PF_THRESH_MIN bound to: 3 - type: integer Parameter PF_THRESH_MAX bound to: 509 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 509 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized11' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized3' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800] Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 167 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: FWFT - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter P_COMMON_CLOCK bound to: 1 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 1 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized12' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 1 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 167 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 1 - type: integer Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 512 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 165 - type: integer Parameter PE_THRESH_ADJ bound to: 165 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 507 - type: integer Parameter PE_THRESH_MIN bound to: 5 - type: integer Parameter PE_THRESH_MAX bound to: 507 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 2 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218] INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized12' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized4' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized7' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 769 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 81 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 769 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized13' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 769 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 81 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 769 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 196864 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 81 - type: integer Parameter PE_THRESH_ADJ bound to: 81 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized9' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 196864 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 769 - type: integer Parameter READ_DATA_WIDTH_A bound to: 769 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 769 - type: integer Parameter ADDR_WIDTH_A bound to: 8 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 769 - type: integer Parameter READ_DATA_WIDTH_B bound to: 769 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 769 - type: integer Parameter ADDR_WIDTH_B bound to: 8 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 769 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 769 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 769 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 769 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 769 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 769 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 769 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized9' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized13' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized7' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized8' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 81 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 256 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized14' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 81 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 256 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 65536 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 81 - type: integer Parameter PE_THRESH_ADJ bound to: 81 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized14' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized8' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized9' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 16 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 81 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 16 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized15' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 16 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 81 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 16 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 1 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 4096 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 81 - type: integer Parameter PE_THRESH_ADJ bound to: 81 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized10' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 4096 - type: integer Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 16 - type: integer Parameter READ_DATA_WIDTH_A bound to: 16 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 16 - type: integer Parameter ADDR_WIDTH_A bound to: 8 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 16 - type: integer Parameter READ_DATA_WIDTH_B bound to: 16 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 16 - type: integer Parameter ADDR_WIDTH_B bound to: 8 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 1 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 16 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 16 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 16 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 16 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 16 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 16 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: yes - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 16 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized10' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized15' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized9' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 81 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1403 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 81 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1403 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 359168 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 81 - type: integer Parameter PE_THRESH_ADJ bound to: 81 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized16' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized10' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 81 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 128 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 81 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 128 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 32768 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 81 - type: integer Parameter PE_THRESH_ADJ bound to: 81 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized17' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized11' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 81 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 160 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 81 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 160 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 40960 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 81 - type: integer Parameter PE_THRESH_ADJ bound to: 81 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized18' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized12' (1055#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937] INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer Parameter WRITE_DATA_WIDTH bound to: 3 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer Parameter PROG_FULL_THRESH bound to: 33 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 3 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer Parameter PROG_EMPTY_THRESH bound to: 33 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer Parameter WRITE_DATA_WIDTH bound to: 3 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer Parameter PROG_FULL_THRESH bound to: 33 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 3 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer Parameter PROG_EMPTY_THRESH bound to: 33 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 1 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 128 - type: integer Parameter FIFO_SIZE bound to: 384 - type: integer Parameter WR_PNTR_WIDTH bound to: 7 - type: integer Parameter RD_PNTR_WIDTH bound to: 7 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 33 - type: integer Parameter PE_THRESH_ADJ bound to: 33 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 125 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 125 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 8 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 8 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 384 - type: integer Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 3 - type: integer Parameter READ_DATA_WIDTH_A bound to: 3 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 3 - type: integer Parameter ADDR_WIDTH_A bound to: 7 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 3 - type: integer Parameter READ_DATA_WIDTH_B bound to: 3 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 3 - type: integer Parameter ADDR_WIDTH_B bound to: 7 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 1 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 3 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 3 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 3 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 3 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 128 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 3 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 3 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 7 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 7 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 7 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 7 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: yes - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 5 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 3 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] Parameter DEST_SYNC_FF bound to: 2 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 7 - type: integer WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417] Parameter REG_WIDTH bound to: 7 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 7 - type: integer Parameter RESET_VALUE bound to: 1 - type: integer Parameter COUNTER_WIDTH bound to: 7 - type: integer Parameter RESET_VALUE bound to: 2 - type: integer Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 22 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 84 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 22 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 22 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 84 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 22 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 1 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 5632 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 84 - type: integer Parameter PE_THRESH_ADJ bound to: 84 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 84 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 84 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 1 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 8192 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 84 - type: integer Parameter PE_THRESH_ADJ bound to: 84 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 WARNING: [Synth 8-6014] Unused sequential element ypmoyqgr5nksql0pdkgrsttsgg1q14k_839_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:710] WARNING: [Synth 8-6014] Unused sequential element zhg3f63euiqe4kk8ajgoqcd56nd_228_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:698] WARNING: [Synth 8-6014] Unused sequential element g19hp2bkqthut2b6i4hbp_698_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:712] WARNING: [Synth 8-6014] Unused sequential element ptwd0hhi5sx06tfyqia12qr477_824_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:572] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter FIFO_WRITE_DEPTH bound to: 1024 - type: integer Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 441 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 266 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 441 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 1 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 1 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 1024 - type: integer Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 441 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 266 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 441 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 1024 - type: integer Parameter FIFO_SIZE bound to: 272384 - type: integer Parameter WR_PNTR_WIDTH bound to: 10 - type: integer Parameter RD_PNTR_WIDTH bound to: 10 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 441 - type: integer Parameter PE_THRESH_ADJ bound to: 441 - type: integer Parameter PF_THRESH_MIN bound to: 3 - type: integer Parameter PF_THRESH_MAX bound to: 1021 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 1021 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 11 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 11 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 272384 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 266 - type: integer Parameter READ_DATA_WIDTH_A bound to: 266 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 266 - type: integer Parameter ADDR_WIDTH_A bound to: 10 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 266 - type: integer Parameter READ_DATA_WIDTH_B bound to: 266 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 266 - type: integer Parameter ADDR_WIDTH_B bound to: 10 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 266 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 266 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 266 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 266 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 1024 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 266 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 266 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 10 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 10 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 10 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 10 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 266 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] Parameter COUNTER_WIDTH bound to: 11 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 10 - type: integer Parameter RESET_VALUE bound to: 1 - type: integer Parameter COUNTER_WIDTH bound to: 10 - type: integer Parameter RESET_VALUE bound to: 2 - type: integer Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter FIFO_WRITE_DEPTH bound to: 1024 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 441 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: FWFT - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 441 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter P_COMMON_CLOCK bound to: 1 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 1 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 1 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 1024 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 441 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 441 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 1 - type: integer Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 1024 - type: integer Parameter FIFO_SIZE bound to: 1024 - type: integer Parameter WR_PNTR_WIDTH bound to: 10 - type: integer Parameter RD_PNTR_WIDTH bound to: 10 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 439 - type: integer Parameter PE_THRESH_ADJ bound to: 439 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 1019 - type: integer Parameter PE_THRESH_MIN bound to: 5 - type: integer Parameter PE_THRESH_MAX bound to: 1019 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 11 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 11 - type: integer Parameter RD_LATENCY bound to: 2 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 1024 - type: integer Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer Parameter CLOCKING_MODE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 1 - type: integer Parameter READ_DATA_WIDTH_A bound to: 1 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 1 - type: integer Parameter ADDR_WIDTH_A bound to: 10 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 1 - type: integer Parameter READ_DATA_WIDTH_B bound to: 1 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 1 - type: integer Parameter ADDR_WIDTH_B bound to: 10 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 2 - type: integer Parameter WRITE_MODE_B bound to: 1 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 1 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 1 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 1 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 1 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 1024 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 1 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 10 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 10 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 10 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 10 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: yes - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 5 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 1 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] WARNING: [Synth 8-6014] Unused sequential element gen_rd_b.gen_doutb_pipe.enb_pipe_reg[0] was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:2588] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218] INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 162 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1403 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 162 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 162 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 1403 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 162 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 718336 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 162 - type: integer Parameter PE_THRESH_ADJ bound to: 162 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 509 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 509 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 718336 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 1403 - type: integer Parameter READ_DATA_WIDTH_A bound to: 1403 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 1403 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 1403 - type: integer Parameter READ_DATA_WIDTH_B bound to: 1403 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 1403 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 1403 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 1403 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 1403 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 1403 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 1403 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 1403 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 1403 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] Parameter DEST_SYNC_FF bound to: 2 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 10 - type: integer WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417] Parameter REG_WIDTH bound to: 10 - type: integer Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 162 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 160 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 162 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 162 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 160 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 162 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 81920 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 162 - type: integer Parameter PE_THRESH_ADJ bound to: 162 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 509 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 509 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 81920 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 160 - type: integer Parameter READ_DATA_WIDTH_A bound to: 160 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 160 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 160 - type: integer Parameter READ_DATA_WIDTH_B bound to: 160 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 160 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 160 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 160 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 160 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 160 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 160 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 160 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 160 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 162 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 256 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 162 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 162 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 256 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 162 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 131072 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 162 - type: integer Parameter PE_THRESH_ADJ bound to: 162 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 509 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 509 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 131072 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 256 - type: integer Parameter READ_DATA_WIDTH_A bound to: 256 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 256 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 256 - type: integer Parameter READ_DATA_WIDTH_B bound to: 256 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 256 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 256 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 256 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 256 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 256 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 256 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 256 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 256 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 162 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 128 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 162 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 162 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 128 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 162 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 65536 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 162 - type: integer Parameter PE_THRESH_ADJ bound to: 162 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 509 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 509 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 65536 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 128 - type: integer Parameter READ_DATA_WIDTH_A bound to: 128 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 128 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 128 - type: integer Parameter READ_DATA_WIDTH_B bound to: 128 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 128 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 128 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 128 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 128 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 128 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 128 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 128 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 128 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 22 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 221 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 22 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 221 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 22 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 221 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 22 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 221 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 11264 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 221 - type: integer Parameter PE_THRESH_ADJ bound to: 221 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 509 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 509 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 11264 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 22 - type: integer Parameter READ_DATA_WIDTH_A bound to: 22 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 22 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 22 - type: integer Parameter READ_DATA_WIDTH_B bound to: 22 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 22 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 22 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 22 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 22 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 22 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 22 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 22 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 22 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 221 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 221 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 221 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 221 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 16384 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 221 - type: integer Parameter PE_THRESH_ADJ bound to: 221 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 509 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 509 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 16384 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] WARNING: [Synth 8-6014] Unused sequential element pxwiifgw0pduwut2wnssia8db_170_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:557] WARNING: [Synth 8-6014] Unused sequential element ccilp38xvekra9wikkza0tevnk_656_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:545] WARNING: [Synth 8-6014] Unused sequential element s9y0opvu2lc45veyw15078pacuu_511_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:559] WARNING: [Synth 8-6014] Unused sequential element zt9uv6rpid383r5g21_370_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:452] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 290 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 135 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 290 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 1 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 1 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 290 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 135 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 290 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 148480 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 135 - type: integer Parameter PE_THRESH_ADJ bound to: 135 - type: integer Parameter PF_THRESH_MIN bound to: 3 - type: integer Parameter PF_THRESH_MAX bound to: 509 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 509 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 148480 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 290 - type: integer Parameter READ_DATA_WIDTH_A bound to: 290 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 290 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter WRITE_DATA_WIDTH_B bound to: 290 - type: integer Parameter READ_DATA_WIDTH_B bound to: 290 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 290 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 290 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 290 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 290 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 290 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 290 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 290 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 290 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469] Parameter FIFO_MEMORY_TYPE bound to: bram - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 66 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: STD - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 256 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 66 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 256 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 65536 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 66 - type: integer Parameter PE_THRESH_ADJ bound to: 66 - type: integer Parameter PF_THRESH_MIN bound to: 5 - type: integer Parameter PF_THRESH_MAX bound to: 253 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 253 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 WARNING: [Synth 8-6014] Unused sequential element h0lxl77j54mft3avoy3_317_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:302] WARNING: [Synth 8-6014] Unused sequential element myg07gi9pxmroc4k_583_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:300] WARNING: [Synth 8-6014] Unused sequential element sa68lmdi59nyrblqnq4iubz4e5aocsoj_267_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:337] WARNING: [Synth 8-689] width (12) of port connection 'control_S_AXI_AWADDR' does not match port width (8) of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:189] WARNING: [Synth 8-689] width (12) of port connection 'control_S_AXI_ARADDR' does not match port width (8) of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:199] Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 304 - type: integer Parameter NUM_QUEUES bound to: 5 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer Parameter C_BASEADDR bound to: 0 - type: integer Parameter QUEUE_DEPTH_BITS bound to: 16 - type: integer Parameter NUM_QUEUES_WIDTH bound to: 3 - type: integer Parameter DMA_QUEUE bound to: 4 - type: integer Parameter BUFFER_SIZE bound to: 131072 - type: integer Parameter BUFFER_SIZE_WIDTH bound to: 12 - type: integer Parameter MAX_PACKET_SIZE bound to: 1600 - type: integer Parameter BUFFER_THRESHOLD bound to: 4046 - type: integer Parameter NUM_STATES bound to: 3 - type: integer Parameter IDLE bound to: 0 - type: integer Parameter WR_PKT bound to: 1 - type: integer Parameter DROP bound to: 2 - type: integer Parameter NUM_METADATA_STATES bound to: 2 - type: integer Parameter WAIT_HEADER bound to: 0 - type: integer Parameter WAIT_EOP bound to: 1 - type: integer Parameter MIN_PACKET_SIZE bound to: 64 - type: integer Parameter META_BUFFER_WIDTH bound to: 11 - type: integer Parameter DIGEST_WIDTH bound to: 256 - type: integer Parameter DST_POS bound to: 24 - type: integer Parameter SEND_DIG_POS bound to: 40 - type: integer Parameter WIDTH bound to: 289 - type: integer Parameter MAX_DEPTH_BITS bound to: 12 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 4046 - type: integer Parameter WIDTH bound to: 289 - type: integer Parameter MAX_DEPTH_BITS bound to: 12 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 4046 - type: integer Parameter MAX_DEPTH bound to: 4096 - type: integer Parameter WIDTH bound to: 128 - type: integer Parameter MAX_DEPTH_BITS bound to: 11 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 2047 - type: integer Parameter WIDTH bound to: 128 - type: integer Parameter MAX_DEPTH_BITS bound to: 11 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 2047 - type: integer Parameter MAX_DEPTH bound to: 2048 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420] INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420] INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420] INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420] INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420] INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:489] Parameter C_BASE_ADDRESS bound to: 0 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues_cpu_regs.v:414] WARNING: [Synth 8-689] width (16) of port connection 'nf0_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:372] WARNING: [Synth 8-689] width (16) of port connection 'nf1_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:373] WARNING: [Synth 8-689] width (16) of port connection 'nf2_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:374] WARNING: [Synth 8-689] width (16) of port connection 'nf3_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:375] WARNING: [Synth 8-689] width (16) of port connection 'dma_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:376] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_sume_sdnet_wrapper_1'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:282] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'bram_output_queues_1'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:332] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_arbiter_v1_0'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:217] WARNING: [Synth 8-350] instance 'axi_clock_converter_0' of module 'control_sub_axi_clock_converter_0_0' requires 42 connections, but only 40 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:3986] WARNING: [Synth 8-350] instance 'axis_fifo_10g_rx' of module 'control_sub_axis_fifo_10g_rx_0' requires 19 connections, but only 16 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:4270] WARNING: [Synth 8-350] instance 'axis_fifo_10g_tx' of module 'control_sub_axis_fifo_10g_tx_0' requires 19 connections, but only 16 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:4287] WARNING: [Synth 8-350] instance 'nf_riffa_dma_1' of module 'control_sub_nf_riffa_dma_1_0' requires 133 connections, but only 132 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:4304] WARNING: [Synth 8-350] instance 'pcie3_7x_1' of module 'control_sub_pcie3_7x_1_0' requires 90 connections, but only 88 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:4437] WARNING: [Synth 8-350] instance 'xbar' of module 'control_sub_xbar_1' requires 40 connections, but only 38 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:3020] WARNING: [Synth 8-350] instance 'dlmb_v10' of module 'control_sub_dlmb_v10_0' requires 25 connections, but only 24 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:7409] WARNING: [Synth 8-350] instance 'ilmb_v10' of module 'control_sub_ilmb_v10_0' requires 25 connections, but only 24 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:7455] WARNING: [Synth 8-350] instance 'lmb_bram' of module 'control_sub_lmb_bram_0' requires 16 connections, but only 14 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:7480] WARNING: [Synth 8-350] instance 'rst_clk_wiz_1_100M' of module 'control_sub_rst_clk_wiz_1_100M_0' requires 10 connections, but only 9 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:7251] WARNING: [Synth 8-689] width (12) of port connection 'M00_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:698] WARNING: [Synth 8-689] width (12) of port connection 'M00_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:702] WARNING: [Synth 8-689] width (12) of port connection 'M01_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:718] WARNING: [Synth 8-689] width (12) of port connection 'M01_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:722] WARNING: [Synth 8-689] width (12) of port connection 'M02_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:738] WARNING: [Synth 8-689] width (12) of port connection 'M02_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:742] WARNING: [Synth 8-689] width (12) of port connection 'M03_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:758] WARNING: [Synth 8-689] width (12) of port connection 'M03_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:762] WARNING: [Synth 8-689] width (12) of port connection 'M04_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:778] WARNING: [Synth 8-689] width (12) of port connection 'M04_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:782] WARNING: [Synth 8-689] width (12) of port connection 'M05_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:798] WARNING: [Synth 8-689] width (12) of port connection 'M05_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:802] WARNING: [Synth 8-689] width (12) of port connection 'M06_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:818] WARNING: [Synth 8-689] width (12) of port connection 'M06_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:822] WARNING: [Synth 8-689] width (12) of port connection 'M07_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:838] WARNING: [Synth 8-689] width (12) of port connection 'M07_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:842] Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_BASE_ADDRESS bound to: 0 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer Parameter tuser_bits_per_byte bound to: 16 - type: integer Parameter interface_byte_width bound to: 32 - type: integer Parameter tuser_width_intern bound to: 512 - type: integer Parameter tuser_width_remain bound to: 384 - type: integer Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_AXIS_DATA_INTERNAL_WIDTH bound to: 64 - type: integer Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:102] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:103] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:104] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:105] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:106] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:107] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:109] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:110] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:111] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:112] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:113] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:116] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:117] Parameter CONST_VAL bound to: 1 - type: integer Parameter CONST_WIDTH bound to: 1 - type: integer Parameter CONST_VAL bound to: 5 - type: integer Parameter CONST_WIDTH bound to: 3 - type: integer INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:70] INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:72] INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:74] INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:76] INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:79] INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:81] INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:88] INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:90] INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:92] INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:94] INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:96] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter QPLL_FBDIV_TOP bound to: 66 - type: integer Parameter QPLL_FBDIV_IN bound to: 10'b0101000000 Parameter QPLL_FBDIV_RATIO bound to: 1'b0 Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 92 - type: integer Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter QPLL_CFG bound to: 27'b000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0101000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b0 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: FALSE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter CLKCM_CFG bound to: TRUE - type: string Parameter CLKRCV_TRST bound to: TRUE - type: string Parameter CLKSWING_CFG bound to: 2'b11 Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer Parameter C_RVAL bound to: 1'b1 INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_ff_synchronizer_rst.v:72] INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_ff_synchronizer_rst.v:72] Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer Parameter C_RVAL bound to: 1'b0 Parameter MASTER_WATCHDOG_TIMER_RESET bound to: 29'b00110111111000010010110100000 INFO: [Synth 8-5534] Detected attribute (* dont_touch = "yes" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_block.v:202] INFO: [Synth 8-5534] Detected attribute (* dont_touch = "yes" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_block.v:204] Parameter RXRESETTIME_NOM bound to: 24'b000000000000011000011011 Parameter RXRESETTIME_MAX bound to: 24'b000100011010010010100110 Parameter SYNTH_VALUE bound to: 24'b000100011010010010100110 Parameter SIM_VALUE bound to: 24'b000000000000011000011011 Parameter INIT bound to: 2'b10 Parameter INIT bound to: 1'b0 Parameter IS_CLR_INVERTED bound to: 1'b0 Parameter IS_G_INVERTED bound to: 1'b0 Parameter C_NUM_SYNC_REGS bound to: 7 - type: integer Parameter C_RVAL bound to: 1'b1 Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_ff_synchronizer.v:68] INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_ff_synchronizer.v:68] Parameter CABLE_PULL_WATCHDOG_RESET bound to: 20'b00100000000000000000 Parameter CABLE_UNPULL_WATCHDOG_RESET bound to: 20'b00100000000000000000 Parameter GEARBOXSLIP_IGNORE_COUNT bound to: 4'b1111 Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b0 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 Parameter ACJTAG_DEBUG_MODE bound to: 1'b0 Parameter ACJTAG_MODE bound to: 1'b0 Parameter ACJTAG_RESET bound to: 1'b0 Parameter ADAPT_CFG0 bound to: 20'b00000000110000010000 Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string Parameter ALIGN_COMMA_ENABLE bound to: 10'b0001111111 Parameter ALIGN_COMMA_WORD bound to: 1 - type: integer Parameter ALIGN_MCOMMA_DET bound to: FALSE - type: string Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011 Parameter ALIGN_PCOMMA_DET bound to: FALSE - type: string Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100 Parameter A_RXOSCALRESET bound to: 1'b0 Parameter CBCC_DATA_SOURCE_SEL bound to: DECODED - type: string Parameter CFOK_CFG bound to: 42'b100100100000000000000001000000111010000000 Parameter CFOK_CFG2 bound to: 6'b100000 Parameter CFOK_CFG3 bound to: 6'b100000 Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer Parameter CLK_CORRECT_USE bound to: FALSE - type: string Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string Parameter CLK_COR_MAX_LAT bound to: 19 - type: integer Parameter CLK_COR_MIN_LAT bound to: 15 - type: integer Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer Parameter CLK_COR_SEQ_1_1 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_1 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_USE bound to: FALSE - type: string Parameter CLK_COR_SEQ_LEN bound to: 1 - type: integer Parameter CPLL_CFG bound to: 29'b00000101111000000011111011100 Parameter CPLL_FBDIV bound to: 4 - type: integer Parameter CPLL_FBDIV_45 bound to: 5 - type: integer Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110 Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000 Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer Parameter DEC_MCOMMA_DETECT bound to: FALSE - type: string Parameter DEC_PCOMMA_DETECT bound to: FALSE - type: string Parameter DEC_VALID_COMMA_ONLY bound to: FALSE - type: string Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000 Parameter ES_CLK_PHASE_SEL bound to: 1'b0 Parameter ES_CONTROL bound to: 6'b000000 Parameter ES_ERRDET_EN bound to: FALSE - type: string Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string Parameter ES_HORZ_OFFSET bound to: 12'b000000000000 Parameter ES_PMA_CFG bound to: 10'b0000000000 Parameter ES_PRESCALE bound to: 5'b00000 Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_QUAL_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_SDATA_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_VERT_OFFSET bound to: 9'b000000000 Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111 Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111 Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string Parameter GEARBOX_MODE bound to: 3'b001 Parameter IS_CLKRSVD0_INVERTED bound to: 1'b0 Parameter IS_CLKRSVD1_INVERTED bound to: 1'b0 Parameter IS_CPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter IS_DMONITORCLK_INVERTED bound to: 1'b0 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_RXUSRCLK2_INVERTED bound to: 1'b0 Parameter IS_RXUSRCLK_INVERTED bound to: 1'b0 Parameter IS_SIGVALIDCLK_INVERTED bound to: 1'b0 Parameter IS_TXPHDLYTSTCLK_INVERTED bound to: 1'b0 Parameter IS_TXUSRCLK2_INVERTED bound to: 1'b0 Parameter IS_TXUSRCLK_INVERTED bound to: 1'b0 Parameter LOOPBACK_CFG bound to: 1'b0 Parameter OUTREFCLK_SEL_INV bound to: 2'b11 Parameter PCS_PCIE_EN bound to: FALSE - type: string Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100 Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00011001 Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100 Parameter PMA_RSV bound to: 128 - type: integer Parameter PMA_RSV2 bound to: 469762058 - type: integer Parameter PMA_RSV3 bound to: 2'b00 Parameter PMA_RSV4 bound to: 15'b000000000001000 Parameter PMA_RSV5 bound to: 4'b0000 Parameter RESET_POWERSAVE_DISABLE bound to: 1'b0 Parameter RXBUFRESET_TIME bound to: 5'b00001 Parameter RXBUF_ADDR_MODE bound to: FAST - type: string Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000 Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000 Parameter RXBUF_EN bound to: TRUE - type: string Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter RXBUF_THRESH_OVFLW bound to: 61 - type: integer Parameter RXBUF_THRESH_OVRD bound to: FALSE - type: string Parameter RXBUF_THRESH_UNDFLW bound to: 4 - type: integer Parameter RXCDRFREQRESET_TIME bound to: 5'b00001 Parameter RXCDRPHRESET_TIME bound to: 5'b00001 Parameter RXCDR_CFG bound to: 83'b00000000000001000000000011111111110001000000000000011000010000010000000000000011010 Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0 Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RXCDR_LOCK_CFG bound to: 6'b010101 Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0 Parameter RXDFELPMRESET_TIME bound to: 7'b0001111 Parameter RXDLY_CFG bound to: 16'b0000000000011111 Parameter RXDLY_LCFG bound to: 9'b000110000 Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter RXGEARBOX_EN bound to: TRUE - type: string Parameter RXISCANRESET_TIME bound to: 5'b00001 Parameter RXLPM_HF_CFG bound to: 14'b00001000000000 Parameter RXLPM_LF_CFG bound to: 18'b001001000000000000 Parameter RXOOB_CFG bound to: 7'b0000110 Parameter RXOOB_CLK_CFG bound to: PMA - type: string Parameter RXOSCALRESET_TIME bound to: 5'b00011 Parameter RXOSCALRESET_TIMEOUT bound to: 5'b00000 Parameter RXOUT_DIV bound to: 1 - type: integer Parameter RXPCSRESET_TIME bound to: 5'b00001 Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter RXPH_CFG bound to: 24'b110000000000000000000010 Parameter RXPH_MONITOR_SEL bound to: 5'b00000 Parameter RXPI_CFG0 bound to: 2'b00 Parameter RXPI_CFG1 bound to: 2'b11 Parameter RXPI_CFG2 bound to: 2'b11 Parameter RXPI_CFG3 bound to: 2'b11 Parameter RXPI_CFG4 bound to: 1'b0 Parameter RXPI_CFG5 bound to: 1'b0 Parameter RXPI_CFG6 bound to: 3'b100 Parameter RXPMARESET_TIME bound to: 5'b00011 Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0 Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer Parameter RXSLIDE_MODE bound to: OFF - type: string Parameter RXSYNC_MULTILANE bound to: 1'b0 Parameter RXSYNC_OVRD bound to: 1'b0 Parameter RXSYNC_SKIP_DA bound to: 1'b0 Parameter RX_BIAS_CFG bound to: 24'b000011000000000000010000 Parameter RX_BUFFER_CFG bound to: 6'b000000 Parameter RX_CLK25_DIV bound to: 7 - type: integer Parameter RX_CLKMUX_PD bound to: 1'b1 Parameter RX_CM_SEL bound to: 2'b11 Parameter RX_CM_TRIM bound to: 4'b1010 Parameter RX_DATA_WIDTH bound to: 32 - type: integer Parameter RX_DDI_SEL bound to: 6'b000000 Parameter RX_DEBUG_CFG bound to: 14'b00000000000000 Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string Parameter RX_DFELPM_CFG0 bound to: 4'b0110 Parameter RX_DFELPM_CFG1 bound to: 1'b0 Parameter RX_DFELPM_KLKH_AGC_STUP_EN bound to: 1'b1 Parameter RX_DFE_AGC_CFG0 bound to: 2'b00 Parameter RX_DFE_AGC_CFG1 bound to: 3'b100 Parameter RX_DFE_AGC_CFG2 bound to: 4'b0000 Parameter RX_DFE_AGC_OVRDEN bound to: 1'b1 Parameter RX_DFE_GAIN_CFG bound to: 23'b00000000010000011000000 Parameter RX_DFE_H2_CFG bound to: 12'b000000000000 Parameter RX_DFE_H3_CFG bound to: 12'b000001000000 Parameter RX_DFE_H4_CFG bound to: 11'b00011100000 Parameter RX_DFE_H5_CFG bound to: 11'b00011100000 Parameter RX_DFE_H6_CFG bound to: 11'b00000100000 Parameter RX_DFE_H7_CFG bound to: 11'b00000100000 Parameter RX_DFE_KL_CFG bound to: 33'b001000001000000000000001100010000 Parameter RX_DFE_KL_LPM_KH_CFG0 bound to: 2'b01 Parameter RX_DFE_KL_LPM_KH_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KH_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KH_OVRDEN bound to: 1'b1 Parameter RX_DFE_KL_LPM_KL_CFG0 bound to: 2'b10 Parameter RX_DFE_KL_LPM_KL_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KL_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KL_OVRDEN bound to: 1'b1 Parameter RX_DFE_LPM_CFG bound to: 16'b0000000010000000 Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RX_DFE_ST_CFG bound to: 54'b000000111000010000000000000000000011000000000000111111 Parameter RX_DFE_UT_CFG bound to: 17'b00011100000000000 Parameter RX_DFE_VP_CFG bound to: 17'b00011101010100011 Parameter RX_DISPERR_SEQ_MATCH bound to: TRUE - type: string Parameter RX_INT_DATAWIDTH bound to: 1 - type: integer Parameter RX_OS_CFG bound to: 13'b0000010000000 Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer Parameter RX_XCLK_SEL bound to: RXREC - type: string Parameter SAS_MAX_COM bound to: 64 - type: integer Parameter SAS_MIN_COM bound to: 36 - type: integer Parameter SATA_BURST_SEQ_LEN bound to: 4'b1111 Parameter SATA_BURST_VAL bound to: 3'b100 Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string Parameter SATA_EIDLE_VAL bound to: 3'b100 Parameter SATA_MAX_BURST bound to: 8 - type: integer Parameter SATA_MAX_INIT bound to: 21 - type: integer Parameter SATA_MAX_WAKE bound to: 7 - type: integer Parameter SATA_MIN_BURST bound to: 4 - type: integer Parameter SATA_MIN_INIT bound to: 12 - type: integer Parameter SATA_MIN_WAKE bound to: 4 - type: integer Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string Parameter SIM_VERSION bound to: 2.0 - type: string Parameter TERM_RCAL_CFG bound to: 15'b100001000010000 Parameter TERM_RCAL_OVRD bound to: 3'b000 Parameter TRANS_TIME_RATE bound to: 8'b00001110 Parameter TST_RSV bound to: 0 - type: integer Parameter TXBUF_EN bound to: TRUE - type: string Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter TXDLY_CFG bound to: 16'b0000000000011111 Parameter TXDLY_LCFG bound to: 9'b000110000 Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter TXGEARBOX_EN bound to: TRUE - type: string Parameter TXOOB_CFG bound to: 1'b0 Parameter TXOUT_DIV bound to: 1 - type: integer Parameter TXPCSRESET_TIME bound to: 5'b00001 Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter TXPH_CFG bound to: 16'b0000011110000000 Parameter TXPH_MONITOR_SEL bound to: 5'b00000 Parameter TXPI_CFG0 bound to: 2'b00 Parameter TXPI_CFG1 bound to: 2'b00 Parameter TXPI_CFG2 bound to: 2'b00 Parameter TXPI_CFG3 bound to: 1'b0 Parameter TXPI_CFG4 bound to: 1'b0 Parameter TXPI_CFG5 bound to: 3'b100 Parameter TXPI_GREY_SEL bound to: 1'b0 Parameter TXPI_INVSTROBE_SEL bound to: 1'b0 Parameter TXPI_PPMCLK_SEL bound to: TXUSRCLK2 - type: string Parameter TXPI_PPM_CFG bound to: 8'b00000000 Parameter TXPI_SYNFREQ_PPM bound to: 3'b000 Parameter TXPMARESET_TIME bound to: 5'b00001 Parameter TXSYNC_MULTILANE bound to: 1'b0 Parameter TXSYNC_OVRD bound to: 1'b0 Parameter TXSYNC_SKIP_DA bound to: 1'b0 Parameter TX_CLK25_DIV bound to: 7 - type: integer Parameter TX_CLKMUX_PD bound to: 1'b1 Parameter TX_DATA_WIDTH bound to: 32 - type: integer Parameter TX_DEEMPH0 bound to: 6'b000000 Parameter TX_DEEMPH1 bound to: 6'b000000 Parameter TX_DRIVE_MODE bound to: DIRECT - type: string Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110 Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100 Parameter TX_INT_DATAWIDTH bound to: 1 - type: integer Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string Parameter TX_MAINCURSOR_SEL bound to: 1'b0 Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110 Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001 Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101 Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010 Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110 Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100 Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010 Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000 Parameter TX_QPI_STATUS_EN bound to: 1'b0 Parameter TX_RXDETECT_CFG bound to: 14'b01100000110010 Parameter TX_RXDETECT_PRECHARGE_TIME bound to: 17'b10101010111001100 Parameter TX_RXDETECT_REF bound to: 3'b100 Parameter TX_XCLK_SEL bound to: TXOUT - type: string Parameter UCODEER_CLR bound to: 1'b0 Parameter USE_PCS_CLK_PHASE_SEL bound to: 1'b0 WARNING: [Synth 8-689] width (2) of port connection 'mac_status_vector' does not match port width (3) of module 'axi_10g_ethernet_shared' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:163] WARNING: [Synth 8-350] instance 'axi_10g_ethernet_i' of module 'axi_10g_ethernet_shared' requires 51 connections, but only 50 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:147] Parameter C_OPERATION bound to: not - type: string Parameter C_SIZE bound to: 1 - type: integer Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_DEFAULT_VALUE_ENABLE bound to: 1 - type: integer Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer Parameter C_M_AXIS_DATA_WIDTH_INTERNAL bound to: 64 - type: integer Parameter C_S_AXIS_DATA_WIDTH_INTERNAL bound to: 64 - type: integer Parameter NUM_RW_REGS bound to: 1 - type: integer Parameter NUM_RO_REGS bound to: 17 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_USE_WSTRB bound to: 0 - type: integer INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:117] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:118] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:119] INFO: [Common 17-14] Message 'Synth 8-5534' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter C_NUM_SYNC_REGS bound to: 6 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter IDLE bound to: 0 - type: integer Parameter WAIT_FOR_EOP bound to: 1 - type: integer Parameter DROP bound to: 2 - type: integer Parameter BUBBLE bound to: 3 - type: integer Parameter ERR_IDLE bound to: 0 - type: integer Parameter ERR_WAIT bound to: 1 - type: integer Parameter ERR_BUBBLE bound to: 2 - type: integer Parameter ALMOST_EMPTY_OFFSET bound to: 9'b000001010 Parameter ALMOST_FULL_OFFSET bound to: 9'b100101100 Parameter DATA_WIDTH bound to: 72 - type: integer Parameter DO_REG bound to: 1 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter EN_SYN bound to: FALSE - type: string Parameter FIFO_MODE bound to: FIFO36_72 - type: string Parameter FIRST_WORD_FALL_THROUGH bound to: TRUE - type: string Parameter INIT bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 Parameter IS_RDCLK_INVERTED bound to: 1'b0 Parameter IS_RDEN_INVERTED bound to: 1'b0 Parameter IS_RSTREG_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter IS_WRCLK_INVERTED bound to: 1'b0 Parameter IS_WREN_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-638] synthesizing module 'fifo_generator_1_9' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/synth/fifo_generator_1_9.vhd:75] Parameter C_COMMON_CLOCK bound to: 0 - type: integer Parameter C_SELECT_XPM bound to: 0 - type: integer Parameter C_COUNT_TYPE bound to: 0 - type: integer Parameter C_DATA_COUNT_WIDTH bound to: 4 - type: integer Parameter C_DEFAULT_VALUE bound to: BlankString - type: string Parameter C_DIN_WIDTH bound to: 1 - type: integer Parameter C_DOUT_RST_VAL bound to: 0 - type: string Parameter C_DOUT_WIDTH bound to: 1 - type: integer Parameter C_ENABLE_RLOCS bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_FULL_FLAGS_RST_VAL bound to: 1 - type: integer Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer Parameter C_HAS_BACKUP bound to: 0 - type: integer Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_INT_CLK bound to: 0 - type: integer Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer Parameter C_HAS_OVERFLOW bound to: 0 - type: integer Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_RD_RST bound to: 0 - type: integer Parameter C_HAS_RST bound to: 1 - type: integer Parameter C_HAS_SRST bound to: 0 - type: integer Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer Parameter C_HAS_VALID bound to: 0 - type: integer Parameter C_HAS_WR_ACK bound to: 0 - type: integer Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_WR_RST bound to: 0 - type: integer Parameter C_IMPLEMENTATION_TYPE bound to: 2 - type: integer Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer Parameter C_MEMORY_TYPE bound to: 1 - type: integer Parameter C_MIF_FILE_NAME bound to: BlankString - type: string Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer Parameter C_OVERFLOW_LOW bound to: 0 - type: integer Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer Parameter C_PRELOAD_REGS bound to: 1 - type: integer Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 15 - type: integer Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 14 - type: integer Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer Parameter C_RD_DATA_COUNT_WIDTH bound to: 4 - type: integer Parameter C_RD_DEPTH bound to: 16 - type: integer Parameter C_RD_FREQ bound to: 1 - type: integer Parameter C_RD_PNTR_WIDTH bound to: 4 - type: integer Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer Parameter C_USE_DOUT_RST bound to: 1 - type: integer Parameter C_USE_ECC bound to: 0 - type: integer Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer Parameter C_VALID_LOW bound to: 0 - type: integer Parameter C_WR_ACK_LOW bound to: 0 - type: integer Parameter C_WR_DATA_COUNT_WIDTH bound to: 4 - type: integer Parameter C_WR_DEPTH bound to: 16 - type: integer Parameter C_WR_FREQ bound to: 1 - type: integer Parameter C_WR_PNTR_WIDTH bound to: 4 - type: integer Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer Parameter C_MSGON_VAL bound to: 1 - type: integer Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer Parameter C_EN_SAFETY_CKT bound to: 1 - type: integer Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer Parameter C_INTERFACE_TYPE bound to: 0 - type: integer Parameter C_AXI_TYPE bound to: 1 - type: integer Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer Parameter C_HAS_MASTER_CE bound to: 0 - type: integer Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer Parameter C_HAS_AXI_ID bound to: 0 - type: integer Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer Parameter C_HAS_AXIS_TID bound to: 0 - type: integer Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer Parameter C_WACH_TYPE bound to: 0 - type: integer Parameter C_WDCH_TYPE bound to: 0 - type: integer Parameter C_WRCH_TYPE bound to: 0 - type: integer Parameter C_RACH_TYPE bound to: 0 - type: integer Parameter C_RDCH_TYPE bound to: 0 - type: integer Parameter C_AXIS_TYPE bound to: 0 - type: integer Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx18 - type: string Parameter C_USE_ECC_WACH bound to: 0 - type: integer Parameter C_USE_ECC_WDCH bound to: 0 - type: integer Parameter C_USE_ECC_WRCH bound to: 0 - type: integer Parameter C_USE_ECC_RACH bound to: 0 - type: integer Parameter C_USE_ECC_RDCH bound to: 0 - type: integer Parameter C_USE_ECC_AXIS bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer Parameter C_DIN_WIDTH_WACH bound to: 1 - type: integer Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer INFO: [Synth 8-3491] module 'fifo_generator_v13_2_2' declared at '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/fifo_generator_v13_2_2/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38483' bound to instance 'U0' of component 'fifo_generator_v13_2_2' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/synth/fifo_generator_1_9.vhd:545] INFO: [Synth 8-256] done synthesizing module 'fifo_generator_1_9' (1251#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/synth/fifo_generator_1_9.vhd:75] WARNING: [Synth 8-350] instance 'rx_info_fifo' of module 'fifo_generator_1_9' requires 11 connections, but only 9 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/rx_queue.v:148] INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/rx_queue.v:175] INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/rx_queue.v:247] Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_S_AXIS_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_LEN_WIDTH bound to: 16 - type: integer Parameter C_SPT_WIDTH bound to: 8 - type: integer Parameter C_DPT_WIDTH bound to: 8 - type: integer Parameter C_DEFAULT_VALUE_ENABLE bound to: 1 - type: integer Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_S_AXIS_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_LEN_WIDTH bound to: 16 - type: integer Parameter C_SPT_WIDTH bound to: 8 - type: integer Parameter C_DPT_WIDTH bound to: 8 - type: integer Parameter C_DEFAULT_VALUE_ENABLE bound to: 1 - type: integer Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer Parameter MAX_PKT_SIZE bound to: 1600 - type: integer Parameter LENGTH_COUNTER_WIDTH bound to: 3 - type: integer Parameter IN_FIFO_DEPTH_BIT bound to: 8 - type: integer Parameter M_S_RATIO_COUNT bound to: 4 - type: integer Parameter S_M_RATIO_COUNT bound to: 0 - type: integer Parameter METADATA_STATE_WAIT_START bound to: 0 - type: integer Parameter METADATA_STATE_WAIT_END bound to: 1 - type: integer Parameter WIDTH bound to: 16 - type: integer Parameter MAX_DEPTH_BITS bound to: 5 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer Parameter WIDTH bound to: 16 - type: integer Parameter MAX_DEPTH_BITS bound to: 5 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer Parameter MAX_DEPTH bound to: 32 - type: integer Parameter WIDTH bound to: 73 - type: integer Parameter MAX_DEPTH_BITS bound to: 8 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 255 - type: integer Parameter WIDTH bound to: 73 - type: integer Parameter MAX_DEPTH_BITS bound to: 8 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 255 - type: integer Parameter MAX_DEPTH bound to: 256 - type: integer Parameter C_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter WAIT_START bound to: 0 - type: integer Parameter RCV_WORD bound to: 1 - type: integer Parameter L2_IFSM_STATES bound to: 1 - type: integer Parameter RFSM_START bound to: 0 - type: integer Parameter RFSM_FINISH_PKT bound to: 1 - type: integer Parameter L2_RFSM_STATES bound to: 1 - type: integer Parameter MAX_PKT_SIZE bound to: 2048 - type: integer Parameter MIN_PKT_SIZE bound to: 64 - type: integer Parameter MAX_PKTS bound to: 32 - type: integer Parameter MAX_DEPTH bound to: 8 - type: integer Parameter L2_MAX_DEPTH bound to: 3 - type: integer Parameter L2_MAX_PKTS bound to: 5 - type: integer Parameter WIDTH bound to: 289 - type: integer Parameter MAX_DEPTH_BITS bound to: 3 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 7 - type: integer Parameter WIDTH bound to: 289 - type: integer Parameter MAX_DEPTH_BITS bound to: 3 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 7 - type: integer Parameter MAX_DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 128 - type: integer Parameter MAX_DEPTH_BITS bound to: 5 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer Parameter WIDTH bound to: 128 - type: integer Parameter MAX_DEPTH_BITS bound to: 5 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer Parameter MAX_DEPTH bound to: 32 - type: integer Parameter C_M_AXIS_DATA_WIDTH bound to: 64 - type: integer Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_LEN_WIDTH bound to: 16 - type: integer Parameter C_SPT_WIDTH bound to: 8 - type: integer Parameter C_DPT_WIDTH bound to: 8 - type: integer Parameter C_DEFAULT_VALUE_ENABLE bound to: 1'b0 Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer Parameter C_M_AXIS_DATA_WIDTH bound to: 64 - type: integer Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_LEN_WIDTH bound to: 16 - type: integer Parameter C_SPT_WIDTH bound to: 8 - type: integer Parameter C_DPT_WIDTH bound to: 8 - type: integer Parameter C_DEFAULT_VALUE_ENABLE bound to: 1'b0 Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer Parameter MAX_PKT_SIZE bound to: 1600 - type: integer Parameter LENGTH_COUNTER_WIDTH bound to: 5 - type: integer Parameter IN_FIFO_DEPTH_BIT bound to: 6 - type: integer Parameter M_S_RATIO_COUNT bound to: 0 - type: integer Parameter S_M_RATIO_COUNT bound to: 4 - type: integer Parameter METADATA_STATE_WAIT_START bound to: 0 - type: integer Parameter METADATA_STATE_WAIT_END bound to: 1 - type: integer Parameter WIDTH bound to: 289 - type: integer Parameter MAX_DEPTH_BITS bound to: 6 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer Parameter WIDTH bound to: 289 - type: integer Parameter MAX_DEPTH_BITS bound to: 6 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer Parameter MAX_DEPTH bound to: 64 - type: integer WARNING: [Synth 8-6014] Unused sequential element SLAVE_WIDER.length_prev_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_axis_converter_main.v:514] Parameter C_AXIS_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter WAIT_START bound to: 0 - type: integer Parameter RCV_WORD bound to: 1 - type: integer Parameter L2_IFSM_STATES bound to: 1 - type: integer Parameter RFSM_START bound to: 0 - type: integer Parameter RFSM_FINISH_PKT bound to: 1 - type: integer Parameter L2_RFSM_STATES bound to: 1 - type: integer Parameter MAX_PKT_SIZE bound to: 2048 - type: integer Parameter MIN_PKT_SIZE bound to: 64 - type: integer Parameter MAX_PKTS bound to: 32 - type: integer Parameter MAX_DEPTH bound to: 32 - type: integer Parameter L2_MAX_DEPTH bound to: 5 - type: integer Parameter L2_MAX_PKTS bound to: 5 - type: integer Parameter WIDTH bound to: 73 - type: integer Parameter MAX_DEPTH_BITS bound to: 5 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer Parameter WIDTH bound to: 73 - type: integer Parameter MAX_DEPTH_BITS bound to: 5 - type: integer Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer Parameter MAX_DEPTH bound to: 32 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter IDLE bound to: 2'b00 Parameter SEND_PKT bound to: 2'b01 Parameter METADATA bound to: 1'b0 Parameter EOP bound to: 1'b1 Parameter ALMOST_EMPTY_OFFSET bound to: 9'b000001010 Parameter ALMOST_FULL_OFFSET bound to: 9'b100000000 Parameter DATA_WIDTH bound to: 72 - type: integer Parameter DO_REG bound to: 1 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter EN_SYN bound to: FALSE - type: string Parameter FIFO_MODE bound to: FIFO36_72 - type: string Parameter FIRST_WORD_FALL_THROUGH bound to: TRUE - type: string Parameter INIT bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 Parameter IS_RDCLK_INVERTED bound to: 1'b0 Parameter IS_RDEN_INVERTED bound to: 1'b0 Parameter IS_RSTREG_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter IS_WRCLK_INVERTED bound to: 1'b0 Parameter IS_WREN_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'tx_info_fifo' of module 'fifo_generator_1_9' requires 11 connections, but only 9 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/tx_queue.v:153] INFO: [Synth 8-226] default block is never used [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/tx_queue.v:208] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'rx_fifo_intf'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:180] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'converter_rx'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:222] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'converter_tx'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:258] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'tx_fifo_intf'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:290] INFO: [Synth 8-638] synthesizing module 'fifo_generator_status' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/synth/fifo_generator_status.vhd:72] Parameter C_COMMON_CLOCK bound to: 0 - type: integer Parameter C_SELECT_XPM bound to: 0 - type: integer Parameter C_COUNT_TYPE bound to: 0 - type: integer Parameter C_DATA_COUNT_WIDTH bound to: 4 - type: integer Parameter C_DEFAULT_VALUE bound to: BlankString - type: string Parameter C_DIN_WIDTH bound to: 458 - type: integer Parameter C_DOUT_RST_VAL bound to: 0 - type: string Parameter C_DOUT_WIDTH bound to: 458 - type: integer Parameter C_ENABLE_RLOCS bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer Parameter C_HAS_BACKUP bound to: 0 - type: integer Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_INT_CLK bound to: 0 - type: integer Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer Parameter C_HAS_OVERFLOW bound to: 0 - type: integer Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_RD_RST bound to: 0 - type: integer Parameter C_HAS_RST bound to: 0 - type: integer Parameter C_HAS_SRST bound to: 0 - type: integer Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer Parameter C_HAS_VALID bound to: 0 - type: integer Parameter C_HAS_WR_ACK bound to: 0 - type: integer Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_WR_RST bound to: 0 - type: integer Parameter C_IMPLEMENTATION_TYPE bound to: 2 - type: integer Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer Parameter C_MEMORY_TYPE bound to: 1 - type: integer Parameter C_MIF_FILE_NAME bound to: BlankString - type: string Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer Parameter C_OVERFLOW_LOW bound to: 0 - type: integer Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer Parameter C_PRELOAD_REGS bound to: 1 - type: integer Parameter C_PRIM_FIFO_TYPE bound to: 512x72 - type: string Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 15 - type: integer Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 14 - type: integer Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer Parameter C_RD_DATA_COUNT_WIDTH bound to: 4 - type: integer Parameter C_RD_DEPTH bound to: 16 - type: integer Parameter C_RD_FREQ bound to: 1 - type: integer Parameter C_RD_PNTR_WIDTH bound to: 4 - type: integer Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer Parameter C_USE_DOUT_RST bound to: 0 - type: integer Parameter C_USE_ECC bound to: 0 - type: integer Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer Parameter C_VALID_LOW bound to: 0 - type: integer Parameter C_WR_ACK_LOW bound to: 0 - type: integer Parameter C_WR_DATA_COUNT_WIDTH bound to: 4 - type: integer Parameter C_WR_DEPTH bound to: 16 - type: integer Parameter C_WR_FREQ bound to: 1 - type: integer Parameter C_WR_PNTR_WIDTH bound to: 4 - type: integer Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer Parameter C_MSGON_VAL bound to: 1 - type: integer Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer Parameter C_INTERFACE_TYPE bound to: 0 - type: integer Parameter C_AXI_TYPE bound to: 1 - type: integer Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer Parameter C_HAS_MASTER_CE bound to: 0 - type: integer Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer Parameter C_HAS_AXI_ID bound to: 0 - type: integer Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer Parameter C_HAS_AXIS_TID bound to: 0 - type: integer Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer Parameter C_WACH_TYPE bound to: 0 - type: integer Parameter C_WDCH_TYPE bound to: 0 - type: integer Parameter C_WRCH_TYPE bound to: 0 - type: integer Parameter C_RACH_TYPE bound to: 0 - type: integer Parameter C_RDCH_TYPE bound to: 0 - type: integer Parameter C_AXIS_TYPE bound to: 0 - type: integer Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx18 - type: string Parameter C_USE_ECC_WACH bound to: 0 - type: integer Parameter C_USE_ECC_WDCH bound to: 0 - type: integer Parameter C_USE_ECC_WRCH bound to: 0 - type: integer Parameter C_USE_ECC_RACH bound to: 0 - type: integer Parameter C_USE_ECC_RDCH bound to: 0 - type: integer Parameter C_USE_ECC_AXIS bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer Parameter C_DIN_WIDTH_WACH bound to: 1 - type: integer Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer INFO: [Synth 8-3491] module 'fifo_generator_v13_2_2' declared at '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/fifo_generator_v13_2_2/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38483' bound to instance 'U0' of component 'fifo_generator_v13_2_2' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/synth/fifo_generator_status.vhd:542] INFO: [Synth 8-256] done synthesizing module 'fifo_generator_status' (1258#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/synth/fifo_generator_status.vhd:72] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'xge_attachment'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:228] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'axi_10g_ethernet_i'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:147] Parameter C_BASE_ADDRESS bound to: 0 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_cpu_regs.v:322] Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_BASE_ADDRESS bound to: 0 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer Parameter tuser_bits_per_byte bound to: 16 - type: integer Parameter interface_byte_width bound to: 32 - type: integer Parameter tuser_width_intern bound to: 512 - type: integer Parameter tuser_width_remain bound to: 384 - type: integer Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer Parameter C_AXIS_DATA_INTERNAL_WIDTH bound to: 64 - type: integer Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer Parameter MASTER_WATCHDOG_TIMER_RESET bound to: 29'b00110111111000010010110100000 Parameter RXRESETTIME_NOM bound to: 24'b000000000000011000011011 Parameter RXRESETTIME_MAX bound to: 24'b000100011010010010100110 Parameter SYNTH_VALUE bound to: 24'b000100011010010010100110 Parameter SIM_VALUE bound to: 24'b000000000000011000011011 Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer Parameter C_RVAL bound to: 1'b1 Parameter C_NUM_SYNC_REGS bound to: 7 - type: integer Parameter C_RVAL bound to: 1'b1 Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer Parameter C_RVAL bound to: 1'b0 Parameter CABLE_PULL_WATCHDOG_RESET bound to: 20'b00100000000000000000 Parameter CABLE_UNPULL_WATCHDOG_RESET bound to: 20'b00100000000000000000 Parameter GEARBOXSLIP_IGNORE_COUNT bound to: 4'b1111 Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b0 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 WARNING: [Synth 8-689] width (2) of port connection 'mac_status_vector' does not match port width (3) of module 'axi_10g_ethernet_nonshared' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_block.v:164] WARNING: [Synth 8-350] instance 'axi_10g_ethernet_i' of module 'axi_10g_ethernet_nonshared' requires 51 connections, but only 50 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_block.v:148] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'axi_10g_ethernet_i'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_block.v:148] Parameter C_BASE_ADDRESS bound to: 0 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs.v:322] INFO: [Synth 8-638] synthesizing module 'identifier_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/synth/identifier_ip.vhd:85] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_XDEVICEFAMILY bound to: virtex7 - type: string Parameter C_ELABORATION_DIR bound to: ./ - type: string Parameter C_INTERFACE_TYPE bound to: 1 - type: integer Parameter C_AXI_TYPE bound to: 0 - type: integer Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string Parameter C_HAS_AXI_ID bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer Parameter C_MEM_TYPE bound to: 1 - type: integer Parameter C_BYTE_SIZE bound to: 8 - type: integer Parameter C_ALGORITHM bound to: 1 - type: integer Parameter C_PRIM_TYPE bound to: 1 - type: integer Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer Parameter C_INIT_FILE_NAME bound to: identifier_ip.mif - type: string Parameter C_INIT_FILE bound to: identifier_ip.mem - type: string Parameter C_USE_DEFAULT_DATA bound to: 1 - type: integer Parameter C_DEFAULT_DATA bound to: DEADDEAD - type: string Parameter C_HAS_RSTA bound to: 0 - type: integer Parameter C_RST_PRIORITY_A bound to: CE - type: string Parameter C_RSTRAM_A bound to: 0 - type: integer Parameter C_INITA_VAL bound to: 0 - type: string Parameter C_HAS_ENA bound to: 1 - type: integer Parameter C_HAS_REGCEA bound to: 0 - type: integer Parameter C_USE_BYTE_WEA bound to: 1 - type: integer Parameter C_WEA_WIDTH bound to: 4 - type: integer Parameter C_WRITE_MODE_A bound to: READ_FIRST - type: string Parameter C_WRITE_WIDTH_A bound to: 32 - type: integer Parameter C_READ_WIDTH_A bound to: 32 - type: integer Parameter C_WRITE_DEPTH_A bound to: 4096 - type: integer Parameter C_READ_DEPTH_A bound to: 4096 - type: integer Parameter C_ADDRA_WIDTH bound to: 12 - type: integer Parameter C_HAS_RSTB bound to: 1 - type: integer Parameter C_RST_PRIORITY_B bound to: CE - type: string Parameter C_RSTRAM_B bound to: 0 - type: integer Parameter C_INITB_VAL bound to: 0 - type: string Parameter C_HAS_ENB bound to: 1 - type: integer Parameter C_HAS_REGCEB bound to: 0 - type: integer Parameter C_USE_BYTE_WEB bound to: 1 - type: integer Parameter C_WEB_WIDTH bound to: 4 - type: integer Parameter C_WRITE_MODE_B bound to: READ_FIRST - type: string Parameter C_WRITE_WIDTH_B bound to: 32 - type: integer Parameter C_READ_WIDTH_B bound to: 32 - type: integer Parameter C_WRITE_DEPTH_B bound to: 4096 - type: integer Parameter C_READ_DEPTH_B bound to: 4096 - type: integer Parameter C_ADDRB_WIDTH bound to: 12 - type: integer Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 0 - type: integer Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer Parameter C_USE_SOFTECC bound to: 0 - type: integer Parameter C_USE_ECC bound to: 0 - type: integer Parameter C_EN_ECC_PIPE bound to: 0 - type: integer Parameter C_HAS_INJECTERR bound to: 0 - type: integer Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string Parameter C_COMMON_CLK bound to: 1 - type: integer Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer Parameter C_USE_URAM bound to: 0 - type: integer Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer Parameter C_EN_SAFETY_CKT bound to: 1 - type: integer Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer Parameter C_COUNT_36K_BRAM bound to: 4 - type: string Parameter C_COUNT_18K_BRAM bound to: 0 - type: string Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 21.0181 mW - type: string INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_1' declared at '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/blk_mem_gen_v8_4_1/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195313' bound to instance 'U0' of component 'blk_mem_gen_v8_4_1' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/synth/identifier_ip.vhd:265] INFO: [Synth 8-256] done synthesizing module 'identifier_ip' (1290#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/synth/identifier_ip.vhd:85] WARNING: [Synth 8-689] width (12) of port connection 's_axi_awaddr' does not match port width (32) of module 'identifier_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1229] WARNING: [Synth 8-689] width (12) of port connection 's_axi_araddr' does not match port width (32) of module 'identifier_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1239] WARNING: [Synth 8-350] instance 'identifier' of module 'identifier_ip' requires 21 connections, but only 19 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1226] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_datapath_0'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:564] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_10g_interface_0'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:908] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_10g_interface_1'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:990] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_10g_interface_2'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1068] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_10g_interface_3'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1148] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'control_sub_i'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:696] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_RLAST WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_R_LAST_INT WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[7] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[6] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[5] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[4] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[3] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARSIZE[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARSIZE[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARSIZE[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARBURST[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARBURST[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARID[3] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARID[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARID[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARID[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MUX_RST[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MEM_LAT_RST WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MEM_REG_RST WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MUX_REGCE[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MEM_REGCE WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port WE WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[11] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[10] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[9] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[8] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[7] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[6] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[5] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[4] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[3] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[7] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[6] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[5] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[3] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[7] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[6] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[5] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[4] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[3] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ECCPIPECE WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MUX_RST[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MEM_LAT_RST WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MEM_REG_RST WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MUX_REGCE[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MEM_REGCE WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port WE WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[11] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[10] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[9] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[8] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[7] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[6] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[5] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[4] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[3] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[7] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[6] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[5] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[4] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[3] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[7] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[6] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[5] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[4] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[3] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ECCPIPECE WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port SSRA WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port REGCEA WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port SSRB WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port WEB[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[8] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[7] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[6] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[5] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[4] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[3] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[2] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:03:14 ; elapsed = 00:03:44 . Memory (MB): peak = 3416.000 ; gain = 2084.918 ; free physical = 6101 ; free virtual = 26316 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ WARNING: [Synth 8-3295] tying undriven pin arbiter_cpu_regs_inst:cpu_resetn_soft to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter.v:348] WARNING: [Synth 8-3295] tying undriven pin du6df7ou4c9jzix9kt8y8sp35_875:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:409] WARNING: [Synth 8-3295] tying undriven pin du6df7ou4c9jzix9kt8y8sp35_875:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:409] WARNING: [Synth 8-3295] tying undriven pin rc2oqgemebaubffc_998:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:450] WARNING: [Synth 8-3295] tying undriven pin rc2oqgemebaubffc_998:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:450] WARNING: [Synth 8-3295] tying undriven pin s8zvr35avia82az9e4ga7z_2508:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:491] WARNING: [Synth 8-3295] tying undriven pin s8zvr35avia82az9e4ga7z_2508:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:491] WARNING: [Synth 8-3295] tying undriven pin d4cl8nwtlfqqa3qq1emn6smhnhrj_2144:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:534] WARNING: [Synth 8-3295] tying undriven pin d4cl8nwtlfqqa3qq1emn6smhnhrj_2144:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:534] WARNING: [Synth 8-3295] tying undriven pin ow8vk1v7n14yey1jc5d040hf1440r1x_695:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:661] WARNING: [Synth 8-3295] tying undriven pin ow8vk1v7n14yey1jc5d040hf1440r1x_695:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:661] WARNING: [Synth 8-3295] tying undriven pin xtsdogepbxcg3t8fqtbed8as0e1l_2610:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:702] WARNING: [Synth 8-3295] tying undriven pin xtsdogepbxcg3t8fqtbed8as0e1l_2610:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:702] WARNING: [Synth 8-3295] tying undriven pin emsxcy8c153tkouy17br04f_2299:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:743] WARNING: [Synth 8-3295] tying undriven pin emsxcy8c153tkouy17br04f_2299:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:743] WARNING: [Synth 8-3295] tying undriven pin v2x1yvitwpecodsxcz4bwdpizcg445_375:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:786] WARNING: [Synth 8-3295] tying undriven pin v2x1yvitwpecodsxcz4bwdpizcg445_375:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:786] WARNING: [Synth 8-3295] tying undriven pin owseb8koh0tm5b2cm23kfowmsv_348:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:829] WARNING: [Synth 8-3295] tying undriven pin owseb8koh0tm5b2cm23kfowmsv_348:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:829] WARNING: [Synth 8-3295] tying undriven pin l7152fs74u8zwxog2cx_2460:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:872] WARNING: [Synth 8-3295] tying undriven pin l7152fs74u8zwxog2cx_2460:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:872] WARNING: [Synth 8-3295] tying undriven pin lci0djz2hlarkew5g4z4wemft697fr_2582:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:915] WARNING: [Synth 8-3295] tying undriven pin lci0djz2hlarkew5g4z4wemft697fr_2582:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:915] WARNING: [Synth 8-3295] tying undriven pin xpemdowtjrj47j8atnb65h4v07_1130:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:958] WARNING: [Synth 8-3295] tying undriven pin xpemdowtjrj47j8atnb65h4v07_1130:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:958] WARNING: [Synth 8-3295] tying undriven pin vxh8gue8epq6gxze_685:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:850] WARNING: [Synth 8-3295] tying undriven pin vxh8gue8epq6gxze_685:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:850] WARNING: [Synth 8-3295] tying undriven pin zmtz6gstdn71pkc38oscb260fx_746:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:891] WARNING: [Synth 8-3295] tying undriven pin zmtz6gstdn71pkc38oscb260fx_746:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:891] WARNING: [Synth 8-3295] tying undriven pin oggsepfdbfvc08g925kumcu8ai081hf_2487:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:932] WARNING: [Synth 8-3295] tying undriven pin oggsepfdbfvc08g925kumcu8ai081hf_2487:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:932] WARNING: [Synth 8-3295] tying undriven pin wdeecdhsjseok1s3v750r3jb_550:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:975] WARNING: [Synth 8-3295] tying undriven pin wdeecdhsjseok1s3v750r3jb_550:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:975] WARNING: [Synth 8-3295] tying undriven pin h2gi6oqvy2ath2fk_362:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1018] WARNING: [Synth 8-3295] tying undriven pin h2gi6oqvy2ath2fk_362:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1018] WARNING: [Synth 8-3295] tying undriven pin wneadextejr1frvvs0h8_344:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1061] WARNING: [Synth 8-3295] tying undriven pin wneadextejr1frvvs0h8_344:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1061] WARNING: [Synth 8-3295] tying undriven pin wip2u61mji55unuwjs6ipl7grolkp_1787:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1104] WARNING: [Synth 8-3295] tying undriven pin wip2u61mji55unuwjs6ipl7grolkp_1787:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1104] WARNING: [Synth 8-3295] tying undriven pin d7gumo82gk6md4n6jh72oukr_1045:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1147] WARNING: [Synth 8-3295] tying undriven pin d7gumo82gk6md4n6jh72oukr_1045:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1147] WARNING: [Synth 8-3295] tying undriven pin vbsfwqsy6fejb9tjlqq1_2668:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1190] WARNING: [Synth 8-3295] tying undriven pin vbsfwqsy6fejb9tjlqq1_2668:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1190] WARNING: [Synth 8-3295] tying undriven pin y0o0b5b83atg8om0jqdqe2p3pwoxl_1489:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1233] WARNING: [Synth 8-3295] tying undriven pin y0o0b5b83atg8om0jqdqe2p3pwoxl_1489:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1233] WARNING: [Synth 8-3295] tying undriven pin v25jqojnept4a2izwn4c0gio6doe0h_1269:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1276] WARNING: [Synth 8-3295] tying undriven pin v25jqojnept4a2izwn4c0gio6doe0h_1269:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1276] WARNING: [Synth 8-3295] tying undriven pin ueoy8q1oq92abqdr6cavsnehcsseh_7:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:661] WARNING: [Synth 8-3295] tying undriven pin ueoy8q1oq92abqdr6cavsnehcsseh_7:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:661] WARNING: [Synth 8-3295] tying undriven pin xt6i6t0dtbr9k9ux4848l_2541:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:702] WARNING: [Synth 8-3295] tying undriven pin xt6i6t0dtbr9k9ux4848l_2541:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:702] WARNING: [Synth 8-3295] tying undriven pin dkcs1lf2vu5dwmt01vw9eqs5xby_452:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:743] WARNING: [Synth 8-3295] tying undriven pin dkcs1lf2vu5dwmt01vw9eqs5xby_452:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:743] WARNING: [Synth 8-3295] tying undriven pin c1szjispkb2i6ti1o_2213:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:786] WARNING: [Synth 8-3295] tying undriven pin c1szjispkb2i6ti1o_2213:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:786] WARNING: [Synth 8-3295] tying undriven pin gp2sxhuvbjmdw26h21zj5zo4h94_979:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:829] WARNING: [Synth 8-3295] tying undriven pin gp2sxhuvbjmdw26h21zj5zo4h94_979:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:829] WARNING: [Synth 8-3295] tying undriven pin osugxrkciuq7h54lwjvabg_1385:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:872] WARNING: [Synth 8-3295] tying undriven pin osugxrkciuq7h54lwjvabg_1385:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:872] WARNING: [Synth 8-3295] tying undriven pin s01rsqufj7k6k4vnqmz3teozsv22_143:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:915] WARNING: [Synth 8-3295] tying undriven pin s01rsqufj7k6k4vnqmz3teozsv22_143:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:915] WARNING: [Synth 8-3295] tying undriven pin os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:958] WARNING: [Synth 8-3295] tying undriven pin os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:958] WARNING: [Synth 8-3295] tying undriven pin qyfmxlhxtgqyj78i3mu2sw5_2306:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:479] WARNING: [Synth 8-3295] tying undriven pin qyfmxlhxtgqyj78i3mu2sw5_2306:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:479] WARNING: [Synth 8-3295] tying undriven pin ehndy8vbflb0gxuke3lnsjm_77:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:520] WARNING: [Synth 8-3295] tying undriven pin ehndy8vbflb0gxuke3lnsjm_77:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:520] WARNING: [Synth 8-3295] tying undriven pin a6l5ilsonpwsue0o_2404:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:561] WARNING: [Synth 8-3295] tying undriven pin a6l5ilsonpwsue0o_2404:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:561] WARNING: [Synth 8-3295] tying undriven pin a1j85vyq4aadbgoq5b7orqtbwpa_1948:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:604] WARNING: [Synth 8-3295] tying undriven pin a1j85vyq4aadbgoq5b7orqtbwpa_1948:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:604] WARNING: [Synth 8-3295] tying undriven pin sss_output_queues_cpu_regs_inst:cpu_resetn_soft to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:643] WARNING: [Synth 8-3295] tying undriven pin nf_10g_interface_shared_cpu_regs_inst:cpu_resetn_soft to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared.v:261] WARNING: [Synth 8-3295] tying undriven pin nf_10g_interface_cpu_regs_inst:cpu_resetn_soft to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface.v:262] --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:03:29 ; elapsed = 00:03:59 . Memory (MB): peak = 3416.000 ; gain = 2084.918 ; free physical = 6297 ; free virtual = 26512 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:03:29 ; elapsed = 00:03:59 . Memory (MB): peak = 3416.000 ; gain = 2084.918 ; free physical = 6297 ; free virtual = 26512 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 246 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Device 21-403] Loading part xc7vx690tffg1761-3 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0/control_sub_mdm_1_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0/control_sub_mdm_1_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0/control_sub_microblaze_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0/control_sub_microblaze_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_xlconcat' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_xlconcat' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0/control_sub_ilmb_v10_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0/control_sub_ilmb_v10_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_lmb_bram_0/control_sub_lmb_bram_0/control_sub_lmb_bram_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_lmb_bram_0/control_sub_lmb_bram_0/control_sub_lmb_bram_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_1/control_sub_xbar_1/control_sub_xbar_1_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_periph/xbar' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_1/control_sub_xbar_1/control_sub_xbar_1_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_periph/xbar' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0_in_context.xdc] for cell 'control_sub_i/dma_sub/pcie_reset_inv' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0_in_context.xdc] for cell 'control_sub_i/dma_sub/pcie_reset_inv' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_dwidth_dma_tx' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_dwidth_dma_tx' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_dwidth_dma_rx' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_dwidth_dma_rx' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0_in_context.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0_in_context.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0_in_context.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0_in_context.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_0/control_sub_xbar_0/control_sub_xbar_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/xbar' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_0/control_sub_xbar_0/control_sub_xbar_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/xbar' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0/control_sub_auto_cc_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0/control_sub_auto_cc_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:53] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:55] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:57] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:60] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:62] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:64] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:67] WARNING: [Vivado 12-180] No cells matched 'get_cells -of [filter [all_fanout -flat -endpoints_only -from [get_pins -filter NAME=~*/Q -of_objects [get_cells -hierarchical -filter {NAME =~ *rxratecounter_i*rxusrclk2_en156*}]]] {NAME =~ *WE}]'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:69] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:70] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:53] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:55] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:57] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:60] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:62] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:64] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:67] WARNING: [Vivado 12-180] No cells matched 'get_cells -of [filter [all_fanout -flat -endpoints_only -from [get_pins -filter NAME=~*/Q -of_objects [get_cells -hierarchical -filter {NAME =~ *rxratecounter_i*rxusrclk2_en156*}]]] {NAME =~ *WE}]'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:69] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:70] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:53] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:55] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:57] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:60] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:62] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:64] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:67] WARNING: [Vivado 12-180] No cells matched 'get_cells -of [filter [all_fanout -flat -endpoints_only -from [get_pins -filter NAME=~*/Q -of_objects [get_cells -hierarchical -filter {NAME =~ *rxratecounter_i*rxusrclk2_en156*}]]] {NAME =~ *WE}]'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:69] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:70] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst' WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:54] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:56] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:58] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:61] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:63] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:65] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:68] WARNING: [Vivado 12-180] No cells matched 'get_cells -of [filter [all_fanout -flat -endpoints_only -from [get_pins -filter NAME=~*/Q -of_objects [get_cells -hierarchical -filter {NAME =~ *rxratecounter_i*rxusrclk2_en156*}]]] {NAME =~ *WE}]'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:70] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:71] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0' INFO: [Timing 38-2] Deriving generated clocks write_xdc: Time (s): cpu = 00:00:52 ; elapsed = 00:00:10 . Memory (MB): peak = 8995.469 ; gain = 229.000 ; free physical = 464 ; free virtual = 20679 Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc] Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc] get_pins: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 9243.469 ; gain = 248.000 ; free physical = 463 ; free virtual = 20678 get_pins: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 9243.469 ; gain = 0.000 ; free physical = 462 ; free virtual = 20678 get_pins: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 9243.469 ; gain = 0.000 ; free physical = 460 ; free virtual = 20676 WARNING: [Vivado 12-507] No nets matched 'control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/pipe_txoutclk_out'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc:116] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc] WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/top_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc] WARNING: [Constraints 18-619] A clock with name 'xphy_refclk_p' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:92] get_pins: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 9243.469 ; gain = 0.000 ; free physical = 460 ; free virtual = 20675 WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:114] get_pins: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 9243.469 ; gain = 0.000 ; free physical = 460 ; free virtual = 20675 WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:115] get_pins: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 9243.469 ; gain = 0.000 ; free physical = 459 ; free virtual = 20674 WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:116] get_pins: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 9243.469 ; gain = 0.000 ; free physical = 460 ; free virtual = 20675 WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:117] get_pins: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 9243.469 ; gain = 0.000 ; free physical = 459 ; free virtual = 20674 WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:118] get_pins: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 9243.469 ; gain = 0.000 ; free physical = 459 ; free virtual = 20674 WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:119] get_pins: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 9243.469 ; gain = 0.000 ; free physical = 458 ; free virtual = 20673 WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:120] get_pins: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 9243.469 ; gain = 0.000 ; free physical = 458 ; free virtual = 20673 WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:121] WARNING: [Vivado 12-627] No clocks matched 'clk_250mhz_mux_x0y1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:134] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:134] get_clocks: Time (s): cpu = 00:00:40 ; elapsed = 00:00:17 . Memory (MB): peak = 10646.469 ; gain = 1403.000 ; free physical = 1604 ; free virtual = 20254 WARNING: [Vivado 12-627] No clocks matched 'clk_125mhz_x0y1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:134] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:134] WARNING: [Vivado 12-627] No clocks matched 'clk_125mhz_x0y1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:135] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:135] WARNING: [Vivado 12-627] No clocks matched 'clk_250mhz_mux_x0y1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:135] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:135] WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:137] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:137] WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:138] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:138] WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:140] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:140] WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:141] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:141] WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:143] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:143] WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:144] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:144] WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:146] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:146] WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:147] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:147] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc] WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/top_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/dont_touch.xdc] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/dont_touch.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Common 17-14] Message 'Vivado 12-3272' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Common 17-14] Message 'XPM_CDC_GRAY: TCL 1000' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/rc2oqgemebaubffc_998/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/rc2oqgemebaubffc_998/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/zmtz6gstdn71pkc38oscb260fx_746/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/zmtz6gstdn71pkc38oscb260fx_746/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xt6i6t0dtbr9k9ux4848l_2541/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xt6i6t0dtbr9k9ux4848l_2541/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xtsdogepbxcg3t8fqtbed8as0e1l_2610/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xtsdogepbxcg3t8fqtbed8as0e1l_2610/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ehndy8vbflb0gxuke3lnsjm_77/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ehndy8vbflb0gxuke3lnsjm_77/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst' WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst' WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst' WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst' WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst' WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: A total of 192 instances were transformed. BUFGCE => BUFGCTRL: 1 instances FDR => FDRE: 12 instances IOBUF => IOBUF (IBUF, OBUFT): 2 instances MUXCY_L => MUXCY: 176 instances SRL16 => SRL16E: 1 instances Constraint Validation Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 10646.469 ; gain = 0.000 ; free physical = 1519 ; free virtual = 20174 WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_clock_converter_0' at clock pin 's_axi_aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axis_dwidth_dma_rx' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axis_dwidth_dma_tx' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axis_fifo_10g_rx' at clock pin 'm_axis_aclk' is different from the actual clock period '4.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axis_fifo_10g_tx' at clock pin 'm_axis_aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/xbar' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc' at clock pin 'm_axi_aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram' at clock pin 'clka' is different from the actual clock period '10.000', this can lead to different synthesis results. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:12:34 ; elapsed = 00:11:37 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 7091 ; free virtual = 25814 --------------------------------------------------------------------------------- INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-4471] merging register 'seq_cnt_en_reg' into 'from_sys_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:377] WARNING: [Synth 8-6014] Unused sequential element seq_cnt_en_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:377] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97] INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'sume_to_sdnet' INFO: [Synth 8-5546] ROM "fd4bvmh5014u2kl4o1hmgeh9rnata_565" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "d4eyedcr7a93xmlxwchca5g_175" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "t7a7mzwjqu49xzm1_27" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "term1" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "size_0" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "term1" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "term1" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "size_0" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "term1" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "size_0" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "size_0" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "CamReg_reg[3]" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "CamReg_reg[2]" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "CamReg_reg[1]" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "CamReg_reg[0]" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'UpdateFSM_reg' in module 'realmain_dummy_table_for_netpfga_0_t_Update' INFO: [Synth 8-5544] ROM "Entry_D0" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "Count_G" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "UpdateFSM_D" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5546] ROM "wack_i" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "term10R" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_0_Editor_FifoReader' INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MUX_EditCmd_offsetEop" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_2_Editor_FifoReader' INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MUX_EditCmd_offsetEop" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MUX_EditDat_0_MASK" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MUX_EditDat_0_POS" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MUX_EditDat_1_POS" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MUX_EditDat_2_MASK" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MUX_EditDat_2_POS" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_3_Editor_FifoReader' INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MUX_EditCmd_offsetEop" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MUX_EditDat_0_MASK" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MUX_EditDat_0_POS" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MUX_EditDat_1_POS" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MUX_EditDat_2_POS" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MUX_EditDat_3_POS" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_4_Editor_FifoReader' INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Common 17-14] Message 'Synth 8-5544' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_5_Editor_FifoReader' INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_6_Editor_FifoReader' INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_7_Editor_FifoReader' INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_8_Editor_FifoReader' INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_9_Editor_FifoReader' INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_10_Editor_FifoReader' INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_11_Editor_FifoReader' INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_12_Editor_FifoReader' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'S_PROTOCOL_ADAPTER_INGRESS' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030] INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__2' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__2' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__3' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__3' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030] INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized5' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__4' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__4' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__5' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__5' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__6' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__6' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__7' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__7' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__8' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__8' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__9' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__9' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030] INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized12' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__10' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__10' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__11' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__11' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__12' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__12' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__13' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__13' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__14' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__14' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__15' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__15' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__16' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__16' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__17' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__17' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__18' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__18' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030] INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized23' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__19' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__19' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__20' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__20' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__21' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__21' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__22' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__22' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__23' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__23' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__24' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__24' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__25' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__25' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_small_fifo.v:103] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97] INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'sss_output_queues' INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[0].metadata_state_reg[0]' in module 'sss_output_queues' INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[1].metadata_state_reg[1]' in module 'sss_output_queues' INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[2].metadata_state_reg[2]' in module 'sss_output_queues' INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[3].metadata_state_reg[3]' in module 'sss_output_queues' INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[4].metadata_state_reg[4]' in module 'sss_output_queues' INFO: [Synth 8-802] inferred FSM for state register 'rs_state_reg' in module 'ten_gig_eth_mac_v15_1_6_rs_64bit' INFO: [Synth 8-5546] ROM "crc_position_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "dic_required" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "dic_returned" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "poss_ifg_count" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5545] ROM "broadcast_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25) INFO: [Synth 8-5546] ROM "control_frame" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "frame_size" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "frame_size" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "byte_count" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "byte_count" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5545] ROM "broadcast_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25) INFO: [Synth 8-5546] ROM "control_frame" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "frame_size" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "frame_size" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "byte_count" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "byte_count" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'pause_state_reg' in module 'ten_gig_eth_mac_v15_1_6_pfc_tx_cntl' INFO: [Synth 8-802] inferred FSM for state register 'legacy_state_reg' in module 'ten_gig_eth_mac_v15_1_6_pfc_tx_cntl' INFO: [Synth 8-802] inferred FSM for state register 'pause_state_reg' in module 'ten_gig_eth_mac_v15_1_6_tx_pause_cntl' INFO: [Synth 8-802] inferred FSM for state register 'rx_state_int_reg' in module 'ten_gig_eth_mac_v15_1_6_rx_fsm' INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5546] ROM "frame_max" won't be mapped to RAM because it is too sparse INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5545] ROM "broadcast_detect" won't be mapped to RAM because address size (48) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "special_addr_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'pause_state_reg' in module 'ten_gig_eth_mac_v15_1_6_rx_control' INFO: [Synth 8-802] inferred FSM for state register 'mcp1_state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_idle_delete' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_tx_pcs_fsm' INFO: [Synth 8-802] inferred FSM for state register 'mcp1_state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_block_lock_fsm' INFO: [Synth 8-802] inferred FSM for state register 'mcp1_state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_ber_mon_fsm' INFO: [Synth 8-5587] ROM size for "DecodeWord" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "DecodeWord0" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "DecodeWord1" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "DecodeWord2" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "DecodeWord3" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "DecodeWord4" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "DecodeWord5" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "DecodeWord6" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-802] inferred FSM for state register 'mcp1_state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_pcs_fsm' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_cs_ipif_access' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_drp_ipif' INFO: [Synth 8-5587] ROM size for "gt_txd_mux" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "gt_txc_mux" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5545] ROM "master_watchdog_barking" won't be mapped to RAM because address size (29) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'rx_queue__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'err_state_reg' in module 'rx_queue__xdcDup__1' INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97] INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'tx_queue__xdcDup__1' INFO: [Synth 8-5545] ROM "master_watchdog_barking" won't be mapped to RAM because address size (29) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'rx_queue__xdcDup__2' INFO: [Synth 8-802] inferred FSM for state register 'err_state_reg' in module 'rx_queue__xdcDup__2' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'tx_queue__xdcDup__2' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'rx_queue__xdcDup__3' INFO: [Synth 8-802] inferred FSM for state register 'err_state_reg' in module 'rx_queue__xdcDup__3' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'tx_queue__xdcDup__3' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'rx_queue' INFO: [Common 17-14] Message 'Synth 8-802' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FIRST | 0 | 00 WAIT | 1 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'sume_to_sdnet' INFO: [Synth 8-3971] The signal gen_wr_b.gen_word_narrow.mem_reg was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_INIT | 1010 | 0000 FSM_IDLE | 0011 | 0001 FSM_LOOK_READ2 | 1000 | 1011 FSM_LOOK_READ | 0111 | 0010 FSM_LOOK_WRITE | 0000 | 0011 FSM_CAM_DEL1 | 0001 | 1001 FSM_CAM_DEL2 | 1001 | 1010 FSM_CAM_POP | 0010 | 0111 FSM_CAM_LATCH | 1011 | 1000 FSM_ADD_READ | 0100 | 0100 FSM_CAM_PUSH | 0101 | 0110 FSM_ADD_WRITE | 0110 | 0101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'UpdateFSM_reg' using encoding 'sequential' in module 'realmain_dummy_table_for_netpfga_0_t_Update' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 0000001 | 000 FSM_INSERT_PAD | 0000010 | 100 FSM_INSERT_2 | 0000100 | 101 FSM_REMOVE_2 | 0001000 | 001 FSM_REMOVE_WAIT_EOP | 0010000 | 010 FSM_INSERT_WAIT_EOP | 0100000 | 110 FSM_INSERT_FLUSH | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_0_Editor_FifoReader' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 0000001 | 000 FSM_INSERT_PAD | 0000010 | 100 FSM_INSERT_2 | 0000100 | 101 FSM_REMOVE_2 | 0001000 | 001 FSM_REMOVE_WAIT_EOP | 0010000 | 010 FSM_INSERT_WAIT_EOP | 0100000 | 110 FSM_INSERT_FLUSH | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_2_Editor_FifoReader' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 0000001 | 000 FSM_INSERT_PAD | 0000010 | 100 FSM_INSERT_2 | 0000100 | 101 FSM_REMOVE_2 | 0001000 | 001 FSM_REMOVE_WAIT_EOP | 0010000 | 010 FSM_INSERT_WAIT_EOP | 0100000 | 110 FSM_INSERT_FLUSH | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_3_Editor_FifoReader' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 0000001 | 000 FSM_INSERT_PAD | 0000010 | 100 FSM_INSERT_2 | 0000100 | 101 FSM_REMOVE_2 | 0001000 | 001 FSM_REMOVE_WAIT_EOP | 0010000 | 010 FSM_INSERT_WAIT_EOP | 0100000 | 110 FSM_INSERT_FLUSH | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_4_Editor_FifoReader' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 0000001 | 000 FSM_INSERT_PAD | 0000010 | 100 FSM_INSERT_2 | 0000100 | 101 FSM_REMOVE_2 | 0001000 | 001 FSM_REMOVE_WAIT_EOP | 0010000 | 010 FSM_INSERT_WAIT_EOP | 0100000 | 110 FSM_INSERT_FLUSH | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_5_Editor_FifoReader' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 0000001 | 000 FSM_INSERT_PAD | 0000010 | 100 FSM_INSERT_2 | 0000100 | 101 FSM_REMOVE_2 | 0001000 | 001 FSM_REMOVE_WAIT_EOP | 0010000 | 010 FSM_INSERT_WAIT_EOP | 0100000 | 110 FSM_INSERT_FLUSH | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_6_Editor_FifoReader' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 0000001 | 000 FSM_INSERT_PAD | 0000010 | 100 FSM_INSERT_2 | 0000100 | 101 FSM_REMOVE_2 | 0001000 | 001 FSM_REMOVE_WAIT_EOP | 0010000 | 010 FSM_INSERT_WAIT_EOP | 0100000 | 110 FSM_INSERT_FLUSH | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_7_Editor_FifoReader' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 0000001 | 000 FSM_INSERT_PAD | 0000010 | 100 FSM_INSERT_2 | 0000100 | 101 FSM_REMOVE_2 | 0001000 | 001 FSM_REMOVE_WAIT_EOP | 0010000 | 010 FSM_INSERT_WAIT_EOP | 0100000 | 110 FSM_INSERT_FLUSH | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_8_Editor_FifoReader' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 0000001 | 000 FSM_INSERT_PAD | 0000010 | 100 FSM_INSERT_2 | 0000100 | 101 FSM_REMOVE_2 | 0001000 | 001 FSM_REMOVE_WAIT_EOP | 0010000 | 010 FSM_INSERT_WAIT_EOP | 0100000 | 110 FSM_INSERT_FLUSH | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_9_Editor_FifoReader' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 0000001 | 000 FSM_INSERT_PAD | 0000010 | 100 FSM_INSERT_2 | 0000100 | 101 FSM_REMOVE_2 | 0001000 | 001 FSM_REMOVE_WAIT_EOP | 0010000 | 010 FSM_INSERT_WAIT_EOP | 0100000 | 110 FSM_INSERT_FLUSH | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_10_Editor_FifoReader' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 0000001 | 000 FSM_INSERT_PAD | 0000010 | 100 FSM_INSERT_2 | 0000100 | 101 FSM_REMOVE_2 | 0001000 | 001 FSM_REMOVE_WAIT_EOP | 0010000 | 010 FSM_INSERT_WAIT_EOP | 0100000 | 110 FSM_INSERT_FLUSH | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_11_Editor_FifoReader' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 0000001 | 000 FSM_INSERT_PAD | 0000010 | 100 FSM_INSERT_2 | 0000100 | 101 FSM_REMOVE_2 | 0001000 | 001 FSM_REMOVE_WAIT_EOP | 0010000 | 010 FSM_INSERT_WAIT_EOP | 0100000 | 110 FSM_INSERT_FLUSH | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_12_Editor_FifoReader' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 00 | 001 RX_SOF_EOF | 01 | 011 RX_SOF | 10 | 010 RX_PKT | 11 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'S_PROTOCOL_ADAPTER_INGRESS' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 01 | 10 both_stages_valid | 10 | 11 stage2_valid | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized1' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 01 | 10 both_stages_valid | 10 | 11 stage2_valid | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized5' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__4' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__4' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__5' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__5' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__6' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__6' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__7' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__7' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__8' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__8' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__9' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__9' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 01 | 10 both_stages_valid | 10 | 11 stage2_valid | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized12' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__10' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__10' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__11' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__11' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__12' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__12' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__13' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__13' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__14' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__14' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__15' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__15' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__16' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__16' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__17' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__17' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__18' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__18' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 01 | 10 both_stages_valid | 10 | 11 stage2_valid | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized23' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__19' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__19' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__20' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__20' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__21' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__21' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__22' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__22' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__23' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__23' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__24' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__24' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__25' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__25' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 001 | 000 WR_PKT | 010 | 001 DROP | 100 | 010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'sss_output_queues' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WAIT_HEADER | 0 | 00 WAIT_EOP | 1 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[0].metadata_state_reg[0]' using encoding 'sequential' in module 'sss_output_queues' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WAIT_HEADER | 0 | 00 WAIT_EOP | 1 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[1].metadata_state_reg[1]' using encoding 'sequential' in module 'sss_output_queues' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WAIT_HEADER | 0 | 00 WAIT_EOP | 1 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[2].metadata_state_reg[2]' using encoding 'sequential' in module 'sss_output_queues' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WAIT_HEADER | 0 | 00 WAIT_EOP | 1 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[3].metadata_state_reg[3]' using encoding 'sequential' in module 'sss_output_queues' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WAIT_HEADER | 0 | 00 WAIT_EOP | 1 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[4].metadata_state_reg[4]' using encoding 'sequential' in module 'sss_output_queues' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- INIT | 00 | 00 COUNT | 01 | 01 FAULT | 10 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'rs_state_reg' using encoding 'sequential' in module 'ten_gig_eth_mac_v15_1_6_rs_64bit' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 0001 | 000 REQ | 0010 | 001 WAIT | 0100 | 010 COUNT | 1000 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'legacy_state_reg' using encoding 'one-hot' in module 'ten_gig_eth_mac_v15_1_6_pfc_tx_cntl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- P_IDLE | 00 | 00 P_REQ | 01 | 01 P_WAIT | 10 | 10 P_HOLD | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'pause_state_reg' using encoding 'sequential' in module 'ten_gig_eth_mac_v15_1_6_pfc_tx_cntl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 001 | 00 REQUEST | 010 | 01 SEND | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'pause_state_reg' using encoding 'one-hot' in module 'ten_gig_eth_mac_v15_1_6_tx_pause_cntl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 000 CHECK_MIN | 001 | 001 DATA | 010 | 010 BAD_STRIP | 011 | 011 VALIDATE | 100 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'rx_state_int_reg' using encoding 'sequential' in module 'ten_gig_eth_mac_v15_1_6_rx_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 00001 | 000 LEGACY | 00010 | 001 PFC | 00100 | 100 PFCQ3_Q6 | 01000 | 101 PFCQ7 | 10000 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'pause_state_reg' using encoding 'one-hot' in module 'ten_gig_eth_mac_v15_1_6_rx_control' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- STRAIGHT | 000 | 000 DELETE3 | 001 | 010 DELETE1 | 010 | 001 TWISTED | 011 | 100 POSSIBLE_DELETE4 | 100 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'mcp1_state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_idle_delete' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- TX_INIT | 000 | 000 TX_E | 001 | 100 TX_C | 010 | 001 TX_D | 011 | 010 TX_T | 100 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_tx_pcs_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- LOCK_INIT | 00 | 00 RESET_CNT | 01 | 01 TEST_VALID_INVALID_SH | 10 | 10 SLIP | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'mcp1_state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_block_lock_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- BER_MT_INIT | 000 | 000 START_TIMER | 001 | 001 BER_TEST_SH | 010 | 010 BER_BAD_SH | 011 | 011 HI_BER | 100 | 100 GOOD_BER | 101 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'mcp1_state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_ber_mon_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RX_INIT | 000 | 000 RX_E | 001 | 100 RX_T | 010 | 011 RX_C | 011 | 001 RX_D | 100 | 010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'mcp1_state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_pcs_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 00 | 000 RDREQ1 | 01 | 001 RDPENDING1 | 10 | 010 RDRESP1 | 11 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_cs_ipif_access' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 00 | 00 REQ | 01 | 01 GNT | 10 | 10 GNT1 | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_drp_ipif' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ERR_BUBBLE | 00 | 010 ERR_IDLE | 01 | 000 ERR_WAIT | 10 | 001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'err_state_reg' using encoding 'sequential' in module 'rx_queue__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 00 | 0000 WAIT_FOR_EOP | 01 | 0001 BUBBLE | 10 | 0011 DROP | 11 | 0010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'rx_queue__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 0 | 000 SEND_PKT | 1 | 001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'tx_queue__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ERR_BUBBLE | 00 | 010 ERR_IDLE | 01 | 000 ERR_WAIT | 10 | 001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'err_state_reg' using encoding 'sequential' in module 'rx_queue__xdcDup__2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 00 | 0000 WAIT_FOR_EOP | 01 | 0001 BUBBLE | 10 | 0011 DROP | 11 | 0010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'rx_queue__xdcDup__2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 0 | 000 SEND_PKT | 1 | 001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'tx_queue__xdcDup__2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ERR_BUBBLE | 00 | 010 ERR_IDLE | 01 | 000 ERR_WAIT | 10 | 001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'err_state_reg' using encoding 'sequential' in module 'rx_queue__xdcDup__3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 00 | 0000 WAIT_FOR_EOP | 01 | 0001 BUBBLE | 10 | 0011 DROP | 11 | 0010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'rx_queue__xdcDup__3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 0 | 000 SEND_PKT | 1 | 001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'tx_queue__xdcDup__3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ERR_BUBBLE | 00 | 010 ERR_IDLE | 01 | 000 ERR_WAIT | 10 | 001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'err_state_reg' using encoding 'sequential' in module 'rx_queue' INFO: [Common 17-14] Message 'Synth 8-3354' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 00 | 0000 WAIT_FOR_EOP | 01 | 0001 BUBBLE | 10 | 0011 DROP | 11 | 0010 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 0 | 000 SEND_PKT | 1 | 001 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- wait_wraddr | 00 | 00 reg_wraddr | 01 | 01 os_wr | 10 | 10 wr_mem | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:14:31 ; elapsed = 00:13:42 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 3133 ; free virtual = 21925 --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE Report RTL Partitions: +------+------------------------------------------------------------------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+------------------------------------------------------------------------------+------------+----------+ |1 |clk_wiz_ip_clk_wiz__GC0 | 1| 13| |2 |TopParser_t_EngineStage_0__GB0 | 1| 26012| |3 |TopParser_t_EngineStage_0__GB1 | 1| 15349| |4 |TopParser_t_EngineStage_0__GB2 | 1| 15267| |5 |TopParser_t_EngineStage_0__GB3 | 1| 27258| |6 |TopParser_t_EngineStage_0__GB4 | 1| 18304| |7 |TopParser_t_EngineStage_0__GB5 | 1| 11824| |8 |TopParser_t_EngineStage_1__GB0 | 1| 23607| |9 |TopParser_t_EngineStage_1__GB1 | 1| 16471| |10 |TopParser_t_EngineStage_1__GB2 | 1| 5302| |11 |TopParser_t_EngineStage_1__GB3 | 1| 9526| |12 |TopParser_t_EngineStage_1__GB4 | 1| 14700| |13 |TopParser_t_EngineStage_1__GB5 | 1| 25325| |14 |TopParser_t_EngineStage_1__GB6 | 1| 21551| |15 |TopParser_t_EngineStage_1__GB7 | 1| 31767| |16 |TopParser_t_EngineStage_2__GB0 | 1| 30294| |17 |TopParser_t_EngineStage_2__GB1 | 1| 17669| |18 |TopParser_t_EngineStage_2__GB2 | 1| 6205| |19 |TopParser_t_EngineStage_2__GB3 | 1| 29213| |20 |TopParser_t_EngineStage_2__GB4 | 1| 8959| |21 |TopParser_t_EngineStage_2__GB5 | 1| 32370| |22 |TopParser_t_EngineStage_2__GB6 | 1| 11224| |23 |TopParser_t_EngineStage_2__GB7 | 1| 11219| |24 |TopParser_t_EngineStage_2__GB8 | 1| 30908| |25 |TopParser_t_EngineStage_3__GB0 | 1| 31388| |26 |TopParser_t_EngineStage_3__GB1 | 1| 25458| |27 |TopParser_t_EngineStage_3__GB2 | 1| 27482| |28 |TopParser_t_EngineStage_3__GB3 | 1| 16357| |29 |TopParser_t_EngineStage_3__GB4 | 1| 10571| |30 |TopParser_t_EngineStage_4__GB0 | 1| 21042| |31 |TopParser_t_EngineStage_4__GB1 | 1| 23417| |32 |TopParser_t_EngineStage_4__GB2 | 1| 27263| |33 |TopParser_t_EngineStage_4__GB3 | 1| 17468| |34 |TopParser_t_EngineStage_5__GB0 | 1| 39552| |35 |TopParser_t_EngineStage_5__GB1 | 1| 27750| |36 |TopParser_t_EngineStage_5__GB2 | 1| 21906| |37 |TopParser_t_Engine__GC0 | 1| 4223| |38 |TopParser_t__GC0 | 1| 21| |39 |TopPipe_lvl_0_t_EngineStage_4__GB0 | 1| 29311| |40 |TopPipe_lvl_0_t_EngineStage_4__GB1 | 1| 16294| |41 |TopPipe_lvl_0_t_EngineStage_5__GB0 | 1| 32431| |42 |TopPipe_lvl_0_t_EngineStage_5__GB1 | 1| 19098| |43 |TopPipe_lvl_0_t_realmain_delta_prepare_sec_compute_user_metadata_v6sum__GB0 | 1| 26870| |44 |TopPipe_lvl_0_t_realmain_delta_prepare_sec_compute_user_metadata_v6sum__GB1 | 1| 5625| |45 |TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB0 | 1| 30317| |46 |TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB1 | 1| 6316| |47 |TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 | 1| 28060| |48 |TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB3 | 1| 913| |49 |TopPipe_lvl_0_t_EngineStage_6__GCB0 | 1| 31587| |50 |TopPipe_lvl_0_t_EngineStage_6__GCB1 | 1| 27497| |51 |TopPipe_lvl_0_t_EngineStage_6__GCB2 | 1| 16836| |52 |TopPipe_lvl_0_t_EngineStage_6__GCB3 | 1| 27207| |53 |TopPipe_lvl_0_t_EngineStage_6__GCB4 | 1| 27204| |54 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec_compute_user_metadata_v6sum__GB0 | 1| 26870| |55 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec_compute_user_metadata_v6sum__GB1 | 1| 5625| |56 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB0 | 1| 30317| |57 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB1 | 1| 6316| |58 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 | 1| 28060| |59 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB3 | 1| 913| |60 |TopPipe_lvl_0_t_EngineStage_7__GCB0 | 1| 31110| |61 |TopPipe_lvl_0_t_EngineStage_7__GCB1 | 1| 9821| |62 |TopPipe_lvl_0_t_EngineStage_7__GCB2 | 1| 19998| |63 |TopPipe_lvl_0_t_EngineStage_7__GCB3 | 1| 14815| |64 |TopPipe_lvl_0_t_EngineStage_7__GCB4 | 1| 29467| |65 |TopPipe_lvl_0_t_EngineStage_7__GCB5 | 1| 2453| |66 |TopPipe_lvl_0_t_EngineStage_7__GCB6 | 1| 273| |67 |TopPipe_lvl_0_t_EngineStage_7__GCB7 | 1| 27693| |68 |TopPipe_lvl_0_t_EngineStage_8__GB0 | 1| 26665| |69 |TopPipe_lvl_0_t_EngineStage_8__GB1 | 1| 26454| |70 |TopPipe_lvl_0_t_EngineStage_8__GB2 | 1| 65| |71 |TopPipe_lvl_0_t_EngineStage_8__GB3 | 1| 13497| |72 |TopPipe_lvl_0_t_EngineStage_9__GB0 | 1| 35254| |73 |TopPipe_lvl_0_t_EngineStage_9__GB1 | 1| 17728| |74 |TopPipe_lvl_0_t_EngineStage_10__GB0 | 1| 32884| |75 |TopPipe_lvl_0_t_EngineStage_10__GB1 | 1| 2845| |76 |TopPipe_lvl_0_t_EngineStage_10__GB2 | 1| 9345| |77 |TopPipe_lvl_0_t_EngineStage_11__GB0 | 1| 18244| |78 |TopPipe_lvl_0_t_EngineStage_11__GB1 | 1| 17445| |79 |TopPipe_lvl_0_t_EngineStage_11__GB2 | 1| 2871| |80 |TopPipe_lvl_0_t_EngineStage_11__GB3 | 1| 20368| |81 |TopPipe_lvl_0_t_EngineStage_12__GB0 | 1| 35255| |82 |TopPipe_lvl_0_t_EngineStage_12__GB1 | 1| 17728| |83 |TopPipe_lvl_0_t_EngineStage_13__GB0 | 1| 23413| |84 |TopPipe_lvl_0_t_EngineStage_13__GB1 | 1| 18278| |85 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec_compute_user_metadata_v6sum__GB0 | 1| 26870| |86 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec_compute_user_metadata_v6sum__GB1 | 1| 5625| |87 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB0 | 1| 30317| |88 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB1 | 1| 6316| |89 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 | 1| 28060| |90 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB3 | 1| 913| |91 |TopPipe_lvl_0_t_EngineStage_15__GCB0 | 1| 32358| |92 |TopPipe_lvl_0_t_EngineStage_15__GCB1 | 1| 27419| |93 |TopPipe_lvl_0_t_EngineStage_15__GCB2 | 1| 18239| |94 |TopPipe_lvl_0_t_EngineStage_15__GCB3 | 1| 27629| |95 |TopPipe_lvl_0_t_EngineStage_15__GCB4 | 1| 27196| |96 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec_compute_user_metadata_v6sum__GB0 | 1| 26870| |97 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec_compute_user_metadata_v6sum__GB1 | 1| 5625| |98 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB0 | 1| 30317| |99 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB1 | 1| 6316| |100 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 | 1| 28060| |101 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB3 | 1| 913| |102 |TopPipe_lvl_0_t_EngineStage_16__GCB0 | 1| 23370| |103 |TopPipe_lvl_0_t_EngineStage_16__GCB1 | 1| 19657| |104 |TopPipe_lvl_0_t_EngineStage_16__GCB2 | 1| 28060| |105 |TopPipe_lvl_0_t_EngineStage_16__GCB3 | 1| 30069| |106 |TopPipe_lvl_0_t_EngineStage_16__GCB4 | 1| 28773| |107 |TopPipe_lvl_0_t_EngineStage_16__GCB5 | 1| 273| |108 |TopPipe_lvl_0_t_EngineStage_17__GB0 | 1| 23377| |109 |TopPipe_lvl_0_t_EngineStage_17__GB1 | 1| 21048| |110 |TopPipe_lvl_0_t_EngineStage_17__GB2 | 1| 65| |111 |TopPipe_lvl_0_t_EngineStage_17__GB3 | 1| 11123| |112 |TopPipe_lvl_0_t_EngineStage_18__GB0 | 1| 35259| |113 |TopPipe_lvl_0_t_EngineStage_18__GB1 | 1| 17918| |114 |TopPipe_lvl_0_t_EngineStage_19__GB0 | 1| 33565| |115 |TopPipe_lvl_0_t_EngineStage_19__GB1 | 1| 8783| |116 |TopPipe_lvl_0_t_EngineStage_20__GB0 | 1| 33678| |117 |TopPipe_lvl_0_t_EngineStage_20__GB1 | 1| 9028| |118 |TopPipe_lvl_0_t_EngineStage_20__GB2 | 1| 65| |119 |TopPipe_lvl_0_t_EngineStage_20__GB3 | 1| 24447| |120 |TopPipe_lvl_0_t_EngineStage_21__GB0 | 1| 18239| |121 |TopPipe_lvl_0_t_EngineStage_21__GB1 | 1| 16934| |122 |TopPipe_lvl_0_t_EngineStage_21__GB2 | 1| 2871| |123 |TopPipe_lvl_0_t_EngineStage_21__GB3 | 1| 20349| |124 |TopPipe_lvl_0_t_EngineStage_22 | 1| 39140| |125 |TopPipe_lvl_0_t_EngineStage_14 | 1| 30752| |126 |TopPipe_lvl_0_t_EngineStage_23 | 1| 27679| |127 |TopPipe_lvl_0_t_Engine__GCB3 | 1| 33388| |128 |TopPipe_lvl_0_t_Engine__GCB4 | 1| 27790| |129 |TopPipe_lvl_0_t_Engine__GCB5 | 1| 22306| |130 |TopPipe_lvl_0_t_Engine__GCB6 | 1| 33417| |131 |TopDeparser_t_EngineStage_0__GB0 | 1| 33018| |132 |TopDeparser_t_EngineStage_0__GB1 | 1| 6497| |133 |TopDeparser_t_EngineStage_0__GB2 | 1| 18726| |134 |reg__7352 | 1| 1403| |135 |TopDeparser_t_EngineStage_2_Editor__GB0 | 1| 29504| |136 |TopDeparser_t_EngineStage_2_Editor__GB1 | 1| 12589| |137 |TopDeparser_t_EngineStage_2__GC0 | 1| 29596| |138 |TopDeparser_t_EngineStage_3_Editor__GB0 | 1| 28865| |139 |TopDeparser_t_EngineStage_3_Editor__GB1 | 1| 8687| |140 |TopDeparser_t_EngineStage_3__GC0 | 1| 29196| |141 |TopDeparser_t_EngineStage_4_Editor_TupleMerge__GB0 | 1| 27336| |142 |TopDeparser_t_EngineStage_4_Editor_TupleMerge__GB1 | 1| 15344| |143 |TopDeparser_t_EngineStage_4_Editor_TupleMerge__GB2 | 1| 11673| |144 |TopDeparser_t_EngineStage_4_Editor__GC0 | 1| 33501| |145 |TopDeparser_t_EngineStage_4__GC0 | 1| 30106| |146 |TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple | 16| 5382| |147 |TopDeparser_t_EngineStage_5_Editor_TupleMerge__GC0 | 1| 5846| |148 |TopDeparser_t_EngineStage_5_Editor__GCB0 | 1| 32387| |149 |TopDeparser_t_EngineStage_5_Editor__GCB1 | 1| 12864| |150 |TopDeparser_t_EngineStage_5__GC0 | 1| 31184| |151 |TopDeparser_t_EngineStage_6_Editor_TupleMerge__GB0 | 1| 26000| |152 |TopDeparser_t_EngineStage_6_Editor_TupleMerge__GB1 | 1| 16308| |153 |TopDeparser_t_EngineStage_6_Editor_TupleMerge__GB2 | 1| 11101| |154 |TopDeparser_t_EngineStage_6_Editor__GC0 | 1| 34270| |155 |TopDeparser_t_EngineStage_6__GC0 | 1| 30501| |156 |TopDeparser_t_EngineStage_7_Editor_TupleMerge__GB0 | 1| 34370| |157 |TopDeparser_t_EngineStage_7_Editor_TupleMerge__GB1 | 1| 21098| |158 |TopDeparser_t_EngineStage_7_Editor_TupleMerge__GB2 | 1| 15509| |159 |TopDeparser_t_EngineStage_7_Editor__GC0 | 1| 33629| |160 |TopDeparser_t_EngineStage_7__GC0 | 1| 30267| |161 |TopDeparser_t_EngineStage_8_Editor__GB0 | 1| 28865| |162 |TopDeparser_t_EngineStage_8_Editor__GB1 | 1| 8687| |163 |TopDeparser_t_EngineStage_8__GC0 | 1| 29197| |164 |TopDeparser_t_EngineStage_9__GB0 | 1| 35383| |165 |TopDeparser_t_EngineStage_9__GB1 | 1| 2898| |166 |TopDeparser_t_EngineStage_9__GB2 | 1| 22922| |167 |reg__11231 | 1| 1403| |168 |TopDeparser_t_EngineStage_10__GB0 | 1| 35383| |169 |TopDeparser_t_EngineStage_10__GB1 | 1| 2898| |170 |TopDeparser_t_EngineStage_10__GB2 | 1| 22922| |171 |reg__11629 | 1| 1403| |172 |TopDeparser_t_EngineStage_11_Editor__GB0 | 1| 33862| |173 |TopDeparser_t_EngineStage_11_Editor__GB1 | 1| 30087| |174 |TopDeparser_t_EngineStage_11__GC0 | 1| 30240| |175 |TopDeparser_t_EngineStage_12_Editor__GB0 | 1| 28841| |176 |TopDeparser_t_EngineStage_12_Editor__GB1 | 1| 8819| |177 |TopDeparser_t_EngineStage_12__GC0 | 1| 29314| |178 |TopDeparser_t_Engine__GC0 | 1| 34799| |179 |TopDeparser_t__GC0 | 1| 23| |180 |SimpleSumeSwitch__GCB0 | 1| 30860| |181 |S_SYNCER_for_TopDeparser | 1| 6865| |182 |SimpleSumeSwitch__GCB2 | 1| 8991| |183 |SimpleSumeSwitch__GCB3 | 1| 13420| |184 |nf_sume_sdnet__GC0 | 1| 11| |185 |nf_datapath__GCB0 | 1| 23530| |186 |nf_datapath__GCB1 | 1| 10473| |187 |bd_a1aa_xpcs_0_shared_clock_and_reset__GC0 | 1| 53| |188 |ten_gig_eth_pcs_pma_v6_0_13 | 2| 14863| |189 |bd_a1aa_xpcs_0_block__GC0 | 1| 899| |190 |bd_a1aa_xpcs_0_support__GC0 | 1| 2| |191 |bd_a1aa__GC0 | 1| 15327| |192 |nf_10g_interface_shared_block__GC0 | 1| 11027| |193 |nf_10g_interface_shared__GC0 | 1| 2767| |194 |bd_7ad4_xmac_0_block | 3| 15327| |195 |bd_7ad4_xpcs_0_block__GC0 | 1| 899| |196 |nf_10g_interface_block__xdcDup__1__GC0 | 1| 11027| |197 |nf_10g_interface__xdcDup__1__GC0 | 1| 2758| |198 |nf_10g_interface_block__xdcDup__2__GC0 | 1| 11027| |199 |nf_10g_interface__xdcDup__2__GC0 | 1| 2758| |200 |nf_10g_interface_block__GC0 | 1| 11027| |201 |nf_10g_interface__GC0 | 1| 2758| |202 |top__GC0 | 1| 8070| +------+------------------------------------------------------------------------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 3600 (col length:200) BRAMs: 2940 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element wrpp2_inst/count_value_i_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1720] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.next_state_d1_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_d1_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.ge_fwft_d1_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element wrpp2_inst/count_value_i_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1720] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element wrpp2_inst/count_value_i_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1720] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.next_state_d1_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_d1_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.ge_fwft_d1_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element wrpp2_inst/count_value_i_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1720] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element wrpp2_inst/count_value_i_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1720] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.next_state_d1_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_d1_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.ge_fwft_d1_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element wrpp2_inst/count_value_i_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1720] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766] INFO: [Synth 8-5545] ROM "master_watchdog_barking" won't be mapped to RAM because address size (29) is larger than maximum supported(25) WARNING: [Synth 8-6014] Unused sequential element nf_10g_interface_shared_cpu_regs_inst/resetn_soft_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_cpu_regs.v:155] INFO: [Synth 8-5545] ROM "master_watchdog_barking" won't be mapped to RAM because address size (29) is larger than maximum supported(25) WARNING: [Synth 8-6014] Unused sequential element nf_10g_interface_cpu_regs_inst/resetn_soft_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs.v:155] WARNING: [Synth 8-6014] Unused sequential element nf_10g_interface_cpu_regs_inst/resetn_soft_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs.v:155] WARNING: [Synth 8-6014] Unused sequential element nf_10g_interface_cpu_regs_inst/resetn_soft_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs.v:155] INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\ErrorCheck_inst/validBits_i1_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\ErrorCheck_inst/validBits_i1_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\ErrorCheck_inst/validBits_i1_reg[2] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\section_RealParser_ipv6_inst/TopParser_fl_hdr_1_ipv6_isValid_1_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\section_RealParser_ipv6_inst/control_increment_offset_1_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\section_RealParser_ipv6_inst/control_increment_offset_1_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\section_RealParser_ipv6_inst/control_increment_offset_1_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\section_RealParser_ipv6_inst/control_increment_offset_1_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\section_RealParser_ipv6_inst/control_increment_offset_1_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\section_RealParser_ipv6_inst/control_increment_offset_1_reg[5] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\section_RealParser_ipv6_inst/control_increment_offset_1_reg[6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\section_RealParser_ipv6_inst/control_increment_offset_1_reg[7] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\section_RealParser_ipv6_inst/control_increment_offset_1_reg[8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\section_RealParser_ipv6_inst/control_increment_offset_1_reg[9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\section_RealParser_ipv6_inst/control_increment_offset_1_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_1i_10/\section_RealParser_ipv6_inst/compute_control_nextSection_inst/flag1_reg ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/TopParser_fl_hdr_1_tcp_isValid_1_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_nextSection_1_reg[0] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_nextSection_1_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_nextSection_1_reg[2] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_nextSection_1_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_nextSection_1_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_nextSection_1_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_increment_offset_1_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_increment_offset_1_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_increment_offset_1_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_increment_offset_1_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_increment_offset_1_reg[4] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_increment_offset_1_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_increment_offset_1_reg[6] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_increment_offset_1_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_increment_offset_1_reg[8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_increment_offset_1_reg[9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_increment_offset_1_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /stage_2i_19/\section_RealParser_tcp_inst/control_nextDone_1_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[16] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[17] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[18] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[19] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[20] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[22] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[23] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[24] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[25] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[26] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[27] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[28] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[30] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[16] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[17] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[18] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[19] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[20] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[22] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[23] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[24] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[25] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[26] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[27] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[28] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[30] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[32] ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[0]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[0]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[1]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[1]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[2]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[2]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[3]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[3]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[4]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[4]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[5]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[5]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[6]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[6]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[7]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[7]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[8]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[8]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[9]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[9]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[10]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[10]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[11]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[11]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[12]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[12]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[13]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[13]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[14]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[14]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[15]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[15]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[16]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[16]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[17]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[17]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[18]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[18]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[19]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[19]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[20]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[20]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[21]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[21]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[22]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[22]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[23]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[23]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[24]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[24]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[25]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[25]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[26]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[26]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[27]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[27]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[28]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[28]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[29]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[29]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[30]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[30]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[31]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[31]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[32]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[32]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[33]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[33]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[34]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[34]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[35]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[35]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[36]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[36]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[37]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[37]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[38]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[38]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[39]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[39]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[40]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[40]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[41]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[41]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[42]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[42]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[43]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[43]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[44]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[44]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[45]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[45]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[46]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[46]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[47]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[47]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[48]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[48]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[49]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[49]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[50]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[50]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[51]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[51]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[52]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[52]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[53]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[53]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[54]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[54]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[55]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[55]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[56]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[56]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[57]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[57]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[58]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[58]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[59]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[59]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[60]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[60]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[61]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[61]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[62]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[62]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[63]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[63]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[64]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[64]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[65]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[65]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[66]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[66]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[67]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[67]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[68]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[68]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[69]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[69]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[70]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[70]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[71]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[71]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[72]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[72]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[73]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[73]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[74]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[74]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[75]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[75]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[76]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[76]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[77]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[77]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[78]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[78]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[79]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[79]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[80]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[80]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[81]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[81]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[82]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[82]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[83]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[83]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[84]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[84]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[85]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[85]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[86]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[86]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[87]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[87]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[88]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[88]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[89]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[89]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[90]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[90]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[91]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[91]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[92]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[92]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[93]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[93]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[94]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[94]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[95]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[95]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[96]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[96]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[97]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[97]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[98]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[98]' INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/TopPipe_fl_1_reg[99]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20i_82/section_act_17_sec_inst/TopPipe_fl_1_reg[99]' INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[47]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[46]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[45]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[44]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[43]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[42]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[41]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[40]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[39]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[38]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[37]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[36]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[35]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[34]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[33]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[32]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[31]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[30]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[29]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[28]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[27]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[26]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[25]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[24]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[23]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[22]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[21]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[20]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[19]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[18]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[17]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[16]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[15]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[14]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[13]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[12]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[11]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[10]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[9]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[8]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[7]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[6]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[5]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[4]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[3]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[2]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[1]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i4_reg[0]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/shift_i4_reg[3]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/shift_i4_reg[2]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/shift_i4_reg[1]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/shift_i4_reg[0]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[78]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[77]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[76]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[75]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[74]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[73]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[72]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[71]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[70]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[69]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[68]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[67]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[66]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[65]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldData_0/data_i6_reg[64]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[47]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[46]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[45]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[44]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[43]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[42]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[41]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[40]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[39]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[38]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[37]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[36]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[35]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[34]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[33]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[32]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[31]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[30]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[29]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[28]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[27]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[26]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[25]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[24]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[23]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[22]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[21]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[20]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[19]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[18]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[17]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[16]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. WARNING: [Synth 8-3332] Sequential element (shiftFieldMask_0/data_i4_reg[15]) is unused and will be removed from module TopDeparser_t_EngineStage_3_Editor_TupleMerge. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3936] Found unconnected internal register 'section_start_inst/compute_control_nextSection_inst/term1_reg' and it is trimmed from '16' to '6' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:5219] WARNING: [Synth 8-3936] Found unconnected internal register 'section_RealParser_ipv4_inst/compute_control_nextSection_inst/term1_reg' and it is trimmed from '8' to '6' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:8854] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp6_inst/control_increment_offsetEop_1_reg[0:0]' into 'section_RealParser_icmp6_inst/compute_control_nextSection_inst/flag1_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:13504] INFO: [Synth 8-4471] merging register 'section_RealParser_udp_inst/control_1_reg[22:0]' into 'section_RealParser_icmp6_inst/control_1_reg[22:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16565] INFO: [Synth 8-4471] merging register 'section_RealParser_udp_inst/control_nextDone_1_reg[0:0]' into 'section_RealParser_icmp6_inst/compute_control_nextSection_inst/flag1_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16545] INFO: [Synth 8-4471] merging register 'section_RealParser_udp_inst/control_increment_offsetEop_1_reg[0:0]' into 'section_RealParser_icmp6_inst/compute_control_nextSection_inst/flag1_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16534] INFO: [Synth 8-4471] merging register 'section_RealParser_udp_inst/p_1_reg[1402:0]' into 'section_RealParser_icmp6_inst/p_1_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16569] INFO: [Synth 8-4471] merging register 'section_RealParser_udp_inst/user_metadata_1_reg[159:0]' into 'section_RealParser_icmp6_inst/user_metadata_1_reg[159:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16573] INFO: [Synth 8-4471] merging register 'section_RealParser_udp_inst/digest_data_1_reg[255:0]' into 'section_RealParser_icmp6_inst/digest_data_1_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16577] INFO: [Synth 8-4471] merging register 'section_RealParser_udp_inst/sume_metadata_1_reg[127:0]' into 'section_RealParser_icmp6_inst/sume_metadata_1_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16581] INFO: [Synth 8-4471] merging register 'section_RealParser_udp_inst/TopParser_fl_1_reg[1946:0]' into 'section_RealParser_icmp6_inst/TopParser_fl_1_reg[1946:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16585] INFO: [Synth 8-4471] merging register 'section_RealParser_udp_inst/TopParser_fl_hdr_1_udp_checksum_1_reg[15:0]' into 'section_RealParser_icmp6_inst/TopParser_fl_hdr_1_icmp6_checksum_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16561] INFO: [Synth 8-4471] merging register 'section_RealParser_udp_inst/TopParser_fl_hdr_1_udp_isValid_1_reg[0:0]' into 'section_RealParser_icmp6_inst/TopParser_fl_hdr_1_icmp6_isValid_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16553] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/compute_TopParser_extracts_size_inst/term1_reg[31:0]' into 'section_RealParser_icmp6_inst/compute_TopParser_extracts_size_inst/term1_reg[31:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17899] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/control_1_reg[22:0]' into 'section_RealParser_icmp6_inst/control_1_reg[22:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17480] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/control_nextSection_1_reg[5:0]' into 'section_RealParser_udp_inst/control_nextSection_1_reg[5:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17445] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/control_nextDone_1_reg[0:0]' into 'section_RealParser_icmp6_inst/compute_control_nextSection_inst/flag1_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17464] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/control_increment_offsetEop_1_reg[0:0]' into 'section_RealParser_icmp6_inst/compute_control_nextSection_inst/flag1_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17449] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/control_increment_offset_1_reg[10:0]' into 'section_RealParser_icmp6_inst/control_increment_offset_1_reg[10:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17472] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/p_1_reg[1402:0]' into 'section_RealParser_icmp6_inst/p_1_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17484] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/user_metadata_1_reg[159:0]' into 'section_RealParser_icmp6_inst/user_metadata_1_reg[159:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17488] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/digest_data_1_reg[255:0]' into 'section_RealParser_icmp6_inst/digest_data_1_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17492] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/sume_metadata_1_reg[127:0]' into 'section_RealParser_icmp6_inst/sume_metadata_1_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17496] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/TopParser_fl_1_reg[1946:0]' into 'section_RealParser_icmp6_inst/TopParser_fl_1_reg[1946:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17500] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/TopParser_fl_hdr_1_icmp_checksum_1_reg[15:0]' into 'section_RealParser_icmp6_inst/TopParser_fl_hdr_1_icmp6_checksum_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17453] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/TopParser_fl_hdr_1_icmp_code_1_reg[7:0]' into 'section_RealParser_icmp6_inst/TopParser_fl_hdr_1_icmp6_code_1_reg[7:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17460] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/TopParser_fl_hdr_1_icmp_type_1_reg[7:0]' into 'section_RealParser_icmp6_inst/TopParser_fl_hdr_1_icmp6_type_1_reg[7:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17476] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp_inst/TopParser_fl_hdr_1_icmp_isValid_1_reg[0:0]' into 'section_RealParser_icmp6_inst/TopParser_fl_hdr_1_icmp6_isValid_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17468] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp6_inst/control_increment_offsetEop_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:13504] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_udp_inst/control_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16565] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_udp_inst/control_nextDone_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16545] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_udp_inst/control_increment_offsetEop_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16534] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_udp_inst/p_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16569] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_udp_inst/user_metadata_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16573] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_udp_inst/digest_data_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16577] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_udp_inst/sume_metadata_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16581] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_udp_inst/TopParser_fl_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16585] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_udp_inst/TopParser_fl_hdr_1_udp_checksum_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16561] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_udp_inst/TopParser_fl_hdr_1_udp_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:16553] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/compute_TopParser_extracts_size_inst/term1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17899] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/control_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17480] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/control_nextSection_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17445] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/control_nextDone_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17464] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/control_increment_offsetEop_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17449] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/control_increment_offset_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17472] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/p_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17484] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/user_metadata_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17488] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/digest_data_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17492] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/sume_metadata_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17496] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/TopParser_fl_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17500] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/TopParser_fl_hdr_1_icmp_checksum_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17453] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/TopParser_fl_hdr_1_icmp_code_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17460] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/TopParser_fl_hdr_1_icmp_type_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17476] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp_inst/TopParser_fl_hdr_1_icmp_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:17468] INFO: [Synth 8-4471] merging register 'TopParser_fl_3_reg[1946:0]' into 'section_reject_inst/TopParser_fl_1_reg[1946:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:12900] INFO: [Synth 8-4471] merging register 'TopParser_fl_4_reg[1946:0]' into 'reject_TopParser_fl_4_reg[1946:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:12901] INFO: [Synth 8-4471] merging register 'TopParser_fl_5_reg[1946:0]' into 'reject_TopParser_fl_5_reg[1946:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:12902] INFO: [Synth 8-4471] merging register 'TopParser_fl_6_reg[1946:0]' into 'reject_TopParser_fl_6_reg[1946:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:12903] WARNING: [Synth 8-6014] Unused sequential element TopParser_fl_5_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:12902] WARNING: [Synth 8-6014] Unused sequential element TopParser_fl_6_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:12903] INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-4471] merging register 'section_RealParser_icmp6_neighbor_solicitation_inst/control_increment_offsetEop_1_reg[0:0]' into 'section_RealParser_icmp6_neighbor_solicitation_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:19564] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp6_neighbor_solicitation_inst/control_increment_offsetEop_2_reg[0:0]' into 'section_RealParser_icmp6_neighbor_solicitation_inst/control_nextDone_2_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:19565] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp6_neighbor_solicitation_inst/TopParser_fl_hdr_1_icmp6_na_ns_isValid_1_reg[0:0]' into 'section_RealParser_icmp6_neighbor_solicitation_inst/TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:19569] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp6_neighbor_solicitation_inst/TopParser_fl_hdr_1_icmp6_na_ns_isValid_2_reg[0:0]' into 'section_RealParser_icmp6_neighbor_solicitation_inst/TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid_2_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:19570] INFO: [Synth 8-4471] merging register 'section_RealParser_icmp6_neighbor_solicitation_inst/control_1_reg[22:0]' into 'section_reject_inst/control_1_reg[22:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:19607] INFO: [Synth 8-4471] merging register 'section_reject_inst/control_increment_offsetEop_1_reg[0:0]' into 'section_RealParser_icmp6_neighbor_solicitation_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:5452] INFO: [Synth 8-4471] merging register 'section_reject_inst/p_1_reg[1402:0]' into 'section_RealParser_icmp6_neighbor_solicitation_inst/p_1_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:5467] INFO: [Synth 8-4471] merging register 'section_reject_inst/user_metadata_1_reg[159:0]' into 'section_RealParser_icmp6_neighbor_solicitation_inst/user_metadata_1_reg[159:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:5471] INFO: [Synth 8-4471] merging register 'section_reject_inst/digest_data_1_reg[255:0]' into 'section_RealParser_icmp6_neighbor_solicitation_inst/digest_data_1_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:5475] INFO: [Synth 8-4471] merging register 'section_reject_inst/sume_metadata_1_reg[127:0]' into 'section_RealParser_icmp6_neighbor_solicitation_inst/sume_metadata_1_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:5479] INFO: [Synth 8-4471] merging register 'section_reject_inst/TopParser_fl_1_reg[1946:0]' into 'section_RealParser_icmp6_neighbor_solicitation_inst/TopParser_fl_1_reg[1946:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:5483] INFO: [Synth 8-4471] merging register 'TopParser_fl_3_reg[1946:0]' into 'section_RealParser_icmp6_neighbor_solicitation_inst/TopParser_fl_1_reg[1946:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:18829] INFO: [Synth 8-4471] merging register 'reject_p_4_reg[1402:0]' into 'section_RealParser_icmp6_neighbor_solicitation_inst/p_2_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:18683] INFO: [Synth 8-4471] merging register 'reject_p_5_reg[1402:0]' into 'RealParser_icmp6_neighbor_solicitation_p_5_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:18684] INFO: [Synth 8-4471] merging register 'reject_p_6_reg[1402:0]' into 'RealParser_icmp6_neighbor_solicitation_p_6_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:18685] INFO: [Synth 8-4471] merging register 'TopParser_fl_4_reg[1946:0]' into 'section_RealParser_icmp6_neighbor_solicitation_inst/TopParser_fl_2_reg[1946:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:18830] WARNING: [Synth 8-6014] Unused sequential element section_RealParser_icmp6_neighbor_solicitation_inst/control_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:19607] INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-4471] merging register 'ErrorCheck_inst/EOP_i1_reg[0:0]' into 'PKT_EOP_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:18990] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-4471] merging register 'start_0_TopParser_extracts_3_reg[31:0]' into 'TopParser_extracts_3_reg[31:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:21228] INFO: [Synth 8-4471] merging register 'start_0_TopParser_extracts_4_reg[31:0]' into 'TopParser_extracts_4_reg[31:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:21229] INFO: [Synth 8-4471] merging register 'start_0_TopParser_extracts_5_reg[31:0]' into 'TopParser_extracts_5_reg[31:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:21230] INFO: [Synth 8-4471] merging register 'start_0_TopParser_extracts_6_reg[31:0]' into 'TopParser_extracts_6_reg[31:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:21231] INFO: [Synth 8-4471] merging register 'control_increment_offsetEop_1_reg[0:0]' into 'compute_control_nextSection_inst/flag1_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6423] INFO: [Synth 8-4471] merging register 'compute_p_ipv4_src_addr_inst/term1R_reg[127:0]' into 'compute_TopPipe_fl_realmain_src_1_inst/term1R_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:8499] INFO: [Synth 8-4471] merging register 'compute_p_ipv4_src_addr_inst/TopPipe_fl_1_reg[31:0]' into 'compute_TopPipe_fl_realmain_src_1_inst/TopPipe_fl_1_reg[31:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:8454] INFO: [Synth 8-4471] merging register 'compute_p_ipv4_src_addr_inst/term2_reg[127:0]' into 'compute_TopPipe_fl_realmain_src_1_inst/term2_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:8489] INFO: [Synth 8-4471] merging register 'compute_p_ipv4_dst_addr_inst/term1_reg[127:0]' into 'compute_TopPipe_fl_realmain_dst_1_inst/term1_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:8598] INFO: [Synth 8-4471] merging register 'control_increment_offsetEop_1_reg[0:0]' into 'control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7242] INFO: [Synth 8-4471] merging register 'control_increment_offsetEop_2_reg[0:0]' into 'control_nextDone_2_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7243] INFO: [Synth 8-4471] merging register 'p_ipv4_dst_addr_2_reg[31:0]' into 'TopPipe_fl_realmain_dst_1_2_reg[31:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7234] INFO: [Synth 8-4471] merging register 'p_ipv6_isValid_1_reg[0:0]' into 'control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7214] INFO: [Synth 8-4471] merging register 'p_ipv6_isValid_2_reg[0:0]' into 'control_nextDone_2_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7215] INFO: [Synth 8-4471] merging register 'user_metadata_chk_ipv4_1_reg[0:0]' into 'p_ipv4_isValid_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7205] INFO: [Synth 8-4471] merging register 'user_metadata_chk_ipv4_2_reg[0:0]' into 'p_ipv4_isValid_2_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7206] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_TopPipe_fl_realmain_src_1_inst/term2_reg' and it is trimmed from '128' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7472] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_TopPipe_fl_realmain_src_1_inst/term1R_reg' and it is trimmed from '128' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7482] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_TopPipe_fl_realmain_dst_1_inst/term1_reg' and it is trimmed from '128' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7581] WARNING: [Synth 8-3936] Found unconnected internal register 'TopPipe_fl_2_reg' and it is trimmed from '769' to '705' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7289] WARNING: [Synth 8-3936] Found unconnected internal register 'TopPipe_fl_1_reg' and it is trimmed from '769' to '705' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7288] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-4471] merging register 'section_condition_sec_4_inst/control_increment_offsetEop_1_reg[0:0]' into 'section_condition_sec_4_inst/compute_control_nextSection_inst/flag1_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:9699] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/compute_p_ipv6_dst_addr_inst/TopPipe_fl_1_reg[287:0]' into 'section_realmain_nat46_static_sec_inst/compute_TopPipe_fl_realmain_dst_2_inst/TopPipe_fl_1_reg[287:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:11023] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/compute_p_ipv6_src_addr_inst/term1_reg[127:0]' into 'section_realmain_nat46_static_sec_inst/compute_TopPipe_fl_realmain_src_2_inst/term1_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:11167] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/control_1_reg[22:0]' into 'section_condition_sec_4_inst/control_1_reg[22:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10439] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/control_nextDone_1_reg[0:0]' into 'section_condition_sec_4_inst/compute_control_nextSection_inst/flag1_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10384] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/control_increment_offsetEop_1_reg[0:0]' into 'section_condition_sec_4_inst/compute_control_nextSection_inst/flag1_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10404] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/control_increment_offsetEop_2_reg[0:0]' into 'section_realmain_nat46_static_sec_inst/control_nextDone_2_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10405] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/control_increment_offset_1_reg[10:0]' into 'section_condition_sec_4_inst/control_increment_offset_1_reg[10:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10389] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/TopPipe_fl_1_reg[768:0]' into 'section_condition_sec_4_inst/TopPipe_fl_1_reg[768:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10444] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/digest_data_1_reg[255:0]' into 'section_condition_sec_4_inst/digest_data_1_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10449] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/local_state_1_reg[15:0]' into 'section_condition_sec_4_inst/local_state_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10454] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/p_1_reg[1402:0]' into 'section_condition_sec_4_inst/p_1_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10459] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/p_ipv4_isValid_1_reg[0:0]' into 'section_condition_sec_4_inst/compute_control_nextSection_inst/flag1_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10434] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/p_ipv4_isValid_2_reg[0:0]' into 'section_realmain_nat46_static_sec_inst/control_nextDone_2_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10435] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/p_ipv6_src_addr_2_reg[127:0]' into 'section_realmain_nat46_static_sec_inst/TopPipe_fl_realmain_src_2_2_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10361] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/sume_metadata_1_reg[127:0]' into 'section_condition_sec_4_inst/sume_metadata_1_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10464] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/user_metadata_1_reg[159:0]' into 'section_condition_sec_4_inst/user_metadata_1_reg[159:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10469] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/realmain_dummy_table_for_netpfga_0_resp_1_reg[2:0]' into 'section_condition_sec_4_inst/realmain_dummy_table_for_netpfga_0_resp_1_reg[2:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:10474] INFO: [Synth 8-4471] merging register 'realmain_set_egress_port_4_sec_p_1_reg[1402:0]' into 'section_condition_sec_4_inst/p_1_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:9375] INFO: [Synth 8-4471] merging register 'condition_sec_4_p_2_reg[1402:0]' into 'section_realmain_nat46_static_sec_inst/p_2_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:9315] INFO: [Synth 8-4471] merging register 'p_1_reg[1402:0]' into 'section_condition_sec_4_inst/p_1_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:9450] INFO: [Synth 8-4471] merging register 'realmain_set_egress_port_4_sec_p_2_reg[1402:0]' into 'section_realmain_nat46_static_sec_inst/p_2_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:9376] INFO: [Synth 8-4471] merging register 'p_2_reg[1402:0]' into 'section_realmain_nat46_static_sec_inst/p_2_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:9451] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/compute_p_ipv6_dst_addr_inst/term1R_reg[127:0]' into 'section_realmain_nat46_static_sec_inst/compute_TopPipe_fl_realmain_dst_2_inst/term1R_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:11068] INFO: [Synth 8-4471] merging register 'section_realmain_nat46_static_sec_inst/compute_p_ipv6_dst_addr_inst/term2_reg[127:0]' into 'section_realmain_nat46_static_sec_inst/compute_TopPipe_fl_realmain_dst_2_inst/term2_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:11058] WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_EngineStage_5__GB0 has port O81[7] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_EngineStage_5__GB0 has port O81[6] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_EngineStage_5__GB0 has port O81[5] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_EngineStage_5__GB0 has port O81[4] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_EngineStage_5__GB0 has port O81[3] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_EngineStage_5__GB0 has port O81[2] driven by constant 1 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_EngineStage_5__GB0 has port O81[1] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_EngineStage_5__GB0 has port O81[0] driven by constant 0 INFO: [Synth 8-4471] merging register 'realmain_set_egress_port_4_sec_TopPipe_fl_1_reg[768:0]' into 'TopPipe_fl_1_reg[768:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:9360] INFO: [Synth 8-4471] merging register 'realmain_set_egress_port_4_sec_TopPipe_fl_2_reg[768:0]' into 'TopPipe_fl_2_reg[768:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:9361] INFO: [Synth 8-4471] merging register 'realmain_set_egress_port_4_sec_digest_data_1_reg[255:0]' into 'digest_data_1_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:9365] INFO: [Synth 8-4471] merging register 'realmain_set_egress_port_4_sec_digest_data_2_reg[255:0]' into 'digest_data_2_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:9366] INFO: [Synth 8-4471] merging register 'realmain_set_egress_port_4_sec_local_state_1_reg[15:0]' into 'local_state_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:9370] INFO: [Synth 8-4471] merging register 'realmain_set_egress_port_4_sec_local_state_2_reg[15:0]' into 'local_state_2_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:9371] INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term9_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:14930] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term8L_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:14936] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term7LL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:14942] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term6LLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:14948] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term5LLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:14954] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term4LLLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:14960] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term3LLLLLR_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:15010] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term4LLLLR_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:15024] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term3LLLLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:14966] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term2LLLLLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:14972] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term2LLLLLLR_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:14986] WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port control_increment_offsetEop_0 driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port resultOut[10] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port resultOut[9] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port resultOut[8] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port resultOut[7] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port resultOut[6] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port resultOut[5] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port resultOut[4] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port resultOut[3] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port resultOut[2] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port resultOut[1] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port resultOut[0] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port control_nextDone_0 driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port O90[5] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port O90[4] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port O90[3] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port O90[2] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port O90[1] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 has port O90[0] driven by constant 1 WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term9_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:19063] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term8L_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:19069] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term7LL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:19075] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term6LLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:19081] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term5LLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:19087] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term4LLLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:19093] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term3LLLLLR_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:19143] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term4LLLLR_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:19157] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term3LLLLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:19099] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term2LLLLLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:19105] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term2LLLLLLR_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:19119] WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port control_increment_offsetEop_0 driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port resultOut[10] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port resultOut[9] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port resultOut[8] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port resultOut[7] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port resultOut[6] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port resultOut[5] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port resultOut[4] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port resultOut[3] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port resultOut[2] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port resultOut[1] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port resultOut[0] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port control_nextDone_0 driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port O105[5] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port O105[4] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port O105[3] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port O105[2] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port O105[1] driven by constant 1 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 has port O105[0] driven by constant 0 WARNING: [Synth 8-3936] Found unconnected internal register 'section_act_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/term1L_reg' and it is trimmed from '17' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:22963] WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_EngineStage_9__GB0 has port TX_TUPLE_TopPipe_fl[448] driven by constant 0 WARNING: [Synth 8-3936] Found unconnected internal register 'compute_TopPipe_fl_realmain_tmp17_0_inst/term1L_reg' and it is trimmed from '17' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:25077] WARNING: [Synth 8-3936] Found unconnected internal register 'section_act_1_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/term1L_reg' and it is trimmed from '17' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:27848] WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_EngineStage_12__GB0 has port TX_TUPLE_TopPipe_fl[448] driven by constant 0 INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3936] Found unconnected internal register 'compute_TopPipe_fl_realmain_tmp17_0_inst/term1L_reg' and it is trimmed from '17' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:29454] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term9_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:34079] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term8L_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:34085] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term7LL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:34091] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term6LLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:34097] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term5LLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:34103] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term4LLLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:34109] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term3LLLLLR_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:34159] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term4LLLLR_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:34173] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term3LLLLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:34115] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term2LLLLLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:34121] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term2LLLLLLR_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:34135] WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port control_increment_offsetEop_0 driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port resultOut[10] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port resultOut[9] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port resultOut[8] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port resultOut[7] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port resultOut[6] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port resultOut[5] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port resultOut[4] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port resultOut[3] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port resultOut[2] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port resultOut[1] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port resultOut[0] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port control_nextDone_0 driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port O158[5] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port O158[4] driven by constant 1 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port O158[3] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port O158[2] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port O158[1] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 has port O158[0] driven by constant 0 WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term9_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:38212] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term8L_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:38218] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term7LL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:38224] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term6LLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:38230] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term5LLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:38236] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term4LLLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:38242] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term3LLLLLR_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:38292] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term4LLLLR_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:38306] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term3LLLLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:38248] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term2LLLLLLL_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:38254] WARNING: [Synth 8-3936] Found unconnected internal register 'compute_user_metadata_v4sum_inst/term2LLLLLLR_reg' and it is trimmed from '32' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:38268] WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port control_increment_offsetEop_0 driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port resultOut[10] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port resultOut[9] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port resultOut[8] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port resultOut[7] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port resultOut[6] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port resultOut[5] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port resultOut[4] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port resultOut[3] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port resultOut[2] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port resultOut[1] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port resultOut[0] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port control_nextDone_0 driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port O176[5] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port O176[4] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port O176[3] driven by constant 0 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port O176[2] driven by constant 1 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port O176[1] driven by constant 1 WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 has port O176[0] driven by constant 1 WARNING: [Synth 8-3936] Found unconnected internal register 'section_act_4_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/term1L_reg' and it is trimmed from '17' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:42112] WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_EngineStage_18__GB0 has port TX_TUPLE_TopPipe_fl[448] driven by constant 0 WARNING: [Synth 8-3936] Found unconnected internal register 'compute_TopPipe_fl_realmain_tmp17_0_inst/term1L_reg' and it is trimmed from '17' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:43686] WARNING: [Synth 8-3936] Found unconnected internal register 'section_act_6_sec_inst/compute_TopPipe_fl_realmain_tmp17_0_inst/term1L_reg' and it is trimmed from '17' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:46997] WARNING: [Synth 8-3917] design TopPipe_lvl_0_t_EngineStage_21__GB1 has port O206[448] driven by constant 0 WARNING: [Synth 8-3936] Found unconnected internal register 'compute_TopPipe_fl_realmain_tmp17_0_inst/term1L_reg' and it is trimmed from '17' to '16' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:48603] INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5784] Optimized 5 bits of RAM "RAM/RAM_reg" due to constant propagation. Old ram width 44 bits, new ram width 39 bits. INFO: [Synth 8-5784] Optimized 5 bits of RAM "RAM/RAM_reg" due to constant propagation. Old ram width 44 bits, new ram width 39 bits. INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5784] Optimized 5 bits of RAM "RAM/RAM_reg" due to constant propagation. Old ram width 44 bits, new ram width 39 bits. INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5784] Optimized 5 bits of RAM "RAM/RAM_reg" due to constant propagation. Old ram width 44 bits, new ram width 39 bits. WARNING: [Synth 8-3936] Found unconnected internal register 'shiftFieldData_0/data_i5_reg' and it is trimmed from '47' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:60685] WARNING: [Synth 8-3936] Found unconnected internal register 'shiftFieldMask_0/data_i5_reg' and it is trimmed from '47' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:60685] WARNING: [Synth 8-3936] Found unconnected internal register 'shiftFieldData_1/data_i5_reg' and it is trimmed from '47' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:60685] WARNING: [Synth 8-3936] Found unconnected internal register 'shiftFieldMask_1/data_i5_reg' and it is trimmed from '47' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:60685] WARNING: [Synth 8-3936] Found unconnected internal register 'shiftFieldData_2/data_i5_reg' and it is trimmed from '47' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:60685] WARNING: [Synth 8-3936] Found unconnected internal register 'shiftFieldMask_2/data_i5_reg' and it is trimmed from '47' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:60685] INFO: [Synth 8-5784] Optimized 5 bits of RAM "RAM/RAM_reg" due to constant propagation. Old ram width 44 bits, new ram width 39 bits. INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3936] Found unconnected internal register 'shiftFieldData_0/data_i5_reg' and it is trimmed from '47' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:66433] WARNING: [Synth 8-3936] Found unconnected internal register 'shiftFieldMask_0/data_i5_reg' and it is trimmed from '47' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:66433] WARNING: [Synth 8-3936] Found unconnected internal register 'shiftFieldData_1/data_i5_reg' and it is trimmed from '47' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:66433] WARNING: [Synth 8-3936] Found unconnected internal register 'shiftFieldMask_1/data_i5_reg' and it is trimmed from '47' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:66433] WARNING: [Synth 8-3936] Found unconnected internal register 'shiftFieldData_2/data_i5_reg' and it is trimmed from '47' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:66433] WARNING: [Synth 8-3936] Found unconnected internal register 'shiftFieldMask_2/data_i5_reg' and it is trimmed from '47' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:66433] INFO: [Synth 8-5784] Optimized 5 bits of RAM "RAM/RAM_reg" due to constant propagation. Old ram width 44 bits, new ram width 39 bits. INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Common 17-14] Message 'Synth 8-5775' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Removed BRAM instance from module xpm_memory_base__parameterized9 due to constant propagation Removed BRAM instance from module xpm_memory_base__parameterized9 due to constant propagation Removed BRAM instance from module xpm_memory_base__parameterized9 due to constant propagation Removed BRAM instance from module xpm_memory_base__parameterized9 due to constant propagation Removed BRAM instance from module xpm_memory_base__parameterized9 due to constant propagation Removed BRAM instance from module xpm_memory_base__parameterized9 due to constant propagation Removed BRAM instance from module xpm_memory_base__parameterized9 due to constant propagation Removed BRAM instance from module xpm_memory_base__parameterized9 due to constant propagation Removed BRAM instance from module xpm_memory_base__parameterized9 due to constant propagation Removed BRAM instance from module xpm_memory_base__parameterized9 due to constant propagation Removed 10 RAM instances from module xpm_memory_base__parameterized9 due to constant propagation INFO: [Synth 8-5784] Optimized 1 bits of RAM "gen_wr_a.gen_word_narrow.mem_reg" due to constant propagation. Old ram width 266 bits, new ram width 265 bits. INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord0" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord1" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord2" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord3" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord4" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord5" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord6" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-3936] Found unconnected internal register 'drp_ipif_i/synch_1/q_reg' and it is trimmed from '34' to '33' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/hdl/ten_gig_eth_pcs_pma_v6_0_rfs.v:40303] INFO: [Synth 8-3936] Found unconnected internal register 'drp_ipif_i/synch_1/d_reg_reg' and it is trimmed from '34' to '33' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/hdl/ten_gig_eth_pcs_pma_v6_0_rfs.v:40277] INFO: [Synth 8-5587] ROM size for "gt_txc_mux" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port is_eval driven by constant 0 INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port gt_progdiv_reset driven by constant 0 INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[4] driven by constant 0 INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[3] driven by constant 0 INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[2] driven by constant 0 INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[1] driven by constant 0 INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[0] driven by constant 0 INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[4] driven by constant 0 INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[3] driven by constant 0 INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[2] driven by constant 0 INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[1] driven by constant 0 INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[0] driven by constant 0 INFO: [Common 17-14] Message 'Synth 8-3917' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5545] ROM "broadcast_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "broadcast_detect" won't be mapped to RAM because address size (48) is larger than maximum supported(25) INFO: [Synth 8-5784] Optimized 104 bits of RAM "axis_fifo_inst/meta_fifo/fifo/queue_reg" due to constant propagation. Old ram width 128 bits, new ram width 24 bits. INFO: [Synth 8-5583] The signal axis_fifo_inst/meta_fifo/fifo/queue_reg is implemented as block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (5 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM. INFO: [Synth 8-5545] ROM "broadcast_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "broadcast_detect" won't be mapped to RAM because address size (48) is larger than maximum supported(25) INFO: [Synth 8-5784] Optimized 104 bits of RAM "axis_fifo_inst/meta_fifo/fifo/queue_reg" due to constant propagation. Old ram width 128 bits, new ram width 24 bits. INFO: [Synth 8-5583] The signal axis_fifo_inst/meta_fifo/fifo/queue_reg is implemented as block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (5 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM. INFO: [Synth 8-5784] Optimized 104 bits of RAM "axis_fifo_inst/meta_fifo/fifo/queue_reg" due to constant propagation. Old ram width 128 bits, new ram width 24 bits. INFO: [Synth 8-5583] The signal axis_fifo_inst/meta_fifo/fifo/queue_reg is implemented as block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (5 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM. INFO: [Synth 8-5784] Optimized 104 bits of RAM "axis_fifo_inst/meta_fifo/fifo/queue_reg" due to constant propagation. Old ram width 128 bits, new ram width 24 bits. INFO: [Synth 8-5583] The signal axis_fifo_inst/meta_fifo/fifo/queue_reg is implemented as block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (5 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:21:02 ; elapsed = 00:20:22 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 2114 ; free virtual = 21852 --------------------------------------------------------------------------------- INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_7 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_7 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_8 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_9 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_10 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_11 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_12 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_13 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_14 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_15 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_16 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_17 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_18 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_19 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_10 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_7 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_8 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_9 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_10 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_11 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_12 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_13 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_14 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_15 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_16 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_17 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_18 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_19 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_7 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_8 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_9 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_10 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_11 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Common 17-14] Message 'Synth 8-4480' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Report RTL Partitions: +------+------------------------------------------------------------------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+------------------------------------------------------------------------------+------------+----------+ |1 |clk_wiz_ip_clk_wiz__GC0 | 1| 13| |2 |TopParser_t_EngineStage_0__GB0 | 1| 26012| |3 |TopParser_t_EngineStage_0__GB1 | 1| 15348| |4 |TopParser_t_EngineStage_0__GB2 | 1| 6334| |5 |TopParser_t_EngineStage_0__GB3 | 1| 27258| |6 |TopParser_t_EngineStage_0__GB4 | 1| 18304| |7 |TopParser_t_EngineStage_0__GB5 | 1| 9420| |8 |TopParser_t_EngineStage_1__GB0 | 1| 15132| |9 |TopParser_t_EngineStage_1__GB1 | 1| 16442| |10 |TopParser_t_EngineStage_1__GB2 | 1| 5293| |11 |TopParser_t_EngineStage_1__GB3 | 1| 8899| |12 |TopParser_t_EngineStage_1__GB4 | 1| 14696| |13 |TopParser_t_EngineStage_1__GB5 | 1| 25325| |14 |TopParser_t_EngineStage_1__GB6 | 1| 21537| |15 |TopParser_t_EngineStage_1__GB7 | 1| 29478| |16 |TopParser_t_EngineStage_2__GB0 | 1| 14134| |17 |TopParser_t_EngineStage_2__GB1 | 1| 9783| |18 |TopParser_t_EngineStage_2__GB2 | 1| 6205| |19 |TopParser_t_EngineStage_2__GB3 | 1| 27266| |20 |TopParser_t_EngineStage_2__GB4 | 1| 8622| |21 |TopParser_t_EngineStage_2__GB5 | 1| 30967| |22 |TopParser_t_EngineStage_2__GB6 | 1| 11224| |23 |TopParser_t_EngineStage_2__GB7 | 1| 10850| |24 |TopParser_t_EngineStage_2__GB8 | 1| 28273| |25 |TopParser_t_EngineStage_3__GB0 | 1| 18982| |26 |TopParser_t_EngineStage_3__GB1 | 1| 25456| |27 |TopParser_t_EngineStage_3__GB2 | 1| 27482| |28 |TopParser_t_EngineStage_3__GB3 | 1| 16357| |29 |TopParser_t_EngineStage_3__GB4 | 1| 7667| |30 |TopParser_t_EngineStage_4__GB0 | 1| 11817| |31 |TopParser_t_EngineStage_4__GB1 | 1| 21094| |32 |TopParser_t_EngineStage_4__GB2 | 1| 27263| |33 |TopParser_t_EngineStage_4__GB3 | 1| 17468| |34 |TopParser_t_EngineStage_5__GB0 | 1| 39356| |35 |TopParser_t_EngineStage_5__GB1 | 1| 27632| |36 |TopParser_t_EngineStage_5__GB2 | 1| 21906| |37 |TopParser_t_Engine__GC0 | 1| 402| |38 |TopParser_t__GC0 | 1| 21| |39 |TopPipe_lvl_0_t_EngineStage_4__GB0 | 1| 20675| |40 |TopPipe_lvl_0_t_EngineStage_4__GB1 | 1| 17619| |41 |TopPipe_lvl_0_t_EngineStage_5__GB0 | 1| 12015| |42 |TopPipe_lvl_0_t_EngineStage_5__GB1 | 1| 13714| |43 |TopPipe_lvl_0_t_realmain_delta_prepare_sec_compute_user_metadata_v6sum__GB0 | 1| 4680| |44 |TopPipe_lvl_0_t_realmain_delta_prepare_sec_compute_user_metadata_v6sum__GB1 | 1| 918| |45 |TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB0 | 1| 21049| |46 |TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB1 | 1| 5676| |47 |TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 | 1| 28060| |48 |TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB3 | 1| 723| |49 |TopPipe_lvl_0_t_EngineStage_6__GCB0 | 1| 20897| |50 |TopPipe_lvl_0_t_EngineStage_6__GCB1 | 1| 27433| |51 |TopPipe_lvl_0_t_EngineStage_6__GCB2 | 1| 19642| |52 |TopPipe_lvl_0_t_EngineStage_6__GCB3 | 1| 26509| |53 |TopPipe_lvl_0_t_EngineStage_6__GCB4 | 1| 26440| |54 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec_compute_user_metadata_v6sum__GB0 | 1| 4680| |55 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec_compute_user_metadata_v6sum__GB1 | 1| 918| |56 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB0 | 1| 21049| |57 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB1 | 1| 5676| |58 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 | 1| 28060| |59 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB3 | 1| 723| |60 |TopPipe_lvl_0_t_EngineStage_7__GCB0 | 1| 22291| |61 |TopPipe_lvl_0_t_EngineStage_7__GCB1 | 1| 12627| |62 |TopPipe_lvl_0_t_EngineStage_7__GCB2 | 1| 19229| |63 |TopPipe_lvl_0_t_EngineStage_7__GCB3 | 1| 13800| |64 |TopPipe_lvl_0_t_EngineStage_7__GCB4 | 1| 28064| |65 |TopPipe_lvl_0_t_EngineStage_7__GCB5 | 1| 2453| |66 |TopPipe_lvl_0_t_EngineStage_7__GCB6 | 1| 273| |67 |TopPipe_lvl_0_t_EngineStage_7__GCB7 | 1| 26585| |68 |TopPipe_lvl_0_t_EngineStage_8__GB0 | 1| 19655| |69 |TopPipe_lvl_0_t_EngineStage_8__GB1 | 1| 22836| |70 |TopPipe_lvl_0_t_EngineStage_8__GB2 | 1| 65| |71 |TopPipe_lvl_0_t_EngineStage_8__GB3 | 1| 9799| |72 |TopPipe_lvl_0_t_EngineStage_9__GB0 | 1| 16719| |73 |TopPipe_lvl_0_t_EngineStage_9__GB1 | 1| 17633| |74 |TopPipe_lvl_0_t_EngineStage_10__GB0 | 1| 32011| |75 |TopPipe_lvl_0_t_EngineStage_10__GB1 | 1| 2845| |76 |TopPipe_lvl_0_t_EngineStage_10__GB2 | 1| 9345| |77 |TopPipe_lvl_0_t_EngineStage_11__GB0 | 1| 16841| |78 |TopPipe_lvl_0_t_EngineStage_11__GB1 | 1| 11075| |79 |TopPipe_lvl_0_t_EngineStage_11__GB2 | 1| 2871| |80 |TopPipe_lvl_0_t_EngineStage_11__GB3 | 1| 18983| |81 |TopPipe_lvl_0_t_EngineStage_12__GB0 | 1| 16720| |82 |TopPipe_lvl_0_t_EngineStage_12__GB1 | 1| 17631| |83 |TopPipe_lvl_0_t_EngineStage_13__GB0 | 1| 10951| |84 |TopPipe_lvl_0_t_EngineStage_13__GB1 | 1| 5773| |85 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec_compute_user_metadata_v6sum__GB0 | 1| 4680| |86 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec_compute_user_metadata_v6sum__GB1 | 1| 918| |87 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB0 | 1| 21049| |88 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB1 | 1| 5676| |89 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 | 1| 28060| |90 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB3 | 1| 723| |91 |TopPipe_lvl_0_t_EngineStage_15__GCB0 | 1| 21667| |92 |TopPipe_lvl_0_t_EngineStage_15__GCB1 | 1| 27400| |93 |TopPipe_lvl_0_t_EngineStage_15__GCB2 | 1| 18239| |94 |TopPipe_lvl_0_t_EngineStage_15__GCB3 | 1| 26452| |95 |TopPipe_lvl_0_t_EngineStage_15__GCB4 | 1| 25663| |96 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec_compute_user_metadata_v6sum__GB0 | 1| 4680| |97 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec_compute_user_metadata_v6sum__GB1 | 1| 918| |98 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB0 | 1| 21049| |99 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB1 | 1| 5676| |100 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 | 1| 28060| |101 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB3 | 1| 723| |102 |TopPipe_lvl_0_t_EngineStage_16__GCB0 | 1| 22470| |103 |TopPipe_lvl_0_t_EngineStage_16__GCB1 | 1| 19655| |104 |TopPipe_lvl_0_t_EngineStage_16__GCB2 | 1| 28060| |105 |TopPipe_lvl_0_t_EngineStage_16__GCB3 | 1| 29771| |106 |TopPipe_lvl_0_t_EngineStage_16__GCB4 | 1| 28471| |107 |TopPipe_lvl_0_t_EngineStage_16__GCB5 | 1| 273| |108 |TopPipe_lvl_0_t_EngineStage_17__GB0 | 1| 11116| |109 |TopPipe_lvl_0_t_EngineStage_17__GB1 | 1| 19650| |110 |TopPipe_lvl_0_t_EngineStage_17__GB2 | 1| 65| |111 |TopPipe_lvl_0_t_EngineStage_17__GB3 | 1| 7450| |112 |TopPipe_lvl_0_t_EngineStage_18__GB0 | 1| 16720| |113 |TopPipe_lvl_0_t_EngineStage_18__GB1 | 1| 17671| |114 |TopPipe_lvl_0_t_EngineStage_19__GB0 | 1| 30517| |115 |TopPipe_lvl_0_t_EngineStage_19__GB1 | 1| 8177| |116 |TopPipe_lvl_0_t_EngineStage_20__GB0 | 1| 26451| |117 |TopPipe_lvl_0_t_EngineStage_20__GB1 | 1| 8361| |118 |TopPipe_lvl_0_t_EngineStage_20__GB2 | 1| 65| |119 |TopPipe_lvl_0_t_EngineStage_20__GB3 | 1| 19274| |120 |TopPipe_lvl_0_t_EngineStage_21__GB0 | 1| 18239| |121 |TopPipe_lvl_0_t_EngineStage_21__GB1 | 1| 11042| |122 |TopPipe_lvl_0_t_EngineStage_21__GB2 | 1| 2871| |123 |TopPipe_lvl_0_t_EngineStage_21__GB3 | 1| 20335| |124 |TopPipe_lvl_0_t_EngineStage_22 | 1| 16683| |125 |TopPipe_lvl_0_t_EngineStage_14 | 1| 13485| |126 |TopPipe_lvl_0_t_EngineStage_23 | 1| 11254| |127 |TopPipe_lvl_0_t_Engine__GCB3 | 1| 26073| |128 |TopPipe_lvl_0_t_Engine__GCB4 | 1| 33123| |129 |TopPipe_lvl_0_t_Engine__GCB5 | 1| 5550| |130 |TopPipe_lvl_0_t_Engine__GCB6 | 1| 37448| |131 |TopDeparser_t_EngineStage_0__GB0 | 1| 19224| |132 |TopDeparser_t_EngineStage_0__GB1 | 1| 3041| |133 |TopDeparser_t_EngineStage_0__GB2 | 1| 14024| |134 |reg__7352 | 1| 1403| |135 |TopDeparser_t_EngineStage_2_Editor__GB0 | 1| 21244| |136 |TopDeparser_t_EngineStage_2_Editor__GB1 | 1| 6970| |137 |TopDeparser_t_EngineStage_2__GC0 | 1| 16398| |138 |TopDeparser_t_EngineStage_3_Editor__GB0 | 1| 20653| |139 |TopDeparser_t_EngineStage_3_Editor__GB1 | 1| 5080| |140 |TopDeparser_t_EngineStage_3__GC0 | 1| 16344| |141 |TopDeparser_t_EngineStage_4_Editor_TupleMerge__GB0 | 1| 14931| |142 |TopDeparser_t_EngineStage_4_Editor_TupleMerge__GB1 | 1| 5705| |143 |TopDeparser_t_EngineStage_4_Editor_TupleMerge__GB2 | 1| 3832| |144 |TopDeparser_t_EngineStage_4_Editor__GC0 | 1| 24966| |145 |TopDeparser_t_EngineStage_4__GC0 | 1| 16445| |146 |TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple | 4| 2720| |147 |TopDeparser_t_EngineStage_5_Editor_TupleMerge__GC0 | 1| 5674| |148 |TopDeparser_t_EngineStage_5_Editor__GCB0 | 1| 19742| |149 |TopDeparser_t_EngineStage_5_Editor__GCB1 | 1| 9359| |150 |TopDeparser_t_EngineStage_5__GC0 | 1| 16605| |151 |TopDeparser_t_EngineStage_6_Editor_TupleMerge__GB0 | 1| 13060| |152 |TopDeparser_t_EngineStage_6_Editor_TupleMerge__GB1 | 1| 5472| |153 |TopDeparser_t_EngineStage_6_Editor_TupleMerge__GB2 | 1| 3331| |154 |TopDeparser_t_EngineStage_6_Editor__GC0 | 1| 26308| |155 |TopDeparser_t_EngineStage_6__GC0 | 1| 16510| |156 |TopDeparser_t_EngineStage_7_Editor_TupleMerge__GB0 | 1| 19194| |157 |TopDeparser_t_EngineStage_7_Editor_TupleMerge__GB1 | 1| 6962| |158 |TopDeparser_t_EngineStage_7_Editor_TupleMerge__GB2 | 1| 4918| |159 |TopDeparser_t_EngineStage_7_Editor__GC0 | 1| 25094| |160 |TopDeparser_t_EngineStage_7__GC0 | 1| 16445| |161 |TopDeparser_t_EngineStage_8_Editor__GB0 | 1| 20653| |162 |TopDeparser_t_EngineStage_8_Editor__GB1 | 1| 5080| |163 |TopDeparser_t_EngineStage_8__GC0 | 1| 16344| |164 |TopDeparser_t_EngineStage_9__GB0 | 1| 24994| |165 |TopDeparser_t_EngineStage_9__GB1 | 1| 2668| |166 |TopDeparser_t_EngineStage_9__GB2 | 1| 19002| |167 |reg__11231 | 1| 1403| |168 |TopDeparser_t_EngineStage_10__GB0 | 1| 24994| |169 |TopDeparser_t_EngineStage_10__GB1 | 1| 2668| |170 |TopDeparser_t_EngineStage_10__GB2 | 1| 19002| |171 |reg__11629 | 1| 1403| |172 |TopDeparser_t_EngineStage_11_Editor__GB0 | 1| 12913| |173 |TopDeparser_t_EngineStage_11_Editor__GB1 | 1| 22440| |174 |TopDeparser_t_EngineStage_11__GC0 | 1| 16445| |175 |TopDeparser_t_EngineStage_12_Editor__GB0 | 1| 20629| |176 |TopDeparser_t_EngineStage_12_Editor__GB1 | 1| 4657| |177 |TopDeparser_t_EngineStage_12__GC0 | 1| 16340| |178 |TopDeparser_t_Engine__GC0 | 1| 20488| |179 |TopDeparser_t__GC0 | 1| 23| |180 |SimpleSumeSwitch__GCB0 | 1| 12433| |181 |S_SYNCER_for_TopDeparser | 1| 5112| |182 |SimpleSumeSwitch__GCB2 | 1| 6754| |183 |SimpleSumeSwitch__GCB3 | 1| 9213| |184 |nf_sume_sdnet__GC0 | 1| 11| |185 |nf_datapath__GCB0 | 1| 14815| |186 |nf_datapath__GCB1 | 1| 9225| |187 |bd_a1aa_xpcs_0_shared_clock_and_reset__GC0 | 1| 53| |188 |ten_gig_eth_pcs_pma_v6_0_13 | 4| 9273| |189 |bd_a1aa_xpcs_0_block__GC0 | 1| 674| |190 |bd_a1aa_xpcs_0_support__GC0 | 1| 2| |191 |bd_a1aa__GC0 | 1| 9790| |192 |nf_10g_interface_shared_block__GC0 | 1| 7932| |193 |nf_10g_interface_shared__GC0 | 1| 1851| |194 |bd_7ad4_xmac_0_block | 3| 9790| |195 |bd_7ad4_xpcs_0_block__GC0 | 3| 674| |196 |nf_10g_interface_block__xdcDup__1__GC0 | 1| 7932| |197 |nf_10g_interface__xdcDup__1__GC0 | 1| 1789| |198 |nf_10g_interface_block__xdcDup__2__GC0 | 1| 7932| |199 |nf_10g_interface__xdcDup__2__GC0 | 1| 1789| |200 |nf_10g_interface_block__GC0 | 1| 7932| |201 |nf_10g_interface__GC0 | 1| 1789| |202 |top__GC0 | 1| 7748| |203 |TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple__1 | 2| 1607| |204 |TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple__2 | 2| 1605| |205 |TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple__3 | 6| 1523| |206 |TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple__4 | 2| 1475| +------+------------------------------------------------------------------------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/clk_wiz_1/clk_out1' to pin 'control_sub_i/nf_mbsys/clk_wiz_1/bbstub_clk_out1/O' INFO: [Synth 8-5783] Moving clock source from hierarchical pin 'control_sub_i/nf_mbsys/clk_wiz_1/clk_in1' to 'axi_lite_bufg0/I' INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/mbsys/mdm_1/Dbg_Clk_0' to pin 'control_sub_i/nf_mbsys/mbsys/mdm_1/bbstub_Dbg_Clk_0/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/mbsys/mdm_1/Dbg_Update_0' to pin 'control_sub_i/nf_mbsys/mbsys/mdm_1/bbstub_Dbg_Update_0/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr/BRAM_Clk_A' to pin 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr/bbstub_BRAM_Clk_A/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr/BRAM_Clk_A' to pin 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr/bbstub_BRAM_Clk_A/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/dma_sub/pcie3_7x_1/user_clk' to pin 'control_sub_i/dma_sub/pcie3_7x_1/bbstub_user_clk/O' WARNING: [Synth 8-3321] set_false_path : Empty from list for constraint at line 75 of /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:75] WARNING: [Synth 8-3321] set_false_path : Empty from list for constraint at line 75 of /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:75] WARNING: [Synth 8-3321] set_false_path : Empty from list for constraint at line 75 of /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:75] WARNING: [Synth 8-3321] set_false_path : Empty from list for constraint at line 76 of /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:76] INFO: [Synth 8-5578] Moved timing constraint from pin 'axi_clocking_i/clk_wiz_i/inst/clk_in1' to pin 'axi_clocking_i/clkin1_buf/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'axi_clocking_i/clk_wiz_i/clk_out1' to pin 'clkout1_buf/O' WARNING: [Synth 8-565] redefining clock 'xphy_refclk_p' WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' INFO: [Synth 8-5819] Moved 9 constraints on hierarchical pins to their respective driving/loading pins --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:23:16 ; elapsed = 00:22:39 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 249 ; free virtual = 20766 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:30:06 ; elapsed = 00:29:51 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 375 ; free virtual = 20844 --------------------------------------------------------------------------------- Report RTL Partitions: +------+------------------------------------------------------------------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+------------------------------------------------------------------------------+------------+----------+ |1 |clk_wiz_ip_clk_wiz__GC0 | 1| 13| |2 |TopParser_t_EngineStage_0__GB0 | 1| 43| |3 |TopParser_t_EngineStage_0__GB2 | 1| 352| |4 |TopParser_t_EngineStage_0__GB3 | 1| 1202| |5 |TopParser_t_EngineStage_0__GB4 | 1| 2445| |6 |TopParser_t_EngineStage_0__GB5 | 1| 5227| |7 |TopParser_t_EngineStage_1__GB0 | 1| 2032| |8 |TopParser_t_EngineStage_1__GB1 | 1| 227| |9 |TopParser_t_EngineStage_1__GB2 | 1| 42| |10 |TopParser_t_EngineStage_1__GB3 | 1| 960| |11 |TopParser_t_EngineStage_1__GB4 | 1| 84| |12 |TopParser_t_EngineStage_1__GB5 | 1| 5979| |13 |TopParser_t_EngineStage_1__GB6 | 1| 6248| |14 |TopParser_t_EngineStage_1__GB7 | 1| 12600| |15 |TopParser_t_EngineStage_2__GB0 | 1| 4286| |16 |TopParser_t_EngineStage_2__GB1 | 1| 4023| |17 |TopParser_t_EngineStage_2__GB2 | 1| 1263| |18 |TopParser_t_EngineStage_2__GB3 | 1| 14413| |19 |TopParser_t_EngineStage_2__GB4 | 1| 3237| |20 |TopParser_t_EngineStage_2__GB5 | 1| 60| |21 |TopParser_t_EngineStage_2__GB7 | 1| 4291| |22 |TopParser_t_EngineStage_2__GB8 | 1| 11772| |23 |TopParser_t_EngineStage_3__GB0 | 1| 8373| |24 |TopParser_t_EngineStage_3__GB1 | 1| 134| |25 |TopParser_t_EngineStage_3__GB2 | 1| 16871| |26 |TopParser_t_EngineStage_3__GB3 | 1| 7173| |27 |TopParser_t_EngineStage_3__GB4 | 1| 7364| |28 |TopParser_t_EngineStage_4__GB0 | 1| 6954| |29 |TopParser_t_EngineStage_4__GB1 | 1| 3366| |30 |TopParser_t_EngineStage_4__GB3 | 1| 6105| |31 |TopParser_t_EngineStage_5__GB0 | 1| 7037| |32 |TopParser_t_EngineStage_5__GB1 | 1| 18467| |33 |TopParser_t_EngineStage_5__GB2 | 1| 9828| |34 |TopParser_t_Engine__GC0 | 1| 402| |35 |TopParser_t__GC0 | 1| 19| |36 |TopPipe_lvl_0_t_EngineStage_4__GB0 | 1| 19313| |37 |TopPipe_lvl_0_t_EngineStage_4__GB1 | 1| 7832| |38 |TopPipe_lvl_0_t_EngineStage_5__GB0 | 1| 6606| |39 |TopPipe_lvl_0_t_EngineStage_5__GB1 | 1| 5840| |40 |TopPipe_lvl_0_t_realmain_delta_prepare_sec_compute_user_metadata_v6sum__GB0 | 1| 2736| |41 |TopPipe_lvl_0_t_realmain_delta_prepare_sec_compute_user_metadata_v6sum__GB1 | 1| 508| |42 |TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB0 | 1| 6329| |43 |TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB1 | 1| 5296| |44 |TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB2 | 1| 28060| |45 |TopPipe_lvl_0_t_realmain_delta_prepare_sec__GCB3 | 1| 6| |46 |TopPipe_lvl_0_t_EngineStage_6__GCB0 | 1| 13502| |47 |TopPipe_lvl_0_t_EngineStage_6__GCB1 | 1| 26673| |48 |TopPipe_lvl_0_t_EngineStage_6__GCB2 | 1| 15433| |49 |TopPipe_lvl_0_t_EngineStage_6__GCB3 | 1| 24767| |50 |TopPipe_lvl_0_t_EngineStage_6__GCB4 | 1| 1141| |51 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec_compute_user_metadata_v6sum__GB0 | 1| 2736| |52 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec_compute_user_metadata_v6sum__GB1 | 1| 508| |53 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB0 | 1| 6329| |54 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB1 | 1| 5296| |55 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB2 | 1| 28060| |56 |TopPipe_lvl_0_t_realmain_delta_prepare_5_sec__GCB3 | 1| 247| |57 |TopPipe_lvl_0_t_EngineStage_7__GCB0 | 1| 21532| |58 |TopPipe_lvl_0_t_EngineStage_7__GCB1 | 1| 12627| |59 |TopPipe_lvl_0_t_EngineStage_7__GCB2 | 1| 829| |60 |TopPipe_lvl_0_t_EngineStage_7__GCB3 | 1| 13442| |61 |TopPipe_lvl_0_t_EngineStage_7__GCB4 | 1| 28064| |62 |TopPipe_lvl_0_t_EngineStage_7__GCB5 | 1| 1717| |63 |TopPipe_lvl_0_t_EngineStage_7__GCB7 | 1| 10293| |64 |TopPipe_lvl_0_t_EngineStage_8__GB0 | 1| 19655| |65 |TopPipe_lvl_0_t_EngineStage_8__GB1 | 1| 10320| |66 |TopPipe_lvl_0_t_EngineStage_8__GB3 | 1| 7938| |67 |TopPipe_lvl_0_t_EngineStage_9__GB0 | 1| 13618| |68 |TopPipe_lvl_0_t_EngineStage_9__GB1 | 1| 7721| |69 |TopPipe_lvl_0_t_EngineStage_10__GB0 | 1| 22351| |70 |TopPipe_lvl_0_t_EngineStage_10__GB1 | 1| 2806| |71 |TopPipe_lvl_0_t_EngineStage_10__GB2 | 1| 6846| |72 |TopPipe_lvl_0_t_EngineStage_11__GB0 | 1| 16841| |73 |TopPipe_lvl_0_t_EngineStage_11__GB1 | 1| 8039| |74 |TopPipe_lvl_0_t_EngineStage_11__GB2 | 1| 2806| |75 |TopPipe_lvl_0_t_EngineStage_11__GB3 | 1| 8323| |76 |TopPipe_lvl_0_t_EngineStage_12__GB0 | 1| 13619| |77 |TopPipe_lvl_0_t_EngineStage_12__GB1 | 1| 7719| |78 |TopPipe_lvl_0_t_EngineStage_13__GB0 | 1| 6389| |79 |TopPipe_lvl_0_t_EngineStage_13__GB1 | 1| 5734| |80 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec_compute_user_metadata_v6sum__GB0 | 1| 2736| |81 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec_compute_user_metadata_v6sum__GB1 | 1| 508| |82 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB0 | 1| 6329| |83 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB1 | 1| 5296| |84 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB2 | 1| 28060| |85 |TopPipe_lvl_0_t_realmain_delta_prepare_4_sec__GCB3 | 1| 247| |86 |TopPipe_lvl_0_t_EngineStage_15__GCB0 | 1| 13548| |87 |TopPipe_lvl_0_t_EngineStage_15__GCB1 | 1| 26662| |88 |TopPipe_lvl_0_t_EngineStage_15__GCB2 | 1| 18239| |89 |TopPipe_lvl_0_t_EngineStage_15__GCB3 | 1| 25264| |90 |TopPipe_lvl_0_t_EngineStage_15__GCB4 | 1| 1100| |91 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec_compute_user_metadata_v6sum__GB0 | 1| 2736| |92 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec_compute_user_metadata_v6sum__GB1 | 1| 508| |93 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB0 | 1| 6329| |94 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB1 | 1| 5296| |95 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB2 | 1| 28060| |96 |TopPipe_lvl_0_t_realmain_delta_prepare_6_sec__GCB3 | 1| 244| |97 |TopPipe_lvl_0_t_EngineStage_16__GCB0 | 1| 21295| |98 |TopPipe_lvl_0_t_EngineStage_16__GCB1 | 1| 19655| |99 |TopPipe_lvl_0_t_EngineStage_16__GCB2 | 1| 28060| |100 |TopPipe_lvl_0_t_EngineStage_16__GCB3 | 1| 13579| |101 |TopPipe_lvl_0_t_EngineStage_16__GCB4 | 1| 9954| |102 |TopPipe_lvl_0_t_EngineStage_17__GB0 | 1| 8036| |103 |TopPipe_lvl_0_t_EngineStage_17__GB1 | 1| 19650| |104 |TopPipe_lvl_0_t_EngineStage_17__GB3 | 1| 5580| |105 |TopPipe_lvl_0_t_EngineStage_18__GB0 | 1| 13579| |106 |TopPipe_lvl_0_t_EngineStage_18__GB1 | 1| 7617| |107 |TopPipe_lvl_0_t_EngineStage_19__GB0 | 1| 22250| |108 |TopPipe_lvl_0_t_EngineStage_19__GB1 | 1| 5636| |109 |TopPipe_lvl_0_t_EngineStage_20__GB0 | 1| 23375| |110 |TopPipe_lvl_0_t_EngineStage_20__GB1 | 1| 6823| |111 |TopPipe_lvl_0_t_EngineStage_20__GB3 | 1| 7753| |112 |TopPipe_lvl_0_t_EngineStage_21__GB0 | 1| 18239| |113 |TopPipe_lvl_0_t_EngineStage_21__GB1 | 1| 7965| |114 |TopPipe_lvl_0_t_EngineStage_21__GB2 | 1| 2806| |115 |TopPipe_lvl_0_t_EngineStage_21__GB3 | 1| 8771| |116 |TopPipe_lvl_0_t_EngineStage_22 | 1| 12025| |117 |TopPipe_lvl_0_t_EngineStage_14 | 1| 8621| |118 |TopPipe_lvl_0_t_EngineStage_23 | 1| 8003| |119 |TopPipe_lvl_0_t_Engine__GCB3 | 1| 25772| |120 |TopPipe_lvl_0_t_Engine__GCB4 | 1| 9217| |121 |TopPipe_lvl_0_t_Engine__GCB5 | 1| 4613| |122 |TopPipe_lvl_0_t_Engine__GCB6 | 1| 16577| |123 |TopDeparser_t_EngineStage_0__GB0 | 1| 18709| |124 |TopDeparser_t_EngineStage_0__GB1 | 1| 2465| |125 |TopDeparser_t_EngineStage_0__GB2 | 1| 13345| |126 |reg__7352 | 1| 1403| |127 |TopDeparser_t_EngineStage_2_Editor__GB0 | 1| 20399| |128 |TopDeparser_t_EngineStage_2_Editor__GB1 | 1| 6968| |129 |TopDeparser_t_EngineStage_2__GC0 | 1| 15318| |130 |TopDeparser_t_EngineStage_3_Editor__GB0 | 1| 19916| |131 |TopDeparser_t_EngineStage_3_Editor__GB1 | 1| 5080| |132 |TopDeparser_t_EngineStage_3__GC0 | 1| 14832| |133 |TopDeparser_t_EngineStage_4_Editor_TupleMerge__GB0 | 1| 14931| |134 |TopDeparser_t_EngineStage_4_Editor_TupleMerge__GB1 | 1| 5705| |135 |TopDeparser_t_EngineStage_4_Editor_TupleMerge__GB2 | 1| 3832| |136 |TopDeparser_t_EngineStage_4_Editor__GC0 | 1| 23547| |137 |TopDeparser_t_EngineStage_4__GC0 | 1| 14749| |138 |TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple | 4| 2720| |139 |TopDeparser_t_EngineStage_5_Editor_TupleMerge__GC0 | 1| 5674| |140 |TopDeparser_t_EngineStage_5_Editor__GCB0 | 1| 17663| |141 |TopDeparser_t_EngineStage_5_Editor__GCB1 | 1| 9357| |142 |TopDeparser_t_EngineStage_5__GC0 | 1| 13655| |143 |TopDeparser_t_EngineStage_6_Editor_TupleMerge__GB0 | 1| 13060| |144 |TopDeparser_t_EngineStage_6_Editor_TupleMerge__GB1 | 1| 5472| |145 |TopDeparser_t_EngineStage_6_Editor_TupleMerge__GB2 | 1| 3331| |146 |TopDeparser_t_EngineStage_6_Editor__GC0 | 1| 24258| |147 |TopDeparser_t_EngineStage_6__GC0 | 1| 11758| |148 |TopDeparser_t_EngineStage_7_Editor_TupleMerge__GB0 | 1| 19194| |149 |TopDeparser_t_EngineStage_7_Editor_TupleMerge__GB1 | 1| 6962| |150 |TopDeparser_t_EngineStage_7_Editor_TupleMerge__GB2 | 1| 4918| |151 |TopDeparser_t_EngineStage_7_Editor__GC0 | 1| 22872| |152 |TopDeparser_t_EngineStage_7__GC0 | 1| 9841| |153 |TopDeparser_t_EngineStage_8_Editor__GB0 | 1| 18935| |154 |TopDeparser_t_EngineStage_8_Editor__GB1 | 1| 5080| |155 |TopDeparser_t_EngineStage_8__GC0 | 1| 8784| |156 |TopDeparser_t_EngineStage_9__GB0 | 1| 23388| |157 |TopDeparser_t_EngineStage_9__GB1 | 1| 2668| |158 |TopDeparser_t_EngineStage_9__GB2 | 1| 6308| |159 |reg__11231 | 1| 323| |160 |TopDeparser_t_EngineStage_10__GB0 | 1| 23335| |161 |TopDeparser_t_EngineStage_10__GB1 | 1| 2668| |162 |TopDeparser_t_EngineStage_10__GB2 | 1| 6114| |163 |reg__11629 | 1| 323| |164 |TopDeparser_t_EngineStage_11_Editor__GB0 | 1| 12911| |165 |TopDeparser_t_EngineStage_11_Editor__GB1 | 1| 20094| |166 |TopDeparser_t_EngineStage_11__GC0 | 1| 7411| |167 |TopDeparser_t_EngineStage_12_Editor__GB0 | 1| 18472| |168 |TopDeparser_t_EngineStage_12_Editor__GB1 | 1| 4613| |169 |TopDeparser_t_EngineStage_12__GC0 | 1| 5636| |170 |TopDeparser_t_Engine__GC0 | 1| 19163| |171 |TopDeparser_t__GC0 | 1| 3| |172 |SimpleSumeSwitch__GCB0 | 1| 12433| |173 |S_SYNCER_for_TopDeparser | 1| 5112| |174 |SimpleSumeSwitch__GCB2 | 1| 6754| |175 |SimpleSumeSwitch__GCB3 | 1| 9093| |176 |nf_sume_sdnet__GC0 | 1| 11| |177 |nf_datapath__GCB0 | 1| 14808| |178 |nf_datapath__GCB1 | 1| 9225| |179 |bd_a1aa_xpcs_0_shared_clock_and_reset__GC0 | 1| 53| |180 |ten_gig_eth_pcs_pma_v6_0_13 | 4| 9273| |181 |bd_a1aa_xpcs_0_block__GC0 | 1| 674| |182 |bd_a1aa_xpcs_0_support__GC0 | 1| 2| |183 |bd_a1aa__GC0 | 1| 9790| |184 |nf_10g_interface_shared_block__GC0 | 1| 7932| |185 |nf_10g_interface_shared__GC0 | 1| 1851| |186 |bd_7ad4_xmac_0_block | 3| 9790| |187 |bd_7ad4_xpcs_0_block__GC0 | 3| 674| |188 |nf_10g_interface_block__xdcDup__1__GC0 | 1| 7932| |189 |nf_10g_interface__xdcDup__1__GC0 | 1| 1789| |190 |nf_10g_interface_block__xdcDup__2__GC0 | 1| 7932| |191 |nf_10g_interface__xdcDup__2__GC0 | 1| 1789| |192 |nf_10g_interface_block__GC0 | 1| 7932| |193 |nf_10g_interface__GC0 | 1| 1789| |194 |top__GC0 | 1| 7748| |195 |TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple__1 | 2| 1607| |196 |TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple__2 | 2| 1605| |197 |TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple__3 | 6| 1523| |198 |TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple__4 | 2| 1475| +------+------------------------------------------------------------------------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met INFO: [Synth 8-4765] Removing register instance (\S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/rd_en_d1_reg ) from module (SimpleSumeSwitch__GCB3) as it is equivalent to (\S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/rd_en_d1_reg__0 ) and driving same net [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request.v:89] --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:39:14 ; elapsed = 00:39:26 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 1103 ; free virtual = 21524 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-5365] Flop stage_0/ErrorCheck_inst/validBits_i1_reg[10] is being inverted and renamed to stage_0/ErrorCheck_inst/validBits_i1_reg[10]_inv. INFO: [Synth 8-5365] Flop stage_0/ErrorCheck_inst/validBits_i1_reg[10] is being inverted and renamed to stage_0/ErrorCheck_inst/validBits_i1_reg[10]_inv. INFO: [Synth 8-6064] Net \stage_7/editor_inst/FifoWrField0Mask [31] is driving 164 big block pins (URAM, BRAM and DSP loads). Created 17 replicas of its driver. INFO: [Synth 8-6064] Net \stage_6/editor_inst/FifoWrField0Mask [47] is driving 224 big block pins (URAM, BRAM and DSP loads). Created 23 replicas of its driver. INFO: [Synth 8-6064] Net \stage_5/editor_inst/FifoWriter_inst/Field0Mask_2_reg[111]_rep__0_n_0 is driving 113 big block pins (URAM, BRAM and DSP loads). Created 12 replicas of its driver. INFO: [Synth 8-6064] Net \stage_5/editor_inst/FifoWriter_inst/FifoWrVal_reg_rep_n_0 is driving 108 big block pins (URAM, BRAM and DSP loads). Created 11 replicas of its driver. INFO: [Synth 8-6064] Net \stage_4/editor_inst/FifoWrField0Mask [23] is driving 162 big block pins (URAM, BRAM and DSP loads). Created 17 replicas of its driver. INFO: [Synth 8-5365] Flop inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT______TopDeparser_BACKPRESSURE_3_reg is being inverted and renamed to inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT______TopDeparser_BACKPRESSURE_3_reg_inv. INFO: [Synth 8-6064] Net \inst/wr_en [4] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver. INFO: [Synth 8-6064] Net \inst/wr_en [3] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver. INFO: [Synth 8-6064] Net \inst/wr_en [2] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver. INFO: [Synth 8-6064] Net \inst/wr_en [1] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver. INFO: [Synth 8-6064] Net \inst/wr_en [0] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-4618] Found max_fanout attribute set to 50 on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 . Fanout reduced from 697 to 155 by creating 11 replicas. INFO: [Synth 8-5778] max_fanout handling on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-4618] Found max_fanout attribute set to 50 on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 . Fanout reduced from 697 to 155 by creating 11 replicas. INFO: [Synth 8-5778] max_fanout handling on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-4618] Found max_fanout attribute set to 50 on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 . Fanout reduced from 697 to 155 by creating 11 replicas. INFO: [Synth 8-5778] max_fanout handling on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-4618] Found max_fanout attribute set to 50 on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 . Fanout reduced from 697 to 155 by creating 11 replicas. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3295] tying undriven pin m_axis_rx_tready_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin m_axis_rx_tready_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin m_axis_rx_tready_inferred:in0 to constant 0 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:39:53 ; elapsed = 00:40:05 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 1110 ; free virtual = 21530 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:39:57 ; elapsed = 00:40:09 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 1110 ; free virtual = 21531 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:40:55 ; elapsed = 00:41:07 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 1064 ; free virtual = 21486 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:40:56 ; elapsed = 00:41:08 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 1065 ; free virtual = 21487 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:42:07 ; elapsed = 00:42:21 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 1109 ; free virtual = 21531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:42:09 ; elapsed = 00:42:23 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 1109 ; free virtual = 21530 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+------------------------------------+----------+ | |BlackBox name |Instances | +------+------------------------------------+----------+ |1 |control_sub_xbar_0 | 1| |2 |control_sub_m00_data_fifo_0 | 1| |3 |control_sub_m01_data_fifo_0 | 1| |4 |control_sub_m02_data_fifo_0 | 1| |5 |control_sub_m03_data_fifo_0 | 1| |6 |control_sub_m04_data_fifo_0 | 1| |7 |control_sub_m05_data_fifo_0 | 1| |8 |control_sub_m06_data_fifo_0 | 1| |9 |control_sub_m07_data_fifo_0 | 1| |10 |control_sub_m08_data_fifo_0 | 1| |11 |control_sub_auto_cc_0 | 1| |12 |control_sub_s00_data_fifo_0 | 1| |13 |control_sub_axi_clock_converter_0_0 | 1| |14 |control_sub_axis_dwidth_dma_rx_0 | 1| |15 |control_sub_axis_dwidth_dma_tx_0 | 1| |16 |control_sub_axis_fifo_10g_rx_0 | 1| |17 |control_sub_axis_fifo_10g_tx_0 | 1| |18 |control_sub_nf_riffa_dma_1_0 | 1| |19 |control_sub_pcie3_7x_1_0 | 1| |20 |control_sub_pcie_reset_inv_0 | 1| |21 |control_sub_axi_iic_0_0 | 1| |22 |control_sub_axi_uartlite_0_0 | 1| |23 |control_sub_clk_wiz_1_0 | 1| |24 |control_sub_xbar_1 | 1| |25 |control_sub_mdm_1_0 | 1| |26 |control_sub_microblaze_0_0 | 1| |27 |control_sub_microblaze_0_axi_intc_0 | 1| |28 |control_sub_microblaze_0_xlconcat_0 | 1| |29 |control_sub_rst_clk_wiz_1_100M_0 | 1| |30 |control_sub_dlmb_bram_if_cntlr_0 | 1| |31 |control_sub_dlmb_v10_0 | 1| |32 |control_sub_ilmb_bram_if_cntlr_0 | 1| |33 |control_sub_ilmb_v10_0 | 1| |34 |control_sub_lmb_bram_0 | 1| +------+------------------------------------+----------+ Report Cell Usage: +------+------------------------------------+-------+ | |Cell |Count | +------+------------------------------------+-------+ |1 |control_sub_auto_cc_0 | 1| |2 |control_sub_axi_clock_converter_0_0 | 1| |3 |control_sub_axi_iic_0_0 | 1| |4 |control_sub_axi_uartlite_0_0 | 1| |5 |control_sub_axis_dwidth_dma_rx_0 | 1| |6 |control_sub_axis_dwidth_dma_tx_0 | 1| |7 |control_sub_axis_fifo_10g_rx_0 | 1| |8 |control_sub_axis_fifo_10g_tx_0 | 1| |9 |control_sub_clk_wiz_1_0 | 1| |10 |control_sub_dlmb_bram_if_cntlr_0 | 1| |11 |control_sub_dlmb_v10_0 | 1| |12 |control_sub_ilmb_bram_if_cntlr_0 | 1| |13 |control_sub_ilmb_v10_0 | 1| |14 |control_sub_lmb_bram_0 | 1| |15 |control_sub_m00_data_fifo_0 | 1| |16 |control_sub_m01_data_fifo_0 | 1| |17 |control_sub_m02_data_fifo_0 | 1| |18 |control_sub_m03_data_fifo_0 | 1| |19 |control_sub_m04_data_fifo_0 | 1| |20 |control_sub_m05_data_fifo_0 | 1| |21 |control_sub_m06_data_fifo_0 | 1| |22 |control_sub_m07_data_fifo_0 | 1| |23 |control_sub_m08_data_fifo_0 | 1| |24 |control_sub_mdm_1_0 | 1| |25 |control_sub_microblaze_0_0 | 1| |26 |control_sub_microblaze_0_axi_intc_0 | 1| |27 |control_sub_microblaze_0_xlconcat_0 | 1| |28 |control_sub_nf_riffa_dma_1_0 | 1| |29 |control_sub_pcie3_7x_1_0 | 1| |30 |control_sub_pcie_reset_inv_0 | 1| |31 |control_sub_rst_clk_wiz_1_100M_0 | 1| |32 |control_sub_s00_data_fifo_0 | 1| |33 |control_sub_xbar_0 | 1| |34 |control_sub_xbar_1 | 1| |35 |BUFG | 4| |36 |BUFGCE | 1| |37 |BUFH | 5| |38 |CARRY4 | 3278| |39 |FIFO36E1 | 4| |40 |FIFO36E1_1 | 4| |41 |GTHE2_CHANNEL | 4| |42 |GTHE2_COMMON | 1| |43 |IBUFDS_GTE2 | 2| |44 |LUT1 | 2563| |45 |LUT2 | 16856| |46 |LUT3 | 36554| |47 |LUT4 | 23813| |48 |LUT5 | 37345| |49 |LUT6 | 81139| |50 |MMCME2_ADV | 1| |51 |MUXCY_L | 176| |52 |MUXF7 | 1380| |53 |MUXF8 | 1| |54 |RAM128X1D | 24| |55 |RAM32M | 352| |56 |RAM64M | 186| |57 |RAM64X1D | 32| |58 |RAMB18E1_1 | 6| |59 |RAMB18E1_2 | 9| |60 |RAMB18E1_3 | 5| |61 |RAMB18E1_4 | 5| |62 |RAMB18E1_5 | 12| |63 |RAMB18E1_6 | 20| |64 |RAMB18E1_7 | 2| |65 |RAMB36E1_1 | 12| |66 |RAMB36E1_10 | 1| |67 |RAMB36E1_11 | 300| |68 |RAMB36E1_2 | 107| |69 |RAMB36E1_3 | 160| |70 |RAMB36E1_4 | 35| |71 |RAMB36E1_5 | 86| |72 |RAMB36E1_6 | 24| |73 |RAMB36E1_7 | 1| |74 |RAMB36E1_8 | 1| |75 |RAMB36E1_9 | 1| |76 |SRL16 | 1| |77 |SRL16E | 49561| |78 |SRLC32E | 6825| |79 |FDCE | 74| |80 |FDPE | 318| |81 |FDR | 8| |82 |FDRE | 338743| |83 |FDSE | 2693| |84 |LDCE | 4| |85 |IBUF | 27| |86 |IBUFDS | 1| |87 |IOBUF | 2| |88 |OBUF | 33| +------+------------------------------------+-------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:42:09 ; elapsed = 00:42:23 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 1109 ; free virtual = 21530 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 77640 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:33:16 ; elapsed = 00:35:02 . Memory (MB): peak = 10646.469 ; gain = 2084.918 ; free physical = 4322 ; free virtual = 24743 Synthesis Optimization Complete : Time (s): cpu = 00:42:10 ; elapsed = 00:42:26 . Memory (MB): peak = 10646.469 ; gain = 9315.387 ; free physical = 4358 ; free virtual = 24742 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 6265 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-35] Removing redundant IBUF, axi_clocking_i/clk_wiz_i/inst/clkin1_ibufg, from the path connected to top-level port: fpga_sysclk_p Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. INFO: [Opt 31-140] Inserted 8 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 8 OBUFs to IO ports without IO buffers. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 670 instances were transformed. (MUXCY,XORCY) => CARRY4: 64 instances BUFGCE => BUFGCTRL: 1 instances FDR => FDRE: 8 instances IOBUF => IOBUF (IBUF, OBUFT): 2 instances RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 24 instances RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 352 instances RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 186 instances RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 32 instances SRL16 => SRL16E: 1 instances INFO: [Common 17-83] Releasing license: Synthesis 1742 Infos, 908 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:43:41 ; elapsed = 00:43:53 . Memory (MB): peak = 10662.477 ; gain = 9331.395 ; free physical = 4737 ; free virtual = 25121 WARNING: [Constraints 18-5210] No constraint will be written out. INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/top.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:47 ; elapsed = 00:01:34 . Memory (MB): peak = 10686.488 ; gain = 24.012 ; free physical = 4652 ; free virtual = 25116 INFO: [runtcl-4] Executing : report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb report_utilization: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 10686.488 ; gain = 0.000 ; free physical = 4658 ; free virtual = 25121 INFO: [Common 17-206] Exiting Vivado at Mon Jul 29 18:08:51 2019... [Mon Jul 29 18:08:51 2019] synth finished wait_on_run: Time (s): cpu = 01:12:29 ; elapsed = 01:32:32 . Memory (MB): peak = 2879.363 ; gain = 0.000 ; free physical = 9575 ; free virtual = 28344 # launch_runs impl_1 -to_step write_bitstream [Mon Jul 29 18:08:53 2019] Launched synth_1... Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth_1/runme.log [Mon Jul 29 18:08:53 2019] Launched impl_1... Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/runme.log # wait_on_run impl_1 [Mon Jul 29 18:08:53 2019] Waiting for impl_1 to finish... *** Running vivado with args -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source top.tcl -notrace Command: link_design -top top -part xc7vx690tffg1761-3 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0.dcp' for cell 'control_sub_i/dma_sub/axi_clock_converter_0' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0.dcp' for cell 'control_sub_i/dma_sub/axis_dwidth_dma_rx' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0.dcp' for cell 'control_sub_i/dma_sub/axis_dwidth_dma_tx' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.dcp' for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.dcp' for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0.dcp' for cell 'control_sub_i/dma_sub/nf_riffa_dma_1' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0.dcp' for cell 'control_sub_i/dma_sub/pcie3_7x_1' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0.dcp' for cell 'control_sub_i/dma_sub/pcie_reset_inv' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_0/control_sub_xbar_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/xbar' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0.dcp' for cell 'control_sub_i/nf_mbsys/axi_iic_0' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.dcp' for cell 'control_sub_i/nf_mbsys/axi_uartlite_0' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.dcp' for cell 'control_sub_i/nf_mbsys/clk_wiz_1' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_xlconcat' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_1/control_sub_xbar_1.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_periph/xbar' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_lmb_bram_0/control_sub_lmb_bram_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram' INFO: [Netlist 29-17] Analyzing 7691 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2018.2 INFO: [Device 21-403] Loading part xc7vx690tffg1761-3 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_board.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_board.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1/U0' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc:50] get_clocks: Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 4365.883 ; gain = 1348.156 ; free physical = 6475 ; free virtual = 25231 Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_board.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_board.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1/inst' INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc:124] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc:57] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc] Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc] Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc] WARNING: [Constraints 18-619] A clock with name 'xphy_refclk_p' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:92] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:114] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:115] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:116] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:117] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:118] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:119] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:120] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:121] INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:149] get_clocks: Time (s): cpu = 00:00:18 ; elapsed = 00:00:08 . Memory (MB): peak = 5829.922 ; gain = 175.000 ; free physical = 5231 ; free virtual = 23987 Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc] Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_late.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_late.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_clocks.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_clocks.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Common 17-14] Message 'Vivado 12-3272' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Common 17-14] Message 'XPM_CDC_GRAY: TCL 1000' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/rc2oqgemebaubffc_998/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/rc2oqgemebaubffc_998/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/zmtz6gstdn71pkc38oscb260fx_746/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/zmtz6gstdn71pkc38oscb260fx_746/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xt6i6t0dtbr9k9ux4848l_2541/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xt6i6t0dtbr9k9ux4848l_2541/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ehndy8vbflb0gxuke3lnsjm_77/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ehndy8vbflb0gxuke3lnsjm_77/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xtsdogepbxcg3t8fqtbed8as0e1l_2610/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xtsdogepbxcg3t8fqtbed8as0e1l_2610/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Generating merged BMM file for the design top 'top'... INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/data/mb_bootloop_le.elf INFO: [Project 1-111] Unisim Transformation Summary: A total of 894 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 2 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 80 instances RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 24 instances RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 527 instances RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 195 instances RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 32 instances 148 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:03:47 ; elapsed = 00:04:10 . Memory (MB): peak = 6294.148 ; gain = 4962.141 ; free physical = 7011 ; free virtual = 25769 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 7010 ; free virtual = 25768 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 13a92017d Time (s): cpu = 00:00:39 ; elapsed = 00:00:14 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6432 ; free virtual = 25190 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 34 inverter(s) to 113 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 6f9e749d Time (s): cpu = 00:01:17 ; elapsed = 00:00:59 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6986 ; free virtual = 25744 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 17 inverter(s) to 49 load pin(s). Phase 2 Constant propagation | Checksum: d75d7ef6 Time (s): cpu = 00:01:45 ; elapsed = 00:01:27 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6986 ; free virtual = 25744 INFO: [Opt 31-389] Phase Constant propagation created 1514 cells and removed 21453 cells Phase 3 Sweep Phase 3 Sweep | Checksum: 15a267b85 Time (s): cpu = 00:02:40 ; elapsed = 00:02:22 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6990 ; free virtual = 25748 INFO: [Opt 31-389] Phase Sweep created 9 cells and removed 26640 cells Phase 4 BUFG optimization Phase 4 BUFG optimization | Checksum: 13d1ba485 Time (s): cpu = 00:02:48 ; elapsed = 00:02:30 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6989 ; free virtual = 25748 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 2 cells. Phase 5 Shift Register Optimization Phase 5 Shift Register Optimization | Checksum: 1aded50b2 Time (s): cpu = 00:03:05 ; elapsed = 00:02:47 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6992 ; free virtual = 25751 INFO: [Opt 31-389] Phase Shift Register Optimization created 1 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 11d6668c8 Time (s): cpu = 00:03:10 ; elapsed = 00:02:52 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6991 ; free virtual = 25749 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 20 cells Starting Connectivity Check Task Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.93 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6991 ; free virtual = 25749 Ending Logic Optimization Task | Checksum: 1a05f3302 Time (s): cpu = 00:03:13 ; elapsed = 00:02:55 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6992 ; free virtual = 25751 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.163 | TNS=0.000 | Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 1 BRAM(s) out of a total of 803 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 22 WE to EN ports Number of BRAM Ports augmented: 434 newly gated: 384 Total Ports: 1606 Ending PowerOpt Patch Enables Task | Checksum: 1e5cbfe33 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6369 ; free virtual = 25131 Ending Power Optimization Task | Checksum: 1e5cbfe33 Time (s): cpu = 00:05:33 ; elapsed = 00:02:02 . Memory (MB): peak = 7938.488 ; gain = 1644.340 ; free physical = 6853 ; free virtual = 25615 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 1194f7277 Time (s): cpu = 00:01:04 ; elapsed = 00:00:30 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6880 ; free virtual = 25642 Ending Final Cleanup Task | Checksum: 1194f7277 Time (s): cpu = 00:01:05 ; elapsed = 00:00:31 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6880 ; free virtual = 25642 INFO: [Common 17-83] Releasing license: Implementation 171 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:10:38 ; elapsed = 00:05:49 . Memory (MB): peak = 7938.488 ; gain = 1644.340 ; free physical = 6880 ; free virtual = 25642 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.07 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6859 ; free virtual = 25628 INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:48 ; elapsed = 00:01:36 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6778 ; free virtual = 25626 INFO: [runtcl-4] Executing : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Coretcl 2-168] The results of DRC are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:43 ; elapsed = 00:00:25 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6717 ; free virtual = 25567 Command: place_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'Explore' directive. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.49 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6716 ; free virtual = 25566 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a19b0e16 Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.58 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6715 ; free virtual = 25565 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.45 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6714 ; free virtual = 25564 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [Place 30-139] Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i (GTHE2_CHANNEL.TXOUTCLK) is locked to GTHE2_CHANNEL_X1Y23 control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 936073ee Time (s): cpu = 00:02:28 ; elapsed = 00:01:20 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6100 ; free virtual = 24953 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9feca4de Time (s): cpu = 00:04:48 ; elapsed = 00:02:30 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 5260 ; free virtual = 24114 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9feca4de Time (s): cpu = 00:04:49 ; elapsed = 00:02:31 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 5260 ; free virtual = 24114 Phase 1 Placer Initialization | Checksum: 9feca4de Time (s): cpu = 00:04:50 ; elapsed = 00:02:32 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 5260 ; free virtual = 24113 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: edf70a0e Time (s): cpu = 00:06:00 ; elapsed = 00:02:58 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4968 ; free virtual = 23822 Phase 2.2 Physical Synthesis In Placer WARNING: [Physopt 32-894] Found a constraint with the -through option on pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-76] Pass 1. Identified 30 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_reset_i/cpllreset. Replicated 15 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/valid_6. Replicated 11 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_3_reset. Replicated 13 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_3/E[0]. Replicated 11 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_4/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 12 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_18/E[0]. Replicated 13 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_19/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 11 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_15/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_16/E[0]. Replicated 12 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_7/E[0]. Replicated 12 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_3/valid_6. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_1/valid_6. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/tuple_in_TUPLE7_VALID. Replicated 12 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_22/E[0]. Replicated 12 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_6/MUX_TUPLE_p_reg[0]_0[0]. Replicated 13 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_0/TX_TUPLE_VALID. Replicated 13 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_0/valid_2. Replicated 11 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/valid_6. Replicated 13 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_23/E[0]. Replicated 11 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_25/valid_1. Replicated 11 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_4/valid_6. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/valid_6. Replicated 10 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/SS[0]. Replicated 14 times. WARNING: [Physopt 32-894] Found a constraint with the -through option on pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_3/tupleForward_inst/PktEop_d_1. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_3/valid_6. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_5/valid_6_reg_n_0_[0]. Replicated 9 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_6/valid_6. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_7/valid_6. Replicated 6 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_1/valid_6. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_8/valid_6. Replicated 5 times. INFO: [Physopt 32-232] Optimized 30 nets. Created 325 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 30 nets or cells. Created 325 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4855 ; free virtual = 23712 INFO: [Physopt 32-76] Pass 1. Identified 1 candidate net for fanout optimization. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/rd_cnt_reg[6]. Replicated 10 times. INFO: [Physopt 32-232] Optimized 1 net. Created 10 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 10 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.67 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4858 ; free virtual = 23714 INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7_i_1_n_0 could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7_i_1 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/wea[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__0 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/gen_wr_b.gen_word_narrow.mem_reg_0_1[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__2 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/gen_wr_b.gen_word_narrow.mem_reg_0_2[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__3 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_1_1[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_Hash_Lookup_inst/i_/xpm_memory_tdpram_inst_i_3 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/RamRwAddr[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_3 could not be replicated INFO: [Physopt 32-117] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/WEA0 could not be optimized because driver control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/rRAM_reg_0_i_1 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_1_1[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_Hash_Lookup_inst/i_/xpm_memory_tdpram_inst_i_5__0 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/RamRwAddr[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_2 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1_n_0 could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1 could not be replicated INFO: [Physopt 32-46] Identified 3 candidate nets for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4871 ; free virtual = 23727 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------- | Very High Fanout | 325 | 0 | 30 | 0 | 1 | 00:00:39 | | Fanout | 10 | 0 | 1 | 0 | 1 | 00:00:01 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 335 | 0 | 31 | 0 | 3 | 00:00:40 | ----------------------------------------------------------------------------------------------------------------------------- Phase 2.2 Physical Synthesis In Placer | Checksum: 1fff03ad0 Time (s): cpu = 00:18:08 ; elapsed = 00:08:23 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4864 ; free virtual = 23721 Phase 2 Global Placement | Checksum: 181c1f290 Time (s): cpu = 00:18:39 ; elapsed = 00:08:37 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 5079 ; free virtual = 23935 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 181c1f290 Time (s): cpu = 00:18:43 ; elapsed = 00:08:38 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4944 ; free virtual = 23801 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1721c486f Time (s): cpu = 00:22:15 ; elapsed = 00:09:40 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4579 ; free virtual = 23435 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1432aceee Time (s): cpu = 00:22:21 ; elapsed = 00:09:44 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4578 ; free virtual = 23435 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 105513320 Time (s): cpu = 00:22:22 ; elapsed = 00:09:45 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4578 ; free virtual = 23434 Phase 3.5 Timing Path Optimizer Phase 3.5 Timing Path Optimizer | Checksum: 105513320 Time (s): cpu = 00:22:23 ; elapsed = 00:09:46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4578 ; free virtual = 23434 Phase 3.6 Fast Optimization Phase 3.6 Fast Optimization | Checksum: 16fb6183b Time (s): cpu = 00:22:30 ; elapsed = 00:09:52 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4578 ; free virtual = 23434 Phase 3.7 Small Shape Detail Placement Phase 3.7 Small Shape Detail Placement | Checksum: 4af46697 Time (s): cpu = 00:25:20 ; elapsed = 00:12:26 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4172 ; free virtual = 23029 Phase 3.8 Re-assign LUT pins Phase 3.8 Re-assign LUT pins | Checksum: a7bddef5 Time (s): cpu = 00:25:32 ; elapsed = 00:12:37 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4189 ; free virtual = 23046 Phase 3.9 Pipeline Register Optimization Phase 3.9 Pipeline Register Optimization | Checksum: f7c3441a Time (s): cpu = 00:25:35 ; elapsed = 00:12:41 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4194 ; free virtual = 23051 Phase 3 Detail Placement | Checksum: f7c3441a Time (s): cpu = 00:25:38 ; elapsed = 00:12:44 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4197 ; free virtual = 23054 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1f9ab725f Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-33] Processed net nf_datapath_0/input_arbiter_v1_0/inst/in_arb_queues[3].in_arb_fifo/fifo/SR[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_1_reset, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[2].output_fifo/fifo/SR[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_3/tupleForward_inst/Enable_d_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_22/valid_2, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_1/E[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20/E[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_21/MUX_TUPLE_p_reg[1402]_0[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_17/MUX_TUPLE_p_reg[1402]_0[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_9/E[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_14/E[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_13/valid_2, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_12/MUX_TUPLE_p_reg[1402]_0[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_11/E[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_10/MUX_TUPLE_p_reg[1402]_0[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_8/MUX_TUPLE_p_reg[1402]_0[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/tuple_out_TUPLE0_VALID, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_5/E[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl/TopPipe_lvl_t_inst/stage_0/valid_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/tuple_out_TUPLE6_VALID, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2_reset, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2/tupleForward_inst/Enable_d_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_3/tupleForward_inst/OutTupDat[3947]_i_1__1_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_4/valid_6, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2/valid_6, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2/tupleForward_inst/OutTupDat[3947]_i_1__0_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_1/tupleForward_inst/PktEop_d_1_i_1__0_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_1/tupleForward_inst/Enable_d_2, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_1/tupleForward_inst/OutTupDat[3947]_i_1_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-31] BUFG insertion identified 33 candidate nets, 0 success, 33 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. Phase 4.1.1.1 BUFG Insertion | Checksum: 1f9ab725f Time (s): cpu = 00:28:20 ; elapsed = 00:13:35 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4576 ; free virtual = 23433 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.674. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 176ec2ee4 Time (s): cpu = 00:35:05 ; elapsed = 00:18:43 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4516 ; free virtual = 23373 Phase 4.1 Post Commit Optimization | Checksum: 176ec2ee4 Time (s): cpu = 00:35:09 ; elapsed = 00:18:47 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4515 ; free virtual = 23373 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 176ec2ee4 Time (s): cpu = 00:35:14 ; elapsed = 00:18:50 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4531 ; free virtual = 23388 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 176ec2ee4 Time (s): cpu = 00:35:17 ; elapsed = 00:18:54 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4534 ; free virtual = 23392 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 187a25870 Time (s): cpu = 00:35:20 ; elapsed = 00:18:57 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4536 ; free virtual = 23393 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 187a25870 Time (s): cpu = 00:35:23 ; elapsed = 00:18:59 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4536 ; free virtual = 23393 Ending Placer Task | Checksum: 156291874 Time (s): cpu = 00:35:23 ; elapsed = 00:19:00 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 5082 ; free virtual = 23939 INFO: [Common 17-83] Releasing license: Implementation 275 Infos, 160 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:35:53 ; elapsed = 00:19:28 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 5082 ; free virtual = 23939 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:45 ; elapsed = 00:00:18 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4249 ; free virtual = 23828 INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:16 ; elapsed = 00:01:43 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4913 ; free virtual = 23934 INFO: [runtcl-4] Executing : report_io -file top_io_placed.rpt report_io: Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.42 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4873 ; free virtual = 23894 INFO: [runtcl-4] Executing : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb report_utilization: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4921 ; free virtual = 23942 report_utilization: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4921 ; free virtual = 23942 INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4920 ; free virtual = 23944 Command: phys_opt_design -directive ExploreWithHoldFix Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: ExploreWithHoldFix Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.48 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4781 ; free virtual = 23805 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.674 | TNS=-358.591 | Phase 1 Physical Synthesis Initialization | Checksum: e30ca06c Time (s): cpu = 00:03:05 ; elapsed = 00:00:58 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4532 ; free virtual = 23556 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.674 | TNS=-358.591 | Phase 2 Fanout Optimization INFO: [Physopt 32-76] Pass 1. Identified 13 candidate nets for fanout optimization. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady. Replicated 2 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][0]_0[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/will_update_dout. Replicated 1 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_1[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/will_update_middle. Replicated 2 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_0[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_3[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_2[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-601] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/WEBWE[0]. Net driver control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/rRAM_reg_0_i_1__2 was replaced. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_alignment_inst/gen_data_input_regs[3].data_register_/pipeline_inst/gen_stages[1].rData_reg[1][0][0]. Replicated 1 times. INFO: [Physopt 32-232] Optimized 5 nets. Created 6 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 5 nets or cells. Created 6 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.589 | TNS=-260.852 | Netlist sorting complete. Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.50 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4543 ; free virtual = 23568 Phase 2 Fanout Optimization | Checksum: 15e721c17 Time (s): cpu = 00:03:40 ; elapsed = 00:01:14 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4543 ; free virtual = 23567 Phase 3 Placement Based Optimization INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization. INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/sel. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/rCtrValue[0]_i_2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rValid[1]_i_2 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[0] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[1]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[1] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[2]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[2] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[3]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[3] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_1[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData[1][32]_i_1__1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_pipeline_inst_/pipeline_inst/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_6 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter[3]_i_4 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[2] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[3] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/clear. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/rCtrValue[0]_i_1 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[7]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[7] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[5]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[5] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[6]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[6] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_0[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData[1][32]_i_1__0 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg_0[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg_i_2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[10] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[8] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[9] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[12] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rRdPtrPlus1[2]_i_1__15 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][52]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[60] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][53]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[61] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][54]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[62] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][55]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[63] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][56]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[64] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][57]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[65] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][0]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter_reg[0]_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter[3]_i_9 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter[3]_i_8 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[127]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][153] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][99] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][64]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[72] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][65]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[73] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][66]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[74] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][67]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[75] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][68]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[76] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][69]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[77] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[107]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][115] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][20]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][28] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[33]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][41] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][82] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg_0[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg_i_2__0 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[64]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][72] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[65]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][73] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[52]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][60] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[53]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][61] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][3]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[11] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_2[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData[1][32]_i_1__2 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg_0[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg_i_2__1 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/rRdPtr_reg_n_0_[9]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/rRdPtr_reg[9] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][35] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][57]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][65] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][59]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][67] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[129]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][155] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][13] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][46]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[54] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][47]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[55] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][48]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][51]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[59] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[130]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][156] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[80]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][88] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][23]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][31] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_3[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData[1][32]_i_1__3 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_i_2__2 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/rRdPtrPlus1_reg__0[7]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/rRdPtrPlus1_reg[7] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/rRdPtrPlus1_reg__0[8]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/rRdPtrPlus1_reg[8] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][36]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[44] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/will_update_dout. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/dout[128]_i_1 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/will_update_middle_repN_1. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout[128]_i_1_replica_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/WR_FULL. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rFull_reg INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/fifo_rden__0. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/dout[128]_i_3 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/chnl_tx_data_ren[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/CHNL_TX_DATA_REN INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[125]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[125] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[19] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[64]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[64] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[66] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][72]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[80] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][73]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[81] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][75]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[83] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][18] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][19] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][20] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[14]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][22] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[15]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][23] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[89]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][97] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][86]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[94] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[63]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][71] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[127]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[21]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[22]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[22] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[24]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[63]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[63] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[65]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[65] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[92]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[99] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][3]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][11] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][115]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][129] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][117]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][131] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][124]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][150] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][13]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][94]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][95]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][115]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[129] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[131] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[11]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[11] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[20]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[20] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[29]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[29] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[34]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[34] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[45]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[45] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[60]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[60] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[69]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[69] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[70]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[70] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[32]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[32] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[3] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[62]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[62] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[75]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[81]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[81] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][4]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[12] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[1] INFO: [Physopt 32-661] Optimized 53 nets. Re-placed 53 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 53 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 53 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-198.963 | Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4438 ; free virtual = 23463 Phase 3 Placement Based Optimization | Checksum: 1a1c2cd81 Time (s): cpu = 00:05:06 ; elapsed = 00:01:32 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4437 ; free virtual = 23462 Phase 4 MultiInst Placement Optimization INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica/O INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter_reg[0]_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter[3]_i_9/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter[3]_i_8/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter[3]_i_4/O INFO: [Physopt 32-661] Optimized 1 net. Re-placed 4 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 0 new cell, deleted 0 existing cell and moved 4 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-201.792 | Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4437 ; free virtual = 23462 Phase 4 MultiInst Placement Optimization | Checksum: 1a6fa4497 Time (s): cpu = 00:05:46 ; elapsed = 00:01:45 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4437 ; free virtual = 23462 Phase 5 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-77] Pass 1. Identified 1 candidate net for rewire optimization. INFO: [Physopt 32-134] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Rewiring did not optimize the net. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4430 ; free virtual = 23455 Netlist sorting complete. Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.47 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4430 ; free virtual = 23455 Phase 5 Rewire | Checksum: 120508df8 Time (s): cpu = 00:05:51 ; elapsed = 00:01:48 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4429 ; free virtual = 23454 Phase 6 Critical Cell Optimization INFO: [Physopt 32-46] Identified 12 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]. Replicated 1 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/clear was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/monitor/_rState. Replicated 1 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/monitor/wBufWen. Replicated 2 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg_0[0]. Replicated 1 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_0[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/intr/Q[5]. Replicated 1 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/intr/Q[0]. Replicated 1 times. INFO: [Physopt 32-601] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/sel. Net driver control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/rCtrValue[0]_i_2 was replaced. INFO: [Physopt 32-232] Optimized 7 nets. Created 7 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 7 nets or cells. Created 7 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-194.096 | Netlist sorting complete. Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.73 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4430 ; free virtual = 23455 Phase 6 Critical Cell Optimization | Checksum: 11ab67e90 Time (s): cpu = 00:06:15 ; elapsed = 00:01:58 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4430 ; free virtual = 23455 Phase 7 Fanout Optimization INFO: [Physopt 32-76] Pass 1. Identified 9 candidate nets for fanout optimization. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_3[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_0[0]. Replicated 2 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/E[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1_n_0. Replicated 2 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_alignment_inst/gen_data_input_regs[3].data_register_/pipeline_inst/gen_stages[1].rData_reg[1][0][0]_repN was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/will_update_middle_repN_1. Replicated 1 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/will_update_dout. Replicated 1 times. INFO: [Physopt 32-232] Optimized 4 nets. Created 6 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 4 nets or cells. Created 6 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-192.855 | Netlist sorting complete. Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.51 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4430 ; free virtual = 23455 Phase 7 Fanout Optimization | Checksum: 106376d48 Time (s): cpu = 00:06:30 ; elapsed = 00:02:06 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4429 ; free virtual = 23454 Phase 8 Placement Based Optimization INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][0]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[127]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][153] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][99] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[107]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][115] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][20]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][28] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[33]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][41] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[64]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][72] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[65]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][73] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[52]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][60] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[53]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][61] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter_reg[0]_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter[3]_i_9 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter[3]_i_8 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter[3]_i_4 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[2] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[3] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][35] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][57]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][65] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][59]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][67] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[129]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][155] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rRdPtrPlus1[2]_i_1__15 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][51]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[59] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[130]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][156] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[80]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][88] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][23]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][31] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][48]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][69]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[77] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][36]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[44] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][72]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[80] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][73]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[81] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][75]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[83] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][18] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][19] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][20] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[14]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][22] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[15]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][23] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[89]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][97] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][86]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[94] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[63]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][71] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][115]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[129] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][4]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[12] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[2] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[25]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][33] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][35] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[48]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[88]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][96] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][113] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][118]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][144] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][123]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][149] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][100]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][108] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][31]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][39] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][88]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][96] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/_rEmpty. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/rEmpty_i_1__18 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/rEmpty. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/rEmpty_reg INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/clear. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/rCtrValue[0]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rValid[1]_i_2 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[0] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[1]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[1] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[2]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[2] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[3]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[3] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[2]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[14] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[12]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[12] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[13]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[13] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][3]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][11] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][115]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][129] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][117]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][131] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][124]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][150] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][130]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[156] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[157] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[5] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[6] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[7] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[10] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[8] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[9] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][80]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[88] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][81]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[89] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][113] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[115]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][129] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[118]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][144] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[119]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][145] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[120]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][146] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[121]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][147] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[123]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][149] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[125]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][151] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[36]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][44] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[51]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][59] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[62]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][70] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[25] INFO: [Physopt 32-661] Optimized 13 nets. Re-placed 13 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 13 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 13 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-191.578 | Netlist sorting complete. Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4429 ; free virtual = 23454 Phase 8 Placement Based Optimization | Checksum: 1a3cf0378 Time (s): cpu = 00:07:54 ; elapsed = 00:02:23 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 9 MultiInst Placement Optimization INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter_reg[0]_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter[3]_i_9/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter[3]_i_8/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter[3]_i_4/O INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 9 MultiInst Placement Optimization | Checksum: 1a0aac06d Time (s): cpu = 00:08:54 ; elapsed = 00:02:40 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4427 ; free virtual = 23453 Phase 10 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-241] No nets found for rewiring () optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.45 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4429 ; free virtual = 23455 Phase 10 Rewire | Checksum: 1a0aac06d Time (s): cpu = 00:08:56 ; elapsed = 00:02:42 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4429 ; free virtual = 23454 Phase 11 Critical Cell Optimization INFO: [Physopt 32-46] Identified 10 candidate nets for critical-cell optimization. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/clear. Replicated 1 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-601] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/monitor/_rState_repN. Net driver control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/monitor/rState[4]_i_1__4_replica was replaced. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/monitor/rState[4]_i_3__0_n_0. Replicated 1 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/monitor/_rState. Replicated 1 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-601] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]_repN. Net driver control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_i_2__2_replica was replaced. INFO: [Physopt 32-232] Optimized 5 nets. Created 3 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 5 nets or cells. Created 3 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-195.879 | Netlist sorting complete. Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.52 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4429 ; free virtual = 23454 Phase 11 Critical Cell Optimization | Checksum: 1d84a5101 Time (s): cpu = 00:09:15 ; elapsed = 00:02:50 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 12 Slr Crossing Optimization Phase 12 Slr Crossing Optimization | Checksum: 1d84a5101 Time (s): cpu = 00:09:16 ; elapsed = 00:02:50 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 13 Fanout Optimization INFO: [Physopt 32-76] Pass 1. Identified 3 candidate nets for fanout optimization. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_3[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1_n_0_repN_1. Replicated 2 times. INFO: [Physopt 32-232] Optimized 1 net. Created 2 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 2 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-190.970 | Netlist sorting complete. Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.47 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 13 Fanout Optimization | Checksum: 14b1a292e Time (s): cpu = 00:09:25 ; elapsed = 00:02:56 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 14 Placement Based Optimization INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][0]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[127]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][153] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][99] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[107]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][115] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][108]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][109]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][131]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][20]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][28] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[33]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][41] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[64]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][72] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[65]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][73] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[52]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][60] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[53]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][61] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter_reg[0]_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter[3]_i_9 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter[3]_i_8 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter[3]_i_4 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[2] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[3] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][35] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][57]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][65] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][59]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][67] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[129]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][155] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rRdPtrPlus1[2]_i_1__15 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][51]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[59] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[130]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][156] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[80]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][88] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][23]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][31] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][48]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][69]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[77] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][36]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[44] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][72]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[80] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][73]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[81] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][75]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[83] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][18] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][19] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][20] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[14]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][22] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[15]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][23] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[89]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][97] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][86]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[94] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[63]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][71] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][115]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[129] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][4]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[12] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[2] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[25]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][33] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][35] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[48]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[88]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][96] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][113] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][118]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][144] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][123]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][149] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][100]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][108] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][31]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][39] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][88]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][96] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/_rEmpty. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/rEmpty_i_1__18 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/rEmpty. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/rEmpty_reg INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][130]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[156] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][80]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[88] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][81]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[89] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][113] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[115]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][129] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[118]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][144] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[119]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][145] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[120]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][146] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[121]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][147] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[123]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][149] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[125]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][151] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[36]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][44] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[51]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][59] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[62]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][70] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][20]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[28] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][21]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[29] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/S[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag_carry__0_i_5 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[69]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][77] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[72]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][80] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[73]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][81] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[75]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][83] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[81]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][89] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/sel. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/rCtrValue[0]_i_2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rValid[1]_i_2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[12] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[13] INFO: [Physopt 32-661] Optimized 6 nets. Re-placed 6 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 6 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 6 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-187.768 | Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.47 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23455 Phase 14 Placement Based Optimization | Checksum: 135273a80 Time (s): cpu = 00:10:50 ; elapsed = 00:03:13 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 15 MultiInst Placement Optimization INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter_reg[0]_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter[3]_i_9/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter[3]_i_8/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter[3]_i_4/O INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 15 MultiInst Placement Optimization | Checksum: 150e4a12b Time (s): cpu = 00:11:48 ; elapsed = 00:03:30 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4427 ; free virtual = 23454 Phase 16 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-241] No nets found for rewiring () optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23455 Phase 16 Rewire | Checksum: 150e4a12b Time (s): cpu = 00:11:50 ; elapsed = 00:03:32 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 17 Critical Cell Optimization INFO: [Physopt 32-46] Identified 5 candidate nets for critical-cell optimization. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/clear_repN was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23455 Phase 17 Critical Cell Optimization | Checksum: 1848f61fc Time (s): cpu = 00:12:00 ; elapsed = 00:03:37 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 18 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 18 DSP Register Optimization | Checksum: 1848f61fc Time (s): cpu = 00:12:01 ; elapsed = 00:03:37 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 19 BRAM Register Optimization INFO: [Physopt 32-665] Processed cell nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/PktFifo_inst/RAM/RAM_reg_3. 72 registers were pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 72 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-187.768 | Netlist sorting complete. Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.69 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 19 BRAM Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:35 ; elapsed = 00:04:04 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 20 URAM Register Optimization INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 20 URAM Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:36 ; elapsed = 00:04:04 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 21 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 21 Shift Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:37 ; elapsed = 00:04:06 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 22 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 22 DSP Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:38 ; elapsed = 00:04:06 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 23 BRAM Register Optimization INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 23 BRAM Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:39 ; elapsed = 00:04:07 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 24 URAM Register Optimization INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 24 URAM Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:40 ; elapsed = 00:04:08 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 25 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 25 Shift Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:41 ; elapsed = 00:04:09 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 26 Critical Pin Optimization INFO: [Physopt 32-606] Identified 11 candidate nets for critical-pin optimization. INFO: [Physopt 32-608] Optimized 5 nets. Swapped 69 pins. INFO: [Physopt 32-775] End 1 Pass. Optimized 5 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 69 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.343 | TNS=-94.073 | Netlist sorting complete. Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.47 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23418 Phase 26 Critical Pin Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:43 ; elapsed = 00:04:12 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 27 Very High Fanout Optimization INFO: [Physopt 32-76] Pass 1. Identified 100 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/rRst. Replicated 3 times. INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_6/MUX_TUPLE_p[1402]_i_3_n_0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_6/MUX_TUPLE_p[1402]_i_2_n_0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_1_reset was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_22/valid_2. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_1/E[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20/E[0]. Replicated 6 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_17/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_21/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_10/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 4 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_11/E[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_12/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_13/valid_2. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_14/E[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_9/E[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_8/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 5 times. INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/tuple_out_TUPLE0_VALID was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_5/E[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl/TopPipe_lvl_t_inst/stage_0/valid_1. Replicated 4 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2_reset. Replicated 4 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_4/valid_6. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_4/p_0_in[1]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_4/p_0_in[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_4/p_0_in[2]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2/tupleForward_inst/PktEop_d_1. Replicated 3 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2/valid_6. Replicated 4 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_4/p_0_in[3]. Replicated 4 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_10/valid_6. Replicated 2 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_9/valid_6. Replicated 2 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_11/valid_6. Replicated 2 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_0/data_i8_reg[446]_0[2]. Replicated 1 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/rRst was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_RESET_clk_line/clk_line_rst_high. Replicated 1 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/user_reset. Replicated 2 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_0/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_1/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_2/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_3/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_4/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_5/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_6/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_7/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_0/data_i8_reg[446]_0[3]. Replicated 1 times. INFO: [Physopt 32-232] Optimized 38 nets. Created 126 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 38 nets or cells. Created 126 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.343 | TNS=-94.073 | Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4397 ; free virtual = 23424 Phase 27 Very High Fanout Optimization | Checksum: d67452a7 Time (s): cpu = 00:19:26 ; elapsed = 00:07:57 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4396 ; free virtual = 23423 Phase 28 Placement Based Optimization INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][35] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][57]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][65] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][59]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][67] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rRdPtrPlus1[2]_i_1__15 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][51]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[59] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][23]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][31] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][48]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][69]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[77] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][36]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[44] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][72]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[80] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][73]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[81] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][75]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[83] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][86]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[94] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][115]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[129] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][4]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[12] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[2] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][113] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][118]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][144] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][123]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][149] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][100]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][108] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][31]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][39] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][88]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][96] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/S[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag_carry__0_i_5 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][20]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][28] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/gen_stages[1].rData_reg[1][2]_0[1]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/_wTxMuxSelectDataEndFlag_carry__0_i_7 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][130]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[156] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/WR_FULL. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rFull_reg INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wCmpFull. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rFull2_i_1__0 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/WEA0. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/rRAM_reg_0_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rFull_i_1__4_n_0. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rFull_i_1__4 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][80]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[88] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][81]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[89] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/gen_stages[1].rData_reg[1][2]_0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag_carry__0_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][0]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][20]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[28] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][21]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[29] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[127]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][153] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][99] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[107]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][115] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/gen_stages[1].rData_reg[1][2]_0[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/_wTxMuxSelectDataEndFlag_carry__0_i_6 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][124]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[150] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][125]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[151] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][127]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[153] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][129]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[155] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][18] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][19] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][20] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][14]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][22] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][15]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][23] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/gen_stages[1].rData_reg[1][2]_0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag_carry__0_i_3 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[18] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[19] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[20] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][14]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[22] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][15]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[23] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][21]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][29] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[33]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][41] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][100]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[108] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][101]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[109] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][102]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[110] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][103]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[111] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][104]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[112] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[113] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][118]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[144] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][119]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[145] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][120]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[146] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][121]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[147] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][123]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[149] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][88]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[96] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][89]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[97] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[99] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][92]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[100] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][26]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][34] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][48]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][53]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][61] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][99] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][107]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[115] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[64]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][72] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[65]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][73] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/gen_stages[1].rData_reg[1][2]_0[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag_carry__0_i_2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[52]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][60] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[53]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][61] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rValid[1]_i_2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/clear_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/rCtrValue[0]_i_1_replica INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[10] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[5] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[6] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[7] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[8] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[9] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][29]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[37] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][30]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[38] INFO: [Physopt 32-661] Optimized 3 nets. Re-placed 3 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 3 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 3 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.343 | TNS=-93.822 | Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4396 ; free virtual = 23423 Phase 28 Placement Based Optimization | Checksum: b86b36dc Time (s): cpu = 00:20:54 ; elapsed = 00:08:15 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4395 ; free virtual = 23423 Phase 29 MultiInst Placement Optimization INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica/O INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.45 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4395 ; free virtual = 23423 Phase 29 MultiInst Placement Optimization | Checksum: 16aa3538e Time (s): cpu = 00:21:07 ; elapsed = 00:08:21 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4395 ; free virtual = 23423 Phase 30 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.343 | TNS=-93.822 | INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Optimizations did not improve timing on the net. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1 INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1/O INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica/O INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/s_axis_rq_tready[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1 INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1/O INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica/O INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/s_axis_rq_tready[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1. Optimizations did not improve timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.343 | TNS=-93.822 | Phase 30 Critical Path Optimization | Checksum: 1a0b8e714 Time (s): cpu = 00:21:51 ; elapsed = 00:08:33 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4395 ; free virtual = 23423 Phase 31 BRAM Enable Optimization Phase 31 BRAM Enable Optimization | Checksum: 1a0b8e714 Time (s): cpu = 00:21:53 ; elapsed = 00:08:35 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4396 ; free virtual = 23424 Phase 32 Hold Fix Optimization INFO: [Physopt 32-668] Estimated Timing Summary | WNS=-0.343 | TNS=-93.822 | WHS=-0.388 | THS=-1352.976 | INFO: [Physopt 32-45] Identified 329 candidate nets for hold slack optimization. INFO: [Physopt 32-234] Optimized 323 nets. Inserted 0 new ZHOLD_DELAYs. Calibrated 0 existing ZHOLD_DELAYs. Inserted 323 buffers. INFO: [Physopt 32-668] Estimated Timing Summary | WNS=-0.343 | TNS=-93.822 | WHS=-0.324 | THS=-1260.569 | Phase 32 Hold Fix Optimization | Checksum: 183b13308 Time (s): cpu = 00:23:12 ; elapsed = 00:08:56 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4263 ; free virtual = 23290 Netlist sorting complete. Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.72 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4276 ; free virtual = 23304 INFO: [Physopt 32-669] Post Physical Optimization Timing Summary | WNS=-0.343 | TNS=-93.822 | WHS=-0.324 | THS=-1260.569 | Summary of Physical Synthesis Optimizations ============================================ -------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | -------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Fanout | 0.085 | 103.889 | 14 | 0 | 10 | 3 | 3 | 00:00:22 | | Placement Based | 0.085 | 66.619 | 0 | 0 | 75 | 0 | 4 | 00:01:06 | | MultiInst Placement | 0.000 | -2.828 | 0 | 0 | 1 | 0 | 4 | 00:00:48 | | Rewire | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 3 | 00:00:03 | | Critical Cell | 0.000 | 3.394 | 10 | 0 | 12 | 0 | 3 | 00:00:19 | | Slr Crossing | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 | | BRAM Register | 0.000 | 0.000 | 72 | 0 | 1 | 0 | 2 | 00:00:25 | | URAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 | | Shift Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:01 | | Critical Pin | 0.161 | 93.695 | 0 | 0 | 5 | 0 | 1 | 00:00:01 | | Very High Fanout | 0.000 | 0.000 | 126 | 0 | 38 | 2 | 1 | 00:03:43 | | BRAM Enable | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | Critical Path | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:11 | | Total | 0.331 | 264.769 | 222 | 0 | 142 | 5 | 30 | 00:07:00 | -------------------------------------------------------------------------------------------------------------------------------------------------------------------- Summary of Hold Fix Optimizations ================================= -------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WHS Gain (ns) | THS Gain (ns) | Added LUTs | Added FFs | Optimized Nets | Dont Touch | Iterations | Elapsed | -------------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT1 and ZHOLD Insertion | 0.063 | 92.407 | 323 | 0 | 323 | 0 | 1 | 00:00:09 | | Total | 0.063 | 92.407 | 323 | 0 | 323 | 0 | 1 | 00:00:09 | -------------------------------------------------------------------------------------------------------------------------------------------------------------- Ending Physical Synthesis Task | Checksum: 5536e89c Time (s): cpu = 00:23:13 ; elapsed = 00:08:57 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4276 ; free virtual = 23304 INFO: [Common 17-83] Releasing license: Implementation 1524 Infos, 160 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:25:52 ; elapsed = 00:09:41 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4709 ; free virtual = 23737 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:45 ; elapsed = 00:00:18 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4021 ; free virtual = 23756 INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:16 ; elapsed = 00:01:44 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4653 ; free virtual = 23844 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-18] Clock Placer Checks: Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i (GTHE2_CHANNEL.TXOUTCLK) is locked to GTHE2_CHANNEL_X1Y23 control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: ec95d42 ConstDB: 0 ShapeSum: 383ba574 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 13f77aa3a Time (s): cpu = 00:01:01 ; elapsed = 00:01:01 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4500 ; free virtual = 23690 Post Restoration Checksum: NetGraph: 755780cb NumContArr: ca20296f Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 13f77aa3a Time (s): cpu = 00:01:13 ; elapsed = 00:01:13 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4503 ; free virtual = 23694 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 13f77aa3a Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4424 ; free virtual = 23615 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 13f77aa3a Time (s): cpu = 00:01:18 ; elapsed = 00:01:18 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4424 ; free virtual = 23615 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 24991dd09 Time (s): cpu = 00:04:36 ; elapsed = 00:02:25 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4172 ; free virtual = 23363 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.137 | TNS=-4.317 | WHS=-0.904 | THS=-29817.598| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 226928804 Time (s): cpu = 00:07:11 ; elapsed = 00:03:05 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4122 ; free virtual = 23313 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.137 | TNS=-4.005 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 1be59df93 Time (s): cpu = 00:07:12 ; elapsed = 00:03:06 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4095 ; free virtual = 23287 Phase 2 Router Initialization | Checksum: 231d14d05 Time (s): cpu = 00:07:13 ; elapsed = 00:03:07 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4094 ; free virtual = 23286 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 1d7b67090 Time (s): cpu = 00:12:57 ; elapsed = 00:04:23 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4053 ; free virtual = 23245 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 31705 Number of Nodes with overlaps = 1870 Number of Nodes with overlaps = 382 Number of Nodes with overlaps = 83 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.264 | TNS=-26.695| WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1b6f39fbc Time (s): cpu = 00:26:00 ; elapsed = 00:07:21 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4055 ; free virtual = 23247 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 107 Number of Nodes with overlaps = 65 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.291 | TNS=-25.694| WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: cb56b2be Time (s): cpu = 00:27:50 ; elapsed = 00:08:12 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4049 ; free virtual = 23241 Phase 4 Rip-up And Reroute | Checksum: cb56b2be Time (s): cpu = 00:27:51 ; elapsed = 00:08:13 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4049 ; free virtual = 23241 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 9825de82 Time (s): cpu = 00:28:25 ; elapsed = 00:08:21 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4028 ; free virtual = 23220 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.185 | TNS=-11.111| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 22b0ba517 Time (s): cpu = 00:28:33 ; elapsed = 00:08:24 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4029 ; free virtual = 23221 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 22b0ba517 Time (s): cpu = 00:28:34 ; elapsed = 00:08:25 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4029 ; free virtual = 23221 Phase 5 Delay and Skew Optimization | Checksum: 22b0ba517 Time (s): cpu = 00:28:35 ; elapsed = 00:08:26 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4029 ; free virtual = 23221 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 197b1443d Time (s): cpu = 00:29:12 ; elapsed = 00:08:36 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4033 ; free virtual = 23225 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.186 | TNS=-11.250| WHS=-0.074 | THS=-0.329 | Phase 6.1 Hold Fix Iter | Checksum: 2158f047e Time (s): cpu = 00:29:23 ; elapsed = 00:08:39 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4012 ; free virtual = 23204 Phase 6 Post Hold Fix | Checksum: 24c84397d Time (s): cpu = 00:29:24 ; elapsed = 00:08:41 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4012 ; free virtual = 23204 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 20.5735 % Global Horizontal Routing Utilization = 20.3181 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 2x2 Area, Max Cong = 88.2883%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X132Y258 -> INT_R_X133Y259 INT_L_X130Y254 -> INT_R_X131Y255 INT_L_X130Y252 -> INT_R_X131Y253 INT_L_X130Y250 -> INT_R_X131Y251 South Dir 2x2 Area, Max Cong = 89.1892%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X132Y248 -> INT_R_X133Y249 INT_L_X132Y246 -> INT_R_X133Y247 INT_L_X132Y244 -> INT_R_X133Y245 East Dir 1x1 Area, Max Cong = 92.6471%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X59Y454 -> INT_R_X59Y454 INT_R_X65Y428 -> INT_R_X65Y428 INT_L_X62Y425 -> INT_L_X62Y425 INT_L_X64Y425 -> INT_L_X64Y425 INT_R_X65Y425 -> INT_R_X65Y425 West Dir 1x1 Area, Max Cong = 92.6471%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X21Y374 -> INT_R_X21Y374 INT_R_X27Y368 -> INT_R_X27Y368 INT_R_X23Y366 -> INT_R_X23Y366 INT_L_X78Y342 -> INT_L_X78Y342 INT_R_X67Y341 -> INT_R_X67Y341 ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 2 Aspect Ratio: 0.666667 Sparse Ratio: 1.5625 Direction: South ---------------- Congested clusters found at Level 1 Effective congestion level: 2 Aspect Ratio: 0.333333 Sparse Ratio: 0.75 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 1 Aspect Ratio: 0.75 Sparse Ratio: 1.75 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5 Phase 7 Route finalize | Checksum: 28b456797 Time (s): cpu = 00:29:40 ; elapsed = 00:08:48 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4006 ; free virtual = 23198 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 28b456797 Time (s): cpu = 00:29:41 ; elapsed = 00:08:48 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4003 ; free virtual = 23195 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_gt_common_block/gthe2_common_0_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y9/GTNORTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y23/GTREFCLK1 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gth_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y5/GTREFCLK1 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y22/GTREFCLK1 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y21/GTREFCLK1 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y20/GTREFCLK1 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y19/GTSOUTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gth_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y4/GTSOUTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y18/GTSOUTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y17/GTSOUTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y16/GTSOUTHREFCLK0 Phase 9 Depositing Routes | Checksum: 2822c1354 Time (s): cpu = 00:30:01 ; elapsed = 00:09:08 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4025 ; free virtual = 23217 Phase 10 Post Router Timing Phase 10.1 Update Timing Phase 10.1 Update Timing | Checksum: 1de2179a0 Time (s): cpu = 00:30:38 ; elapsed = 00:09:19 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4031 ; free virtual = 23223 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.186 | TNS=-11.250| WHS=0.010 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 10 Post Router Timing | Checksum: 1de2179a0 Time (s): cpu = 00:30:39 ; elapsed = 00:09:20 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4031 ; free virtual = 23223 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:30:39 ; elapsed = 00:09:20 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4359 ; free virtual = 23551 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 1554 Infos, 162 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:31:21 ; elapsed = 00:09:50 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4361 ; free virtual = 23554 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:49 ; elapsed = 00:00:21 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 3337 ; free virtual = 23416 INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:21 ; elapsed = 00:01:47 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4125 ; free virtual = 23516 INFO: [runtcl-4] Executing : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx Command: report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Coretcl 2-168] The results of DRC are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:01:47 ; elapsed = 00:00:34 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 3938 ; free virtual = 23331 INFO: [runtcl-4] Executing : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx Command: report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 8 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:06:31 ; elapsed = 00:01:38 . Memory (MB): peak = 8491.820 ; gain = 553.332 ; free physical = 1798 ; free virtual = 21200 INFO: [runtcl-4] Executing : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx Command: report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 1566 Infos, 163 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:03:41 ; elapsed = 00:01:16 . Memory (MB): peak = 8955.473 ; gain = 463.652 ; free physical = 1467 ; free virtual = 20879 INFO: [runtcl-4] Executing : report_route_status -file top_route_status.rpt -pb top_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:01:02 ; elapsed = 00:00:19 . Memory (MB): peak = 9457.984 ; gain = 502.512 ; free physical = 1269 ; free virtual = 20687 INFO: [runtcl-4] Executing : report_incremental_reuse -file top_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. INFO: [runtcl-4] Executing : report_clock_utilization -file top_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:01:09 ; elapsed = 00:01:09 . Memory (MB): peak = 9457.984 ; gain = 0.000 ; free physical = 1263 ; free virtual = 20681 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs Command: phys_opt_design -directive AggressiveExplore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 99.8% nets are fully routed) INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AggressiveExplore INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Netlist sorting complete. Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.49 . Memory (MB): peak = 9490.000 ; gain = 0.000 ; free physical = 1249 ; free virtual = 20670 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.183 | TNS=-10.888 | WHS=0.010 | THS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1b914bab1 Time (s): cpu = 00:03:26 ; elapsed = 00:01:02 . Memory (MB): peak = 9490.000 ; gain = 0.000 ; free physical = 940 ; free virtual = 20361 Phase 2 Critical Path Optimization INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.183 | TNS=-10.888 | WHS=0.010 | THS=0.000 | INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][97]. Optimizations did not improve timing on the net. INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.063 | TNS=-1.501 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Critial path length was reduced through logic transformation on cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1_comp. INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.045 | TNS=-1.059 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[0] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[0]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.045 | TNS=-1.059 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Critial path length was reduced through logic transformation on cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0_comp. INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.040 | TNS=-0.878 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Critial path length was reduced through logic transformation on cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1_comp_1. INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.039 | TNS=-0.296 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][34]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[42] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][34]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.039 | TNS=-0.257 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][35]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[43] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][35]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.039 | TNS=-0.217 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][36]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[44] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][36]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.039 | TNS=-0.178 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][37]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[45] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][37]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.039 | TNS=-0.138 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][38]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[46] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][38]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.039 | TNS=-0.099 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][39]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[47] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][39]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.010 | TNS=-0.059 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][40]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[48] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][40]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.010 | TNS=-0.049 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][41]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[49] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][41]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.010 | TNS=-0.039 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][42]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/_wTxMuxSelectDataEndFlag. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/S[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag0[15]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][42]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/_wTxMuxSelectDataEndFlag. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/S[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag0[15]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1. Optimizations did not improve timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.010 | TNS=-0.039 | WHS=0.006 | THS=0.000 | Phase 2 Critical Path Optimization | Checksum: 1b914bab1 Time (s): cpu = 00:20:33 ; elapsed = 00:09:46 . Memory (MB): peak = 9685.402 ; gain = 195.402 ; free physical = 906 ; free virtual = 20327 Phase 3 Hold Fix Optimization INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.010 | TNS=-0.039 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-45] Identified 11 candidate nets for hold slack optimization. INFO: [Physopt 32-234] Optimized 11 nets. Inserted 0 new ZHOLD_DELAYs. Calibrated 0 existing ZHOLD_DELAYs. Inserted 11 buffers. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.010 | TNS=-0.039 | WHS=0.006 | THS=0.000 | Phase 3 Hold Fix Optimization | Checksum: 1b914bab1 Time (s): cpu = 00:24:27 ; elapsed = 00:12:55 . Memory (MB): peak = 9685.402 ; gain = 195.402 ; free physical = 902 ; free virtual = 20324 Netlist sorting complete. Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.46 . Memory (MB): peak = 9685.402 ; gain = 0.000 ; free physical = 903 ; free virtual = 20324 INFO: [Physopt 32-669] Post Physical Optimization Timing Summary | WNS=-0.010 | TNS=-0.039 | WHS=0.006 | THS=0.000 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Critical Path | 0.173 | 10.849 | 0 | 0 | 13 | 0 | 1 | 00:08:41 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Summary of Hold Fix Optimizations ================================= -------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WHS Gain (ns) | THS Gain (ns) | Added LUTs | Added FFs | Optimized Nets | Dont Touch | Iterations | Elapsed | -------------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT1 and ZHOLD Insertion | 0.000 | 0.000 | 11 | 0 | 11 | 0 | 1 | 00:03:09 | | Total | 0.000 | 0.000 | 11 | 0 | 11 | 0 | 1 | 00:03:09 | -------------------------------------------------------------------------------------------------------------------------------------------------------------- Ending Physical Synthesis Task | Checksum: 1b914bab1 Time (s): cpu = 00:24:28 ; elapsed = 00:12:56 . Memory (MB): peak = 9685.402 ; gain = 195.402 ; free physical = 908 ; free virtual = 20330 INFO: [Common 17-83] Releasing license: Implementation 1651 Infos, 164 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:24:41 ; elapsed = 00:13:09 . Memory (MB): peak = 9685.402 ; gain = 227.418 ; free physical = 1644 ; free virtual = 21066 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:51 ; elapsed = 00:00:21 . Memory (MB): peak = 9685.402 ; gain = 0.000 ; free physical = 656 ; free virtual = 20963 INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_postroute_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:21 ; elapsed = 00:01:47 . Memory (MB): peak = 9685.402 ; gain = 0.000 ; free physical = 1403 ; free virtual = 21024 INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -warn_on_violation -file top_timing_summary_postroute_physopted.rpt -pb top_timing_summary_postroute_physopted.pb -rpx top_timing_summary_postroute_physopted.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:03:34 ; elapsed = 00:00:46 . Memory (MB): peak = 9685.402 ; gain = 0.000 ; free physical = 1510 ; free virtual = 21137 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_postroute_physopted.rpt -pb top_bus_skew_postroute_physopted.pb -rpx top_bus_skew_postroute_physopted.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ehndy8vbflb0gxuke3lnsjm_77/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ehndy8vbflb0gxuke3lnsjm_77/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/rc2oqgemebaubffc_998/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/rc2oqgemebaubffc_998/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xt6i6t0dtbr9k9ux4848l_2541/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xt6i6t0dtbr9k9ux4848l_2541/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/zmtz6gstdn71pkc38oscb260fx_746/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/zmtz6gstdn71pkc38oscb260fx_746/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xtsdogepbxcg3t8fqtbed8as0e1l_2610/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xtsdogepbxcg3t8fqtbed8as0e1l_2610/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. Command: write_bitstream -force top.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems. Evaluation cores found in this design: IP core 'axi_10g_ethernet_nonshared' (bd_7ad4) was generated with multiple features: IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license. IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license. IP core 'bd_7ad4_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license. IP core 'axi_10g_ethernet_shared' (bd_a1aa) was generated with multiple features: IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license. IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license. IP core 'bd_a1aa_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license. Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation. Running DRC as a precondition to command write_bitstream INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PLBUFGOPT-1] Non-Optimal connections to BUFG: A non-muxed BUFG control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1 is driven by another global buffer control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica. Remove non-muxed BUFG if it is not desired WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/ENBWREN (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[0] (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[1] (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[2] (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC RTSTAT-10] No routable loads: 350 net(s) have no routable loads. The problem bus(es) and/or net(s) are control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i... and (the first 15 of 70 listed). INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_4/editor_inst/PktFifo_inst/RAM/RAM_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/PktFifo_inst/RAM/RAM_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_10) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_8) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_10) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_8) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_10) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_8) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [Common 17-14] Message 'DRC REQP-181' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 52 Warnings, 422 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Bitstream compression saved 65812608 bits. Writing bitstream ./top.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Common 17-83] Releasing license: Implementation 1818 Infos, 217 Warnings, 2 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:08:09 ; elapsed = 00:04:06 . Memory (MB): peak = 9776.414 ; gain = 91.012 ; free physical = 1442 ; free virtual = 21096 INFO: [Common 17-206] Exiting Vivado at Mon Jul 29 20:16:10 2019... [Mon Jul 29 20:16:15 2019] impl_1 finished wait_on_run: Time (s): cpu = 00:45:57 ; elapsed = 02:07:22 . Memory (MB): peak = 2883.371 ; gain = 0.000 ; free physical = 8664 ; free virtual = 28326 # exit INFO: [Common 17-206] Exiting Vivado at Mon Jul 29 20:16:15 2019... make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw' make -C hw export_to_sdk make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw' rm -f ../hw/create_ip/id_rom16x32.coe cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh echo 16028002 >> rom_data.txt echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt grep: ../../../RELEASE_NOTES: No such file or directory echo 00000204 >> rom_data.txt echo 0000FFFF >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt echo FFFF0000 >> rom_data.txt cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py 16 mv -f id_rom16x32.coe ../hw/create_ip/ mv -f rom_data.txt ../hw/create_ip/ if test -d project; then\ echo "export simple_sume_switch project to SDK"; \ vivado -mode tcl -source tcl/export_hardware.tcl -tclargs simple_sume_switch;\ else \ echo "Project simple_sume_switch does not exist.";\ echo "Please run \"make project\" to create and build the project first";\ fi;\ export simple_sume_switch project to SDK ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source tcl/export_hardware.tcl # set design [lindex $argv 0] # puts "\nOpening $design XPR project\n" Opening simple_sume_switch XPR project # open_project project/$design.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'. WARNING: [IP_Flow 19-3664] IP 'bd_7ad4_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-20680-ESPRIMO-P956/coregen/bd_7ad4_xpcs_0_1/elaborate/configure_gt.tcl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'bd_a1aa_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-20680-ESPRIMO-P956/coregen/bd_a1aa_xpcs_0_2/elaborate/configure_gt.tcl'. Please regenerate to continue. open_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1372.844 ; gain = 189.508 ; free physical = 9387 ; free virtual = 29051 # puts "\nOpening $design Implementation design\n" Opening simple_sume_switch Implementation design # open_run impl_1 INFO: [Netlist 29-17] Analyzing 6081 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2018.2 INFO: [Device 21-403] Loading part xc7vx690tffg1761-3 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 4908.293 ; gain = 501.727 ; free physical = 6136 ; free virtual = 25801 Restored from archive | CPU: 20.930000 secs | Memory: 509.936699 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 4908.293 ; gain = 501.727 ; free physical = 6136 ; free virtual = 25801 Generating merged BMM file for the design top 'top'... INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/data/mb_bootloop_le.elf INFO: [Project 1-111] Unisim Transformation Summary: A total of 840 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 2 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 79 instances RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 24 instances RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 525 instances RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 151 instances RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 24 instances SRLC16E => SRL16E: 1 instances open_run: Time (s): cpu = 00:02:08 ; elapsed = 00:03:21 . Memory (MB): peak = 5636.648 ; gain = 4263.805 ; free physical = 6251 ; free virtual = 25917 # puts "\nCopying top.sysdef\n" Copying top.sysdef # file copy -force ./project/$design.runs/impl_1/top.sysdef ../sw/embedded/$design.hdf # exit INFO: [Common 17-206] Exiting Vivado at Mon Jul 29 20:19:49 2019... make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw' make -C sw/embedded/ project make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded' mkdir ./SDK_Workspace xsdk -batch -source ./tcl/simple_sume_switch_xsdk.tcl Starting xsdk. This could take few seconds... Eclipse: Cannot open display: done INFO: [Hsi 55-1698] elapsed time for repository loading 0 seconds /opt/Xilinx/SDK/2018.2/gnu/microblaze/lin BSP project 'bsp' created successfully. WARNING: [Hsi 61-9] Current Software design may not be compatible with "hello_world" app. Tool is ignoring the MSS file specified in the app directory Application project 'app' created successfully. Building '/bsp' Invoking Make Builder...bsp 20:19:56 **** Build of project bsp **** make -k all make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src' make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src' Compiling standalone microblaze_sleep.c:74:9: note: #pragma message: For the sleep routines, assembly instructions are used #pragma message ("For the sleep routines, assembly instructions are used") ^~~~~~~ mb-ar: creating ../../../lib/libxil.a make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' Compiling iic make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' Compiling uartlite make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' Compiling bram make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' Compiling cpu make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' Compiling intc make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' Finished building libraries make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp' 20:19:58 Build Finished (took 1s.918ms) Building '/app' 20:19:58 **** Build of configuration Debug for project app **** make all make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug' Building file: ../src/helloworld.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c" Finished building: ../src/helloworld.c Building file: ../src/platform.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c" Finished building: ../src/platform.c Building target: app.elf Invoking: MicroBlaze gcc linker mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf" ./src/helloworld.o ./src/platform.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group Finished building target: app.elf Invoking: MicroBlaze Print Size mb-size app.elf |tee "app.elf.size" text data bss dec hex filename 3112 316 3108 6536 1988 app.elf Finished building: app.elf.size make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug' 20:19:58 Build Finished (took 512ms) Invoking scanner config builder on project Building '/hw_platform' make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded' make -C sw/embedded/ compile make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded' Eclipse: GTK+ Version Check Eclipse: Cannot open display: Building All Projects... Building workspace Building '/bsp' Invoking Make Builder...bsp 20:20:01 **** Build of project bsp **** make -k all make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src' make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src' Compiling standalone microblaze_sleep.c:74:9: note: #pragma message: For the sleep routines, assembly instructions are used #pragma message ("For the sleep routines, assembly instructions are used") ^~~~~~~ make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' Compiling iic make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' Compiling uartlite make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' Compiling bram make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' Compiling cpu make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' Compiling intc make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' Finished building libraries make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp' 20:20:03 Build Finished (took 1s.872ms) Building '/app' 20:20:03 **** Build of configuration Debug for project app **** make all make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug' Building file: ../src/helloworld.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c" ../src/helloworld.c: In function 'runManualTest': ../src/helloworld.c:103:5: warning: implicit declaration of function 'pmReadInfo' [-Wimplicit-function-declaration] pmReadInfo(); ^~~~~~~~~~ ../src/helloworld.c: In function 'main': ../src/helloworld.c:125:11: warning: implicit declaration of function 'IicInit' [-Wimplicit-function-declaration] Status = IicInit(&IicInstance); ^~~~~~~ ../src/helloworld.c:134:11: warning: implicit declaration of function 'SetupInterruptSystem'; did you mean 'XIntc_InterruptHandler'? [-Wimplicit-function-declaration] Status = SetupInterruptSystem(&IicInstance); ^~~~~~~~~~~~~~~~~~~~ XIntc_InterruptHandler ../src/helloworld.c:143:11: warning: implicit declaration of function 'IicInitPost' [-Wimplicit-function-declaration] Status = IicInitPost(&IicInstance); ^~~~~~~~~~~ ../src/helloworld.c:149:2: warning: implicit declaration of function 'config_SI5324' [-Wimplicit-function-declaration] config_SI5324(); ^~~~~~~~~~~~~ Finished building: ../src/helloworld.c Building file: ../src/platform.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c" Finished building: ../src/platform.c Building target: app.elf Invoking: MicroBlaze gcc linker mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf" ./src/helloworld.o ./src/platform.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group ./src/helloworld.o: In function `runManualTest': /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/../src/helloworld.c:103: undefined reference to `pmReadInfo' ./src/helloworld.o: In function `main': makefile:36: recipe for target 'app.elf' failed /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/../src/helloworld.c:125: undefined reference to `IicInit' /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/../src/helloworld.c:143: undefined reference to `IicInitPost' make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug' /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/../src/helloworld.c:149: undefined reference to `config_SI5324' collect2: error: ld returned 1 exit status make[2]: *** [app.elf] Error 1 20:20:04 Build Finished (took 510ms) 20:20:04 **** Build of configuration Release for project app **** make all make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release' Building file: ../src/helloworld.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c" ../src/helloworld.c: In function 'runManualTest': ../src/helloworld.c:103:5: warning: implicit declaration of function 'pmReadInfo' [-Wimplicit-function-declaration] pmReadInfo(); ^~~~~~~~~~ ../src/helloworld.c: In function 'main': ../src/helloworld.c:125:11: warning: implicit declaration of function 'IicInit' [-Wimplicit-function-declaration] Status = IicInit(&IicInstance); ^~~~~~~ ../src/helloworld.c:134:11: warning: implicit declaration of function 'SetupInterruptSystem'; did you mean 'XIntc_InterruptHandler'? [-Wimplicit-function-declaration] Status = SetupInterruptSystem(&IicInstance); ^~~~~~~~~~~~~~~~~~~~ XIntc_InterruptHandler ../src/helloworld.c:143:11: warning: implicit declaration of function 'IicInitPost' [-Wimplicit-function-declaration] Status = IicInitPost(&IicInstance); ^~~~~~~~~~~ ../src/helloworld.c:149:2: warning: implicit declaration of function 'config_SI5324' [-Wimplicit-function-declaration] config_SI5324(); ^~~~~~~~~~~~~ Finished building: ../src/helloworld.c Building file: ../src/iic_config.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_config.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_config.d" -MT"src/iic_config.o" -o "src/iic_config.o" "../src/iic_config.c" ../src/iic_config.c: In function 'IicReadData3': ../src/iic_config.c:439:10: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types] addrPtr = &addr; ^ ../src/iic_config.c:397:5: warning: unused variable 'IicOptions' [-Wunused-variable] u8 IicOptions; ^~~~~~~~~~ Finished building: ../src/iic_config.c Building file: ../src/iic_pm.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_pm.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_pm.d" -MT"src/iic_pm.o" -o "src/iic_pm.o" "../src/iic_pm.c" Finished building: ../src/iic_pm.c Building file: ../src/iic_si5324.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_si5324.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_si5324.d" -MT"src/iic_si5324.o" -o "src/iic_si5324.o" "../src/iic_si5324.c" Finished building: ../src/iic_si5324.c Building file: ../src/platform.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c" Finished building: ../src/platform.c Building target: app.elf Invoking: MicroBlaze gcc linker mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf" ./src/helloworld.o ./src/iic_config.o ./src/iic_pm.o ./src/iic_si5324.o ./src/platform.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group Finished building target: app.elf Invoking: MicroBlaze Print Size mb-size app.elf |tee "app.elf.size" text data bss dec hex filename 18364 468 3376 22208 56c0 app.elf Finished building: app.elf.size make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release' 20:20:05 Build Finished (took 607ms) Invoking scanner config builder on project Building '/hw_platform' Eclipse: GTK+ Version Check Eclipse: Cannot open display: Building All Projects... Building workspace Building '/bsp' Invoking Make Builder...bsp 20:20:09 **** Build of project bsp **** make -k all make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src' make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src' Compiling standalone microblaze_sleep.c:74:9: note: #pragma message: For the sleep routines, assembly instructions are used #pragma message ("For the sleep routines, assembly instructions are used") ^~~~~~~ make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' Compiling iic make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' Compiling uartlite make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' Compiling bram make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' Compiling cpu make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src' Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' Compiling intc make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src' Finished building libraries make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp' 20:20:11 Build Finished (took 1s.870ms) Building '/app' 20:20:11 **** Clean-only build of configuration Debug for project app **** make clean make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug' rm -rf ./src/helloworld.o ./src/platform.o ./src/helloworld.d ./src/platform.d app.elf.size app.elf make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug' 20:20:11 Build Finished (took 406ms) 20:20:11 **** Build of configuration Debug for project app **** make all make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug' Building file: ../src/helloworld.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c" ../src/helloworld.c: In function 'runManualTest': ../src/helloworld.c:103:5: warning: implicit declaration of function 'pmReadInfo' [-Wimplicit-function-declaration] pmReadInfo(); ^~~~~~~~~~ ../src/helloworld.c: In function 'main': ../src/helloworld.c:125:11: warning: implicit declaration of function 'IicInit' [-Wimplicit-function-declaration] Status = IicInit(&IicInstance); ^~~~~~~ ../src/helloworld.c:134:11: warning: implicit declaration of function 'SetupInterruptSystem'; did you mean 'XIntc_InterruptHandler'? [-Wimplicit-function-declaration] Status = SetupInterruptSystem(&IicInstance); ^~~~~~~~~~~~~~~~~~~~ XIntc_InterruptHandler ../src/helloworld.c:143:11: warning: implicit declaration of function 'IicInitPost' [-Wimplicit-function-declaration] Status = IicInitPost(&IicInstance); ^~~~~~~~~~~ ../src/helloworld.c:149:2: warning: implicit declaration of function 'config_SI5324' [-Wimplicit-function-declaration] config_SI5324(); ^~~~~~~~~~~~~ Finished building: ../src/helloworld.c Building file: ../src/iic_config.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/iic_config.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_config.d" -MT"src/iic_config.o" -o "src/iic_config.o" "../src/iic_config.c" ../src/iic_config.c: In function 'IicReadData3': ../src/iic_config.c:439:10: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types] addrPtr = &addr; ^ ../src/iic_config.c:397:5: warning: unused variable 'IicOptions' [-Wunused-variable] u8 IicOptions; ^~~~~~~~~~ Finished building: ../src/iic_config.c Building file: ../src/iic_pm.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/iic_pm.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_pm.d" -MT"src/iic_pm.o" -o "src/iic_pm.o" "../src/iic_pm.c" Finished building: ../src/iic_pm.c Building file: ../src/iic_si5324.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/iic_si5324.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_si5324.d" -MT"src/iic_si5324.o" -o "src/iic_si5324.o" "../src/iic_si5324.c" Finished building: ../src/iic_si5324.c Building file: ../src/platform.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c" Finished building: ../src/platform.c Building target: app.elf Invoking: MicroBlaze gcc linker mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf" ./src/helloworld.o ./src/iic_config.o ./src/iic_pm.o ./src/iic_si5324.o ./src/platform.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group Finished building target: app.elf Invoking: MicroBlaze Print Size mb-size app.elf |tee "app.elf.size" text data bss dec hex filename 20340 468 3376 24184 5e78 app.elf Finished building: app.elf.size make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug' 20:20:12 Build Finished (took 611ms) 20:20:12 **** Clean-only build of configuration Release for project app **** make clean make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release' rm -rf ./src/helloworld.o ./src/iic_config.o ./src/iic_pm.o ./src/iic_si5324.o ./src/platform.o ./src/helloworld.d ./src/iic_config.d ./src/iic_pm.d ./src/iic_si5324.d ./src/platform.d app.elf.size app.elf make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release' 20:20:12 Build Finished (took 406ms) 20:20:12 **** Build of configuration Release for project app **** make all make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release' Building file: ../src/helloworld.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c" ../src/helloworld.c: In function 'runManualTest': ../src/helloworld.c:103:5: warning: implicit declaration of function 'pmReadInfo' [-Wimplicit-function-declaration] pmReadInfo(); ^~~~~~~~~~ ../src/helloworld.c: In function 'main': ../src/helloworld.c:125:11: warning: implicit declaration of function 'IicInit' [-Wimplicit-function-declaration] Status = IicInit(&IicInstance); ^~~~~~~ ../src/helloworld.c:134:11: warning: implicit declaration of function 'SetupInterruptSystem'; did you mean 'XIntc_InterruptHandler'? [-Wimplicit-function-declaration] Status = SetupInterruptSystem(&IicInstance); ^~~~~~~~~~~~~~~~~~~~ XIntc_InterruptHandler ../src/helloworld.c:143:11: warning: implicit declaration of function 'IicInitPost' [-Wimplicit-function-declaration] Status = IicInitPost(&IicInstance); ^~~~~~~~~~~ ../src/helloworld.c:149:2: warning: implicit declaration of function 'config_SI5324' [-Wimplicit-function-declaration] config_SI5324(); ^~~~~~~~~~~~~ Finished building: ../src/helloworld.c Building file: ../src/iic_config.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_config.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_config.d" -MT"src/iic_config.o" -o "src/iic_config.o" "../src/iic_config.c" ../src/iic_config.c: In function 'IicReadData3': ../src/iic_config.c:439:10: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types] addrPtr = &addr; ^ ../src/iic_config.c:397:5: warning: unused variable 'IicOptions' [-Wunused-variable] u8 IicOptions; ^~~~~~~~~~ Finished building: ../src/iic_config.c Building file: ../src/iic_pm.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_pm.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_pm.d" -MT"src/iic_pm.o" -o "src/iic_pm.o" "../src/iic_pm.c" Finished building: ../src/iic_pm.c Building file: ../src/iic_si5324.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_si5324.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_si5324.d" -MT"src/iic_si5324.o" -o "src/iic_si5324.o" "../src/iic_si5324.c" Finished building: ../src/iic_si5324.c Building file: ../src/platform.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c" Finished building: ../src/platform.c Building target: app.elf Invoking: MicroBlaze gcc linker mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf" ./src/helloworld.o ./src/iic_config.o ./src/iic_pm.o ./src/iic_si5324.o ./src/platform.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group Finished building target: app.elf Invoking: MicroBlaze Print Size mb-size app.elf |tee "app.elf.size" text data bss dec hex filename 18364 468 3376 22208 56c0 app.elf Finished building: app.elf.size make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release' 20:20:13 Build Finished (took 612ms) Invoking scanner config builder on project Building '/hw_platform' Eclipse: GTK+ Version Check make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded' make -C hw load_elf make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw' if test -d project; then\ echo "export simple_sume_switch project to SDK"; \ vivado -mode tcl -source tcl/load_elf.tcl -tclargs simple_sume_switch;\ else \ echo "Project simple_sume_switch does not exist.";\ echo "Please run \"make project\" to create and build the project first";\ fi;\ export simple_sume_switch project to SDK ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source tcl/load_elf.tcl # set design [lindex $argv 0] # set ws "SDK_Workspace" # puts "\nOpening $design XPR project\n" Opening simple_sume_switch XPR project # open_project project/$design.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'. WARNING: [IP_Flow 19-3664] IP 'bd_7ad4_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-20680-ESPRIMO-P956/coregen/bd_7ad4_xpcs_0_1/elaborate/configure_gt.tcl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'bd_a1aa_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-20680-ESPRIMO-P956/coregen/bd_a1aa_xpcs_0_2/elaborate/configure_gt.tcl'. Please regenerate to continue. open_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1372.844 ; gain = 189.508 ; free physical = 9300 ; free virtual = 29043 # set bd_file [get_files -regexp -nocase {.*sub*.bd}] # set elf_file ../sw/embedded/$ws/$design/app/Debug/app.elf # puts "\nOpening $design BD project\n" Opening simple_sume_switch BD project # open_bd_design $bd_file Adding cell -- xilinx.com:ip:axi_iic:2.0 - axi_iic_0 Adding cell -- xilinx.com:ip:axi_uartlite:2.0 - axi_uartlite_0 Adding cell -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_1 Adding cell -- xilinx.com:ip:mdm:3.2 - mdm_1 Adding cell -- xilinx.com:ip:microblaze:10.0 - microblaze_0 Adding cell -- xilinx.com:ip:axi_intc:4.1 - microblaze_0_axi_intc Adding cell -- xilinx.com:ip:xlconcat:2.1 - microblaze_0_xlconcat Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_clk_wiz_1_100M Adding cell -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - dlmb_bram_if_cntlr Adding cell -- xilinx.com:ip:lmb_v10:3.0 - dlmb_v10 Adding cell -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - ilmb_bram_if_cntlr Adding cell -- xilinx.com:ip:lmb_v10:3.0 - ilmb_v10 Adding cell -- xilinx.com:ip:blk_mem_gen:8.4 - lmb_bram Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar Adding cell -- xilinx.com:ip:util_vector_logic:2.0 - pcie_reset_inv Adding cell -- xilinx.com:ip:axis_dwidth_converter:1.1 - axis_dwidth_dma_tx Adding cell -- xilinx.com:ip:axis_dwidth_converter:1.1 - axis_dwidth_dma_rx Adding cell -- xilinx.com:ip:axis_data_fifo:1.1 - axis_fifo_10g_rx Adding cell -- xilinx.com:ip:axis_data_fifo:1.1 - axis_fifo_10g_tx Adding cell -- NetFPGA:NetFPGA:nf_riffa_dma:1.0 - nf_riffa_dma_1 Adding cell -- xilinx.com:ip:axi_clock_converter:2.1 - axi_clock_converter_0 Adding cell -- xilinx.com:ip:pcie3_7x:4.3 - pcie3_7x_1 Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m08_data_fifo Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m07_data_fifo Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m06_data_fifo Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m05_data_fifo Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m04_data_fifo Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m03_data_fifo Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m02_data_fifo Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m01_data_fifo Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m00_data_fifo Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - s00_data_fifo Adding cell -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc Successfully read diagram from BD file # if {[llength [get_files app.elf]]} { # puts "ELF File [get_files app.elf] is already associated" # exit # } else { # add_files -norecurse -force ${elf_file} # set_property SCOPED_TO_REF [current_bd_design] [get_files -all -of_objects [get_fileset sources_1] ${elf_file}] # set_property SCOPED_TO_CELLS nf_mbsys/mbsys/microblaze_0 [get_files -all -of_objects [get_fileset sources_1] ${elf_file}] # } WARNING: [Vivado 12-818] No files matched 'app.elf' # reset_run impl_1 -prev_step # launch_runs impl_1 -to_step write_bitstream INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'identifier_ip'... [Mon Jul 29 20:20:31 2019] Launched impl_1... Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/runme.log # wait_on_run impl_1 [Mon Jul 29 20:20:31 2019] Waiting for impl_1 to finish... *** Running vivado with args -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source top.tcl -notrace Command: link_design -top top -part xc7vx690tffg1761-3 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0.dcp' for cell 'control_sub_i/dma_sub/axi_clock_converter_0' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0.dcp' for cell 'control_sub_i/dma_sub/axis_dwidth_dma_rx' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0.dcp' for cell 'control_sub_i/dma_sub/axis_dwidth_dma_tx' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.dcp' for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.dcp' for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0.dcp' for cell 'control_sub_i/dma_sub/nf_riffa_dma_1' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0.dcp' for cell 'control_sub_i/dma_sub/pcie3_7x_1' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0.dcp' for cell 'control_sub_i/dma_sub/pcie_reset_inv' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_0/control_sub_xbar_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/xbar' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0.dcp' for cell 'control_sub_i/nf_mbsys/axi_iic_0' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.dcp' for cell 'control_sub_i/nf_mbsys/axi_uartlite_0' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.dcp' for cell 'control_sub_i/nf_mbsys/clk_wiz_1' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_xlconcat' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_1/control_sub_xbar_1.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_periph/xbar' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10' INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_lmb_bram_0/control_sub_lmb_bram_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram' INFO: [Netlist 29-17] Analyzing 7691 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2018.2 INFO: [Device 21-403] Loading part xc7vx690tffg1761-3 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_board.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_board.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1/U0' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc:50] get_clocks: Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 4365.883 ; gain = 1348.156 ; free physical = 6475 ; free virtual = 25231 Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_board.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_board.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1/inst' INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc:124] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc:57] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc] Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc] Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc] Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc] WARNING: [Constraints 18-619] A clock with name 'xphy_refclk_p' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:92] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:114] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:115] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:116] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:117] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:118] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:119] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:120] WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:121] INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:149] get_clocks: Time (s): cpu = 00:00:18 ; elapsed = 00:00:08 . Memory (MB): peak = 5829.922 ; gain = 175.000 ; free physical = 5231 ; free virtual = 23987 Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc] Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_late.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_late.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_clocks.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_clocks.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst' Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Common 17-14] Message 'Vivado 12-3272' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Common 17-14] Message 'XPM_CDC_GRAY: TCL 1000' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/rc2oqgemebaubffc_998/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/rc2oqgemebaubffc_998/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/zmtz6gstdn71pkc38oscb260fx_746/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/zmtz6gstdn71pkc38oscb260fx_746/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oggsepfdbfvc08g925kumcu8ai081hf_2487/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/h2gi6oqvy2ath2fk_362/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a1j85vyq4aadbgoq5b7orqtbwpa_1948/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xt6i6t0dtbr9k9ux4848l_2541/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xt6i6t0dtbr9k9ux4848l_2541/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ehndy8vbflb0gxuke3lnsjm_77/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ehndy8vbflb0gxuke3lnsjm_77/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xtsdogepbxcg3t8fqtbed8as0e1l_2610/xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xtsdogepbxcg3t8fqtbed8as0e1l_2610/xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Generating merged BMM file for the design top 'top'... INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/data/mb_bootloop_le.elf INFO: [Project 1-111] Unisim Transformation Summary: A total of 894 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 2 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 80 instances RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 24 instances RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 527 instances RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 195 instances RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 32 instances 148 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:03:47 ; elapsed = 00:04:10 . Memory (MB): peak = 6294.148 ; gain = 4962.141 ; free physical = 7011 ; free virtual = 25769 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 7010 ; free virtual = 25768 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 13a92017d Time (s): cpu = 00:00:39 ; elapsed = 00:00:14 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6432 ; free virtual = 25190 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 34 inverter(s) to 113 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 6f9e749d Time (s): cpu = 00:01:17 ; elapsed = 00:00:59 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6986 ; free virtual = 25744 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 17 inverter(s) to 49 load pin(s). Phase 2 Constant propagation | Checksum: d75d7ef6 Time (s): cpu = 00:01:45 ; elapsed = 00:01:27 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6986 ; free virtual = 25744 INFO: [Opt 31-389] Phase Constant propagation created 1514 cells and removed 21453 cells Phase 3 Sweep Phase 3 Sweep | Checksum: 15a267b85 Time (s): cpu = 00:02:40 ; elapsed = 00:02:22 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6990 ; free virtual = 25748 INFO: [Opt 31-389] Phase Sweep created 9 cells and removed 26640 cells Phase 4 BUFG optimization Phase 4 BUFG optimization | Checksum: 13d1ba485 Time (s): cpu = 00:02:48 ; elapsed = 00:02:30 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6989 ; free virtual = 25748 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 2 cells. Phase 5 Shift Register Optimization Phase 5 Shift Register Optimization | Checksum: 1aded50b2 Time (s): cpu = 00:03:05 ; elapsed = 00:02:47 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6992 ; free virtual = 25751 INFO: [Opt 31-389] Phase Shift Register Optimization created 1 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 11d6668c8 Time (s): cpu = 00:03:10 ; elapsed = 00:02:52 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6991 ; free virtual = 25749 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 20 cells Starting Connectivity Check Task Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.93 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6991 ; free virtual = 25749 Ending Logic Optimization Task | Checksum: 1a05f3302 Time (s): cpu = 00:03:13 ; elapsed = 00:02:55 . Memory (MB): peak = 6294.148 ; gain = 0.000 ; free physical = 6992 ; free virtual = 25751 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.163 | TNS=0.000 | Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 1 BRAM(s) out of a total of 803 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 22 WE to EN ports Number of BRAM Ports augmented: 434 newly gated: 384 Total Ports: 1606 Ending PowerOpt Patch Enables Task | Checksum: 1e5cbfe33 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6369 ; free virtual = 25131 Ending Power Optimization Task | Checksum: 1e5cbfe33 Time (s): cpu = 00:05:33 ; elapsed = 00:02:02 . Memory (MB): peak = 7938.488 ; gain = 1644.340 ; free physical = 6853 ; free virtual = 25615 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 1194f7277 Time (s): cpu = 00:01:04 ; elapsed = 00:00:30 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6880 ; free virtual = 25642 Ending Final Cleanup Task | Checksum: 1194f7277 Time (s): cpu = 00:01:05 ; elapsed = 00:00:31 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6880 ; free virtual = 25642 INFO: [Common 17-83] Releasing license: Implementation 171 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:10:38 ; elapsed = 00:05:49 . Memory (MB): peak = 7938.488 ; gain = 1644.340 ; free physical = 6880 ; free virtual = 25642 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.07 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6859 ; free virtual = 25628 INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:48 ; elapsed = 00:01:36 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6778 ; free virtual = 25626 INFO: [runtcl-4] Executing : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Coretcl 2-168] The results of DRC are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:43 ; elapsed = 00:00:25 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6717 ; free virtual = 25567 Command: place_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'Explore' directive. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.49 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6716 ; free virtual = 25566 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a19b0e16 Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.58 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6715 ; free virtual = 25565 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.45 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6714 ; free virtual = 25564 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [Place 30-139] Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i (GTHE2_CHANNEL.TXOUTCLK) is locked to GTHE2_CHANNEL_X1Y23 control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 936073ee Time (s): cpu = 00:02:28 ; elapsed = 00:01:20 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 6100 ; free virtual = 24953 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9feca4de Time (s): cpu = 00:04:48 ; elapsed = 00:02:30 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 5260 ; free virtual = 24114 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9feca4de Time (s): cpu = 00:04:49 ; elapsed = 00:02:31 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 5260 ; free virtual = 24114 Phase 1 Placer Initialization | Checksum: 9feca4de Time (s): cpu = 00:04:50 ; elapsed = 00:02:32 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 5260 ; free virtual = 24113 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: edf70a0e Time (s): cpu = 00:06:00 ; elapsed = 00:02:58 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4968 ; free virtual = 23822 Phase 2.2 Physical Synthesis In Placer WARNING: [Physopt 32-894] Found a constraint with the -through option on pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-76] Pass 1. Identified 30 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_reset_i/cpllreset. Replicated 15 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/valid_6. Replicated 11 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_3_reset. Replicated 13 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_3/E[0]. Replicated 11 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_4/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 12 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_18/E[0]. Replicated 13 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_19/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 11 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_15/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_16/E[0]. Replicated 12 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_7/E[0]. Replicated 12 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_3/valid_6. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_1/valid_6. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/tuple_in_TUPLE7_VALID. Replicated 12 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_22/E[0]. Replicated 12 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_6/MUX_TUPLE_p_reg[0]_0[0]. Replicated 13 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_0/TX_TUPLE_VALID. Replicated 13 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_0/valid_2. Replicated 11 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/valid_6. Replicated 13 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_23/E[0]. Replicated 11 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_25/valid_1. Replicated 11 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_4/valid_6. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/valid_6. Replicated 10 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/SS[0]. Replicated 14 times. WARNING: [Physopt 32-894] Found a constraint with the -through option on pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_3/tupleForward_inst/PktEop_d_1. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_3/valid_6. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_5/valid_6_reg_n_0_[0]. Replicated 9 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_6/valid_6. Replicated 10 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_7/valid_6. Replicated 6 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_1/valid_6. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_8/valid_6. Replicated 5 times. INFO: [Physopt 32-232] Optimized 30 nets. Created 325 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 30 nets or cells. Created 325 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4855 ; free virtual = 23712 INFO: [Physopt 32-76] Pass 1. Identified 1 candidate net for fanout optimization. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/rd_cnt_reg[6]. Replicated 10 times. INFO: [Physopt 32-232] Optimized 1 net. Created 10 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 10 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.67 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4858 ; free virtual = 23714 INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7_i_1_n_0 could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ueoy8q1oq92abqdr6cavsnehcsseh_7/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7_i_1 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/wea[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__0 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/gen_wr_b.gen_word_narrow.mem_reg_0_1[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__2 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/gen_wr_b.gen_word_narrow.mem_reg_0_2[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__3 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_1_1[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_Hash_Lookup_inst/i_/xpm_memory_tdpram_inst_i_3 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/RamRwAddr[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_3 could not be replicated INFO: [Physopt 32-117] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/WEA0 could not be optimized because driver control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/rRAM_reg_0_i_1 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_1_1[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Lookup_inst/realmain_dummy_table_for_netpfga_0_t_Hash_Lookup_inst/i_/xpm_memory_tdpram_inst_i_5__0 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/RamRwAddr[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_dummy_table_for_netpfga_0/realmain_dummy_table_for_netpfga_0_t_Wrap_inst/realmain_dummy_table_for_netpfga_0_t_IntTop_inst/realmain_dummy_table_for_netpfga_0_t_Update_inst/realmain_dummy_table_for_netpfga_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_2 could not be replicated INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1_n_0 could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/a6l5ilsonpwsue0o_2404/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1 could not be replicated INFO: [Physopt 32-46] Identified 3 candidate nets for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4871 ; free virtual = 23727 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------- | Very High Fanout | 325 | 0 | 30 | 0 | 1 | 00:00:39 | | Fanout | 10 | 0 | 1 | 0 | 1 | 00:00:01 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 335 | 0 | 31 | 0 | 3 | 00:00:40 | ----------------------------------------------------------------------------------------------------------------------------- Phase 2.2 Physical Synthesis In Placer | Checksum: 1fff03ad0 Time (s): cpu = 00:18:08 ; elapsed = 00:08:23 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4864 ; free virtual = 23721 Phase 2 Global Placement | Checksum: 181c1f290 Time (s): cpu = 00:18:39 ; elapsed = 00:08:37 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 5079 ; free virtual = 23935 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 181c1f290 Time (s): cpu = 00:18:43 ; elapsed = 00:08:38 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4944 ; free virtual = 23801 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1721c486f Time (s): cpu = 00:22:15 ; elapsed = 00:09:40 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4579 ; free virtual = 23435 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1432aceee Time (s): cpu = 00:22:21 ; elapsed = 00:09:44 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4578 ; free virtual = 23435 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 105513320 Time (s): cpu = 00:22:22 ; elapsed = 00:09:45 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4578 ; free virtual = 23434 Phase 3.5 Timing Path Optimizer Phase 3.5 Timing Path Optimizer | Checksum: 105513320 Time (s): cpu = 00:22:23 ; elapsed = 00:09:46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4578 ; free virtual = 23434 Phase 3.6 Fast Optimization Phase 3.6 Fast Optimization | Checksum: 16fb6183b Time (s): cpu = 00:22:30 ; elapsed = 00:09:52 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4578 ; free virtual = 23434 Phase 3.7 Small Shape Detail Placement Phase 3.7 Small Shape Detail Placement | Checksum: 4af46697 Time (s): cpu = 00:25:20 ; elapsed = 00:12:26 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4172 ; free virtual = 23029 Phase 3.8 Re-assign LUT pins Phase 3.8 Re-assign LUT pins | Checksum: a7bddef5 Time (s): cpu = 00:25:32 ; elapsed = 00:12:37 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4189 ; free virtual = 23046 Phase 3.9 Pipeline Register Optimization Phase 3.9 Pipeline Register Optimization | Checksum: f7c3441a Time (s): cpu = 00:25:35 ; elapsed = 00:12:41 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4194 ; free virtual = 23051 Phase 3 Detail Placement | Checksum: f7c3441a Time (s): cpu = 00:25:38 ; elapsed = 00:12:44 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4197 ; free virtual = 23054 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1f9ab725f Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-33] Processed net nf_datapath_0/input_arbiter_v1_0/inst/in_arb_queues[3].in_arb_fifo/fifo/SR[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_1_reset, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[2].output_fifo/fifo/SR[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_3/tupleForward_inst/Enable_d_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_22/valid_2, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_1/E[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20/E[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_21/MUX_TUPLE_p_reg[1402]_0[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_17/MUX_TUPLE_p_reg[1402]_0[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_9/E[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_14/E[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_13/valid_2, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_12/MUX_TUPLE_p_reg[1402]_0[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_11/E[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_10/MUX_TUPLE_p_reg[1402]_0[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_8/MUX_TUPLE_p_reg[1402]_0[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/tuple_out_TUPLE0_VALID, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_5/E[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl/TopPipe_lvl_t_inst/stage_0/valid_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/tuple_out_TUPLE6_VALID, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2_reset, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2/tupleForward_inst/Enable_d_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_3/tupleForward_inst/OutTupDat[3947]_i_1__1_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_4/valid_6, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2/valid_6, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2/tupleForward_inst/OutTupDat[3947]_i_1__0_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_1/tupleForward_inst/PktEop_d_1_i_1__0_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_1/tupleForward_inst/Enable_d_2, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_1/tupleForward_inst/OutTupDat[3947]_i_1_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-31] BUFG insertion identified 33 candidate nets, 0 success, 33 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. Phase 4.1.1.1 BUFG Insertion | Checksum: 1f9ab725f Time (s): cpu = 00:28:20 ; elapsed = 00:13:35 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4576 ; free virtual = 23433 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.674. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 176ec2ee4 Time (s): cpu = 00:35:05 ; elapsed = 00:18:43 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4516 ; free virtual = 23373 Phase 4.1 Post Commit Optimization | Checksum: 176ec2ee4 Time (s): cpu = 00:35:09 ; elapsed = 00:18:47 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4515 ; free virtual = 23373 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 176ec2ee4 Time (s): cpu = 00:35:14 ; elapsed = 00:18:50 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4531 ; free virtual = 23388 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 176ec2ee4 Time (s): cpu = 00:35:17 ; elapsed = 00:18:54 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4534 ; free virtual = 23392 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 187a25870 Time (s): cpu = 00:35:20 ; elapsed = 00:18:57 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4536 ; free virtual = 23393 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 187a25870 Time (s): cpu = 00:35:23 ; elapsed = 00:18:59 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4536 ; free virtual = 23393 Ending Placer Task | Checksum: 156291874 Time (s): cpu = 00:35:23 ; elapsed = 00:19:00 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 5082 ; free virtual = 23939 INFO: [Common 17-83] Releasing license: Implementation 275 Infos, 160 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:35:53 ; elapsed = 00:19:28 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 5082 ; free virtual = 23939 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:45 ; elapsed = 00:00:18 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4249 ; free virtual = 23828 INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:16 ; elapsed = 00:01:43 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4913 ; free virtual = 23934 INFO: [runtcl-4] Executing : report_io -file top_io_placed.rpt report_io: Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.42 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4873 ; free virtual = 23894 INFO: [runtcl-4] Executing : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb report_utilization: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4921 ; free virtual = 23942 report_utilization: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4921 ; free virtual = 23942 INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4920 ; free virtual = 23944 Command: phys_opt_design -directive ExploreWithHoldFix Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: ExploreWithHoldFix Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.48 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4781 ; free virtual = 23805 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.674 | TNS=-358.591 | Phase 1 Physical Synthesis Initialization | Checksum: e30ca06c Time (s): cpu = 00:03:05 ; elapsed = 00:00:58 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4532 ; free virtual = 23556 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.674 | TNS=-358.591 | Phase 2 Fanout Optimization INFO: [Physopt 32-76] Pass 1. Identified 13 candidate nets for fanout optimization. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady. Replicated 2 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][0]_0[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/will_update_dout. Replicated 1 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_1[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/will_update_middle. Replicated 2 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_0[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_3[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_2[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-601] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/WEBWE[0]. Net driver control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/rRAM_reg_0_i_1__2 was replaced. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_alignment_inst/gen_data_input_regs[3].data_register_/pipeline_inst/gen_stages[1].rData_reg[1][0][0]. Replicated 1 times. INFO: [Physopt 32-232] Optimized 5 nets. Created 6 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 5 nets or cells. Created 6 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.589 | TNS=-260.852 | Netlist sorting complete. Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.50 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4543 ; free virtual = 23568 Phase 2 Fanout Optimization | Checksum: 15e721c17 Time (s): cpu = 00:03:40 ; elapsed = 00:01:14 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4543 ; free virtual = 23567 Phase 3 Placement Based Optimization INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization. INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/sel. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/rCtrValue[0]_i_2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rValid[1]_i_2 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[0] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[1]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[1] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[2]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[2] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[3]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[3] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_1[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData[1][32]_i_1__1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_pipeline_inst_/pipeline_inst/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_6 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter[3]_i_4 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[2] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[3] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/clear. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/rCtrValue[0]_i_1 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[7]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[7] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[5]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[5] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[6]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[6] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_0[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData[1][32]_i_1__0 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg_0[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg_i_2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[10] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[8] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[9] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[12] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rRdPtrPlus1[2]_i_1__15 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][52]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[60] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][53]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[61] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][54]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[62] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][55]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[63] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][56]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[64] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][57]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[65] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][0]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter_reg[0]_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter[3]_i_9 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter[3]_i_8 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[127]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][153] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][99] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][64]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[72] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][65]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[73] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][66]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[74] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][67]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[75] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][68]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[76] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][69]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[77] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[107]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][115] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][20]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][28] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[33]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][41] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][82] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg_0[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg_i_2__0 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[64]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][72] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[65]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][73] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[52]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][60] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[53]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][61] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][3]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[11] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_2[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData[1][32]_i_1__2 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg_0[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg_i_2__1 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/rRdPtr_reg_n_0_[9]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/rRdPtr_reg[9] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][35] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][57]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][65] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][59]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][67] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[129]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][155] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][13] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][46]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[54] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][47]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[55] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][48]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][51]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[59] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[130]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][156] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[80]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][88] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][23]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][31] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_3[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData[1][32]_i_1__3 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_i_2__2 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/rRdPtrPlus1_reg__0[7]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/rRdPtrPlus1_reg[7] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/rRdPtrPlus1_reg__0[8]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/rRdPtrPlus1_reg[8] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][36]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[44] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/will_update_dout. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/dout[128]_i_1 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/will_update_middle_repN_1. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout[128]_i_1_replica_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/WR_FULL. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rFull_reg INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/fifo_rden__0. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/dout[128]_i_3 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/chnl_tx_data_ren[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/CHNL_TX_DATA_REN INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[125]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[125] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[19] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[64]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[64] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[66] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][72]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[80] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][73]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[81] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][75]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[83] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][18] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][19] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][20] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[14]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][22] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[15]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][23] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[89]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][97] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][86]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[94] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[63]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][71] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[127]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[21]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[22]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[22] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[24]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[63]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[63] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[65]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[65] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[92]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[99] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][3]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][11] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][115]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][129] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][117]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][131] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][124]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][150] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][13]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][94]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][95]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][115]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[129] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[131] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[11]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[11] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[20]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[20] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[29]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[29] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[34]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[34] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[45]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[45] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[60]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[60] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[69]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[69] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[70]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[70] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[32]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[32] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[3] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[62]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[62] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[75]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg_n_0_[81]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/middle_dout_reg[81] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][4]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[12] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[1] INFO: [Physopt 32-661] Optimized 53 nets. Re-placed 53 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 53 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 53 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-198.963 | Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4438 ; free virtual = 23463 Phase 3 Placement Based Optimization | Checksum: 1a1c2cd81 Time (s): cpu = 00:05:06 ; elapsed = 00:01:32 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4437 ; free virtual = 23462 Phase 4 MultiInst Placement Optimization INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica/O INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter_reg[0]_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter[3]_i_9/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter[3]_i_8/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter[3]_i_4/O INFO: [Physopt 32-661] Optimized 1 net. Re-placed 4 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 0 new cell, deleted 0 existing cell and moved 4 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-201.792 | Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4437 ; free virtual = 23462 Phase 4 MultiInst Placement Optimization | Checksum: 1a6fa4497 Time (s): cpu = 00:05:46 ; elapsed = 00:01:45 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4437 ; free virtual = 23462 Phase 5 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-77] Pass 1. Identified 1 candidate net for rewire optimization. INFO: [Physopt 32-134] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Rewiring did not optimize the net. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4430 ; free virtual = 23455 Netlist sorting complete. Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.47 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4430 ; free virtual = 23455 Phase 5 Rewire | Checksum: 120508df8 Time (s): cpu = 00:05:51 ; elapsed = 00:01:48 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4429 ; free virtual = 23454 Phase 6 Critical Cell Optimization INFO: [Physopt 32-46] Identified 12 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]. Replicated 1 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/clear was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/monitor/_rState. Replicated 1 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/monitor/wBufWen. Replicated 2 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg_0[0]. Replicated 1 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_0[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/intr/Q[5]. Replicated 1 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/intr/Q[0]. Replicated 1 times. INFO: [Physopt 32-601] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/sel. Net driver control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/rCtrValue[0]_i_2 was replaced. INFO: [Physopt 32-232] Optimized 7 nets. Created 7 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 7 nets or cells. Created 7 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-194.096 | Netlist sorting complete. Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.73 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4430 ; free virtual = 23455 Phase 6 Critical Cell Optimization | Checksum: 11ab67e90 Time (s): cpu = 00:06:15 ; elapsed = 00:01:58 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4430 ; free virtual = 23455 Phase 7 Fanout Optimization INFO: [Physopt 32-76] Pass 1. Identified 9 candidate nets for fanout optimization. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_3[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_0[0]. Replicated 2 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/E[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1_n_0. Replicated 2 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_alignment_inst/gen_data_input_regs[3].data_register_/pipeline_inst/gen_stages[1].rData_reg[1][0][0]_repN was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/will_update_middle_repN_1. Replicated 1 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/axis_riffa_fifo/will_update_dout. Replicated 1 times. INFO: [Physopt 32-232] Optimized 4 nets. Created 6 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 4 nets or cells. Created 6 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-192.855 | Netlist sorting complete. Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.51 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4430 ; free virtual = 23455 Phase 7 Fanout Optimization | Checksum: 106376d48 Time (s): cpu = 00:06:30 ; elapsed = 00:02:06 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4429 ; free virtual = 23454 Phase 8 Placement Based Optimization INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][0]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[127]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][153] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][99] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[107]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][115] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][20]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][28] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[33]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][41] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[64]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][72] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[65]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][73] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[52]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][60] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[53]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][61] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter_reg[0]_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter[3]_i_9 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter[3]_i_8 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter[3]_i_4 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[2] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[3] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][35] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][57]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][65] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][59]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][67] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[129]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][155] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rRdPtrPlus1[2]_i_1__15 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][51]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[59] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[130]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][156] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[80]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][88] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][23]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][31] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][48]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][69]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[77] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][36]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[44] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][72]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[80] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][73]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[81] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][75]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[83] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][18] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][19] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][20] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[14]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][22] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[15]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][23] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[89]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][97] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][86]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[94] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[63]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][71] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][115]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[129] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][4]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[12] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[2] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[25]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][33] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][35] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[48]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[88]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][96] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][113] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][118]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][144] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][123]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][149] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][100]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][108] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][31]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][39] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][88]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][96] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/_rEmpty. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/rEmpty_i_1__18 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/rEmpty. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/rEmpty_reg INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/clear. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/rCtrValue[0]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rValid[1]_i_2 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[0] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[1]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[1] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[2]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[2] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[3]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[3] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[2]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[14] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[12]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[12] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[13]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[13] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][3]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][11] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][115]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][129] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][117]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][131] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][124]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][150] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][130]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[156] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[157] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[5] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[6] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[7] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[10] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[8] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[9] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][80]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[88] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][81]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[89] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][113] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[115]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][129] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[118]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][144] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[119]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][145] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[120]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][146] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[121]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][147] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[123]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][149] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[125]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][151] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[36]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][44] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[51]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][59] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[62]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][70] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[25] INFO: [Physopt 32-661] Optimized 13 nets. Re-placed 13 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 13 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 13 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-191.578 | Netlist sorting complete. Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4429 ; free virtual = 23454 Phase 8 Placement Based Optimization | Checksum: 1a3cf0378 Time (s): cpu = 00:07:54 ; elapsed = 00:02:23 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 9 MultiInst Placement Optimization INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter_reg[0]_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter[3]_i_9/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter[3]_i_8/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter[3]_i_4/O INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 9 MultiInst Placement Optimization | Checksum: 1a0aac06d Time (s): cpu = 00:08:54 ; elapsed = 00:02:40 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4427 ; free virtual = 23453 Phase 10 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-241] No nets found for rewiring () optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.45 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4429 ; free virtual = 23455 Phase 10 Rewire | Checksum: 1a0aac06d Time (s): cpu = 00:08:56 ; elapsed = 00:02:42 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4429 ; free virtual = 23454 Phase 11 Critical Cell Optimization INFO: [Physopt 32-46] Identified 10 candidate nets for critical-cell optimization. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/clear. Replicated 1 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-601] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/monitor/_rState_repN. Net driver control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/monitor/rState[4]_i_1__4_replica was replaced. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/monitor/rState[4]_i_3__0_n_0. Replicated 1 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/monitor/_rState. Replicated 1 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-601] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]_repN. Net driver control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_i_2__2_replica was replaced. INFO: [Physopt 32-232] Optimized 5 nets. Created 3 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 5 nets or cells. Created 3 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-195.879 | Netlist sorting complete. Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.52 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4429 ; free virtual = 23454 Phase 11 Critical Cell Optimization | Checksum: 1d84a5101 Time (s): cpu = 00:09:15 ; elapsed = 00:02:50 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 12 Slr Crossing Optimization Phase 12 Slr Crossing Optimization | Checksum: 1d84a5101 Time (s): cpu = 00:09:16 ; elapsed = 00:02:50 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 13 Fanout Optimization INFO: [Physopt 32-76] Pass 1. Identified 3 candidate nets for fanout optimization. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/gen_stages[1].rData_reg[1][1]_3[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1_n_0_repN_1. Replicated 2 times. INFO: [Physopt 32-232] Optimized 1 net. Created 2 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 2 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-190.970 | Netlist sorting complete. Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.47 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 13 Fanout Optimization | Checksum: 14b1a292e Time (s): cpu = 00:09:25 ; elapsed = 00:02:56 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 14 Placement Based Optimization INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][0]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[127]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][153] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][99] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[107]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][115] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][108]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][109]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][131]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][20]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][28] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[33]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][41] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[64]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][72] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[65]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][73] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[52]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][60] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[53]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][61] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter_reg[0]_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter[3]_i_9 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter[3]_i_8 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter[3]_i_4 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[2] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[3] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][35] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][57]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][65] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][59]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][67] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[129]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][155] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rRdPtrPlus1[2]_i_1__15 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][51]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[59] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[130]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][156] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[80]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][88] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][23]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][31] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][48]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][69]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[77] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][36]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[44] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][72]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[80] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][73]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[81] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][75]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[83] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][18] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][19] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][20] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[14]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][22] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[15]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][23] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[89]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][97] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][86]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[94] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[63]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][71] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][115]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[129] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][4]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[12] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[2] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[25]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][33] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][35] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[48]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[88]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][96] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][113] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][118]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][144] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][123]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][149] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][100]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][108] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][31]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][39] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][88]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][96] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/_rEmpty. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/rEmpty_i_1__18 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/rEmpty. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/rEmpty_reg INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][130]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[156] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][80]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[88] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][81]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[89] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][113] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[115]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][129] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[118]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][144] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[119]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][145] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[120]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][146] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[121]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][147] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[123]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][149] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[125]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][151] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[36]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][44] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[51]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][59] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[62]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][70] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][20]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[28] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][21]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[29] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/S[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag_carry__0_i_5 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[69]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][77] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[72]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][80] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[73]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][81] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[75]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][83] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[81]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][89] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/sel. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/rCtrValue[0]_i_2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rValid[1]_i_2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[12] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[13] INFO: [Physopt 32-661] Optimized 6 nets. Re-placed 6 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 6 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 6 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-187.768 | Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.47 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23455 Phase 14 Placement Based Optimization | Checksum: 135273a80 Time (s): cpu = 00:10:50 ; elapsed = 00:03:13 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 15 MultiInst Placement Optimization INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter_reg[0]_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/select_reg/pipeline_inst/rPacketCounter[3]_i_9/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rPacketCounter[3]_i_8/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter[3]_i_4/O INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 15 MultiInst Placement Optimization | Checksum: 150e4a12b Time (s): cpu = 00:11:48 ; elapsed = 00:03:30 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4427 ; free virtual = 23454 Phase 16 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-241] No nets found for rewiring () optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23455 Phase 16 Rewire | Checksum: 150e4a12b Time (s): cpu = 00:11:50 ; elapsed = 00:03:32 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 17 Critical Cell Optimization INFO: [Physopt 32-46] Identified 5 candidate nets for critical-cell optimization. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/clear_repN was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/out[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23455 Phase 17 Critical Cell Optimization | Checksum: 1848f61fc Time (s): cpu = 00:12:00 ; elapsed = 00:03:37 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 18 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 18 DSP Register Optimization | Checksum: 1848f61fc Time (s): cpu = 00:12:01 ; elapsed = 00:03:37 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4428 ; free virtual = 23454 Phase 19 BRAM Register Optimization INFO: [Physopt 32-665] Processed cell nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/PktFifo_inst/RAM/RAM_reg_3. 72 registers were pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 72 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.504 | TNS=-187.768 | Netlist sorting complete. Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.69 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 19 BRAM Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:35 ; elapsed = 00:04:04 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 20 URAM Register Optimization INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 20 URAM Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:36 ; elapsed = 00:04:04 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 21 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 21 Shift Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:37 ; elapsed = 00:04:06 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 22 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 22 DSP Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:38 ; elapsed = 00:04:06 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 23 BRAM Register Optimization INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 23 BRAM Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:39 ; elapsed = 00:04:07 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 24 URAM Register Optimization INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 24 URAM Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:40 ; elapsed = 00:04:08 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 25 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 25 Shift Register Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:41 ; elapsed = 00:04:09 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 26 Critical Pin Optimization INFO: [Physopt 32-606] Identified 11 candidate nets for critical-pin optimization. INFO: [Physopt 32-608] Optimized 5 nets. Swapped 69 pins. INFO: [Physopt 32-775] End 1 Pass. Optimized 5 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 69 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.343 | TNS=-94.073 | Netlist sorting complete. Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.47 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23418 Phase 26 Critical Pin Optimization | Checksum: b230a7b1 Time (s): cpu = 00:12:43 ; elapsed = 00:04:12 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4391 ; free virtual = 23417 Phase 27 Very High Fanout Optimization INFO: [Physopt 32-76] Pass 1. Identified 100 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/rRst. Replicated 3 times. INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_6/MUX_TUPLE_p[1402]_i_3_n_0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_6/MUX_TUPLE_p[1402]_i_2_n_0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_1_reset was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_22/valid_2. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_1/E[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_20/E[0]. Replicated 6 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_17/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_21/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_10/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 4 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_11/E[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_12/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_13/valid_2. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_14/E[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_9/E[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_8/MUX_TUPLE_p_reg[1402]_0[0]. Replicated 5 times. INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/tuple_out_TUPLE0_VALID was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_5/E[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl/TopPipe_lvl_t_inst/stage_0/valid_1. Replicated 4 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2_reset. Replicated 4 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_4/valid_6. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_4/p_0_in[1]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_4/p_0_in[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_4/p_0_in[2]. Replicated 5 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2/tupleForward_inst/PktEop_d_1. Replicated 3 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_2/valid_6. Replicated 4 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_4/p_0_in[3]. Replicated 4 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_10/valid_6. Replicated 2 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_9/valid_6. Replicated 2 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_11/valid_6. Replicated 2 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_0/data_i8_reg[446]_0[2]. Replicated 1 times. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/rRst was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_RESET_clk_line/clk_line_rst_high. Replicated 1 times. INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/user_reset. Replicated 2 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_0/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_1/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_2/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_3/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_4/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_5/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_6/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_7/shift_i8[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/TupleMerge_inst/shiftFieldData_0/data_i8_reg[446]_0[3]. Replicated 1 times. INFO: [Physopt 32-232] Optimized 38 nets. Created 126 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 38 nets or cells. Created 126 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.343 | TNS=-94.073 | Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4397 ; free virtual = 23424 Phase 27 Very High Fanout Optimization | Checksum: d67452a7 Time (s): cpu = 00:19:26 ; elapsed = 00:07:57 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4396 ; free virtual = 23423 Phase 28 Placement Based Optimization INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][61]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][69] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][27]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][35] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][57]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][65] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][59]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][67] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rRdPtrPlus1[2]_i_1__15 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][50]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[58] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][51]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[59] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][23]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][31] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][48]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][67]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[75] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][69]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[77] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][36]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[44] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][37]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[45] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][71]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[79] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][72]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[80] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][73]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[81] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][74]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[82] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][75]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[83] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][83]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[91] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][85]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[93] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][86]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[94] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][112]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[126] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][113]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[127] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][114]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[128] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][115]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[129] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][4]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[12] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[17] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[1] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[2] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[103] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][97]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[105] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][113] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][118]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][144] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][123]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][149] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][100]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][108] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][31]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][39] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][46]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][54] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][70]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][78] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][84]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][92] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][88]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][96] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/S[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag_carry__0_i_5 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][20]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][28] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][94]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][102] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][95]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][103] INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/gen_stages[1].rData_reg[1][2]_0[1]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/_wTxMuxSelectDataEndFlag_carry__0_i_7 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][130]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[156] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][131]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[157] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/WR_FULL. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rFull_reg INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wCmpFull. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rFull2_i_1__0 INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/WEA0. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/rRAM_reg_0_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rFull_i_1__4_n_0. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rFull_i_1__4 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][80]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[88] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][81]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[89] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/gen_stages[1].rData_reg[1][2]_0[3]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag_carry__0_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][0]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][17]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[25] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][20]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[28] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][21]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[29] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[116]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][130] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[117]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][131] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[127]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][153] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[41]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][49] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][99] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[107]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][115] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[19]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][27] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[40]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][48] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[42]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][50] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[96]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][104] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[98]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][106] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[99]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][107] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/gen_stages[1].rData_reg[1][2]_0[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/compute_reg/pipeline_inst/_wTxMuxSelectDataEndFlag_carry__0_i_6 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][124]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[150] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][125]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[151] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][126]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[152] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][127]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[153] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][128]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[154] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][129]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[155] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][18] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][19] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][20] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][14]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][22] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][15]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][23] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][13] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][14] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][15] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/gen_stages[1].rData_reg[1][2]_0[1]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag_carry__0_i_3 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[18] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[19] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][12]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[20] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][13]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[21] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][14]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[22] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][15]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[23] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][18]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][26] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][16]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][24] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][21]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][29] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][16] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[33]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][41] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[35]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][43] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][34]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][42] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][38]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][46] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][43]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][51] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][100]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[108] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][101]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[109] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][102]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[110] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][103]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[111] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][104]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[112] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][105]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[113] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][118]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[144] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][119]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[145] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][120]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[146] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][121]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[147] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][122]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[148] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][123]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[149] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][88]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[96] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][89]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[97] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][90]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[98] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[99] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][92]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[100] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][26]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][34] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][44]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][52] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][45]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][53] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][47]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][55] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][48]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][56] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][49]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][57] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][53]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][61] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][91]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][99] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][107]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[115] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][108]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[116] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][109]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[117] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][110]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[118] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][111]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[119] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[106]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][114] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[64]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][72] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[65]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][73] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[66]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][74] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[68]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][76] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[82]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][90] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[87]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][95] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/gen_stages[1].rData_reg[1][2]_0[2]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag_carry__0_i_2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][0] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[39]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][47] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[52]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][60] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[53]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][61] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[76]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][84] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[77]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][85] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[78]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][86] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[79]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/gen_stages[1].rData_reg[1][87] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN_1. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/_wTxMuxSelectReady. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rValid[1]_i_2 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/clear_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/rCtrValue[0]_i_1_replica INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[10]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[10] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[11]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[11] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[5]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[5] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[6]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[6] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[7]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[7] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[8]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[8] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[9]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[9] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][28]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[36] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][29]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[37] INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][30]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[38] INFO: [Physopt 32-661] Optimized 3 nets. Re-placed 3 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 3 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 3 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.343 | TNS=-93.822 | Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4396 ; free virtual = 23423 Phase 28 Placement Based Optimization | Checksum: b86b36dc Time (s): cpu = 00:20:54 ; elapsed = 00:08:15 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4395 ; free virtual = 23423 Phase 29 MultiInst Placement Optimization INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1/O INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica/O INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.45 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4395 ; free virtual = 23423 Phase 29 MultiInst Placement Optimization | Checksum: 16aa3538e Time (s): cpu = 00:21:07 ; elapsed = 00:08:21 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4395 ; free virtual = 23423 Phase 30 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.343 | TNS=-93.822 | INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Optimizations did not improve timing on the net. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1 INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1/O INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica/O INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/s_axis_rq_tready[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][101] INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][93]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1 INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1 INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][173]_i_1/O INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/gen_stages[1].rData[1][131]_i_1__1_replica/O INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/s_axis_rq_tready[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1. Optimizations did not improve timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.343 | TNS=-93.822 | Phase 30 Critical Path Optimization | Checksum: 1a0b8e714 Time (s): cpu = 00:21:51 ; elapsed = 00:08:33 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4395 ; free virtual = 23423 Phase 31 BRAM Enable Optimization Phase 31 BRAM Enable Optimization | Checksum: 1a0b8e714 Time (s): cpu = 00:21:53 ; elapsed = 00:08:35 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4396 ; free virtual = 23424 Phase 32 Hold Fix Optimization INFO: [Physopt 32-668] Estimated Timing Summary | WNS=-0.343 | TNS=-93.822 | WHS=-0.388 | THS=-1352.976 | INFO: [Physopt 32-45] Identified 329 candidate nets for hold slack optimization. INFO: [Physopt 32-234] Optimized 323 nets. Inserted 0 new ZHOLD_DELAYs. Calibrated 0 existing ZHOLD_DELAYs. Inserted 323 buffers. INFO: [Physopt 32-668] Estimated Timing Summary | WNS=-0.343 | TNS=-93.822 | WHS=-0.324 | THS=-1260.569 | Phase 32 Hold Fix Optimization | Checksum: 183b13308 Time (s): cpu = 00:23:12 ; elapsed = 00:08:56 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4263 ; free virtual = 23290 Netlist sorting complete. Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.72 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4276 ; free virtual = 23304 INFO: [Physopt 32-669] Post Physical Optimization Timing Summary | WNS=-0.343 | TNS=-93.822 | WHS=-0.324 | THS=-1260.569 | Summary of Physical Synthesis Optimizations ============================================ -------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | -------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Fanout | 0.085 | 103.889 | 14 | 0 | 10 | 3 | 3 | 00:00:22 | | Placement Based | 0.085 | 66.619 | 0 | 0 | 75 | 0 | 4 | 00:01:06 | | MultiInst Placement | 0.000 | -2.828 | 0 | 0 | 1 | 0 | 4 | 00:00:48 | | Rewire | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 3 | 00:00:03 | | Critical Cell | 0.000 | 3.394 | 10 | 0 | 12 | 0 | 3 | 00:00:19 | | Slr Crossing | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 | | BRAM Register | 0.000 | 0.000 | 72 | 0 | 1 | 0 | 2 | 00:00:25 | | URAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 | | Shift Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:01 | | Critical Pin | 0.161 | 93.695 | 0 | 0 | 5 | 0 | 1 | 00:00:01 | | Very High Fanout | 0.000 | 0.000 | 126 | 0 | 38 | 2 | 1 | 00:03:43 | | BRAM Enable | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | Critical Path | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:11 | | Total | 0.331 | 264.769 | 222 | 0 | 142 | 5 | 30 | 00:07:00 | -------------------------------------------------------------------------------------------------------------------------------------------------------------------- Summary of Hold Fix Optimizations ================================= -------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WHS Gain (ns) | THS Gain (ns) | Added LUTs | Added FFs | Optimized Nets | Dont Touch | Iterations | Elapsed | -------------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT1 and ZHOLD Insertion | 0.063 | 92.407 | 323 | 0 | 323 | 0 | 1 | 00:00:09 | | Total | 0.063 | 92.407 | 323 | 0 | 323 | 0 | 1 | 00:00:09 | -------------------------------------------------------------------------------------------------------------------------------------------------------------- Ending Physical Synthesis Task | Checksum: 5536e89c Time (s): cpu = 00:23:13 ; elapsed = 00:08:57 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4276 ; free virtual = 23304 INFO: [Common 17-83] Releasing license: Implementation 1524 Infos, 160 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:25:52 ; elapsed = 00:09:41 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4709 ; free virtual = 23737 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:45 ; elapsed = 00:00:18 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4021 ; free virtual = 23756 INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:16 ; elapsed = 00:01:44 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4653 ; free virtual = 23844 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-18] Clock Placer Checks: Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i (GTHE2_CHANNEL.TXOUTCLK) is locked to GTHE2_CHANNEL_X1Y23 control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: ec95d42 ConstDB: 0 ShapeSum: 383ba574 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 13f77aa3a Time (s): cpu = 00:01:01 ; elapsed = 00:01:01 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4500 ; free virtual = 23690 Post Restoration Checksum: NetGraph: 755780cb NumContArr: ca20296f Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 13f77aa3a Time (s): cpu = 00:01:13 ; elapsed = 00:01:13 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4503 ; free virtual = 23694 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 13f77aa3a Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4424 ; free virtual = 23615 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 13f77aa3a Time (s): cpu = 00:01:18 ; elapsed = 00:01:18 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4424 ; free virtual = 23615 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 24991dd09 Time (s): cpu = 00:04:36 ; elapsed = 00:02:25 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4172 ; free virtual = 23363 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.137 | TNS=-4.317 | WHS=-0.904 | THS=-29817.598| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 226928804 Time (s): cpu = 00:07:11 ; elapsed = 00:03:05 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4122 ; free virtual = 23313 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.137 | TNS=-4.005 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 1be59df93 Time (s): cpu = 00:07:12 ; elapsed = 00:03:06 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4095 ; free virtual = 23287 Phase 2 Router Initialization | Checksum: 231d14d05 Time (s): cpu = 00:07:13 ; elapsed = 00:03:07 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4094 ; free virtual = 23286 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 1d7b67090 Time (s): cpu = 00:12:57 ; elapsed = 00:04:23 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4053 ; free virtual = 23245 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 31705 Number of Nodes with overlaps = 1870 Number of Nodes with overlaps = 382 Number of Nodes with overlaps = 83 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.264 | TNS=-26.695| WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1b6f39fbc Time (s): cpu = 00:26:00 ; elapsed = 00:07:21 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4055 ; free virtual = 23247 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 107 Number of Nodes with overlaps = 65 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.291 | TNS=-25.694| WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: cb56b2be Time (s): cpu = 00:27:50 ; elapsed = 00:08:12 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4049 ; free virtual = 23241 Phase 4 Rip-up And Reroute | Checksum: cb56b2be Time (s): cpu = 00:27:51 ; elapsed = 00:08:13 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4049 ; free virtual = 23241 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 9825de82 Time (s): cpu = 00:28:25 ; elapsed = 00:08:21 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4028 ; free virtual = 23220 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.185 | TNS=-11.111| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 22b0ba517 Time (s): cpu = 00:28:33 ; elapsed = 00:08:24 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4029 ; free virtual = 23221 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 22b0ba517 Time (s): cpu = 00:28:34 ; elapsed = 00:08:25 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4029 ; free virtual = 23221 Phase 5 Delay and Skew Optimization | Checksum: 22b0ba517 Time (s): cpu = 00:28:35 ; elapsed = 00:08:26 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4029 ; free virtual = 23221 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 197b1443d Time (s): cpu = 00:29:12 ; elapsed = 00:08:36 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4033 ; free virtual = 23225 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.186 | TNS=-11.250| WHS=-0.074 | THS=-0.329 | Phase 6.1 Hold Fix Iter | Checksum: 2158f047e Time (s): cpu = 00:29:23 ; elapsed = 00:08:39 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4012 ; free virtual = 23204 Phase 6 Post Hold Fix | Checksum: 24c84397d Time (s): cpu = 00:29:24 ; elapsed = 00:08:41 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4012 ; free virtual = 23204 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 20.5735 % Global Horizontal Routing Utilization = 20.3181 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 2x2 Area, Max Cong = 88.2883%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X132Y258 -> INT_R_X133Y259 INT_L_X130Y254 -> INT_R_X131Y255 INT_L_X130Y252 -> INT_R_X131Y253 INT_L_X130Y250 -> INT_R_X131Y251 South Dir 2x2 Area, Max Cong = 89.1892%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X132Y248 -> INT_R_X133Y249 INT_L_X132Y246 -> INT_R_X133Y247 INT_L_X132Y244 -> INT_R_X133Y245 East Dir 1x1 Area, Max Cong = 92.6471%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X59Y454 -> INT_R_X59Y454 INT_R_X65Y428 -> INT_R_X65Y428 INT_L_X62Y425 -> INT_L_X62Y425 INT_L_X64Y425 -> INT_L_X64Y425 INT_R_X65Y425 -> INT_R_X65Y425 West Dir 1x1 Area, Max Cong = 92.6471%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X21Y374 -> INT_R_X21Y374 INT_R_X27Y368 -> INT_R_X27Y368 INT_R_X23Y366 -> INT_R_X23Y366 INT_L_X78Y342 -> INT_L_X78Y342 INT_R_X67Y341 -> INT_R_X67Y341 ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 2 Aspect Ratio: 0.666667 Sparse Ratio: 1.5625 Direction: South ---------------- Congested clusters found at Level 1 Effective congestion level: 2 Aspect Ratio: 0.333333 Sparse Ratio: 0.75 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 1 Aspect Ratio: 0.75 Sparse Ratio: 1.75 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5 Phase 7 Route finalize | Checksum: 28b456797 Time (s): cpu = 00:29:40 ; elapsed = 00:08:48 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4006 ; free virtual = 23198 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 28b456797 Time (s): cpu = 00:29:41 ; elapsed = 00:08:48 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4003 ; free virtual = 23195 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_gt_common_block/gthe2_common_0_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y9/GTNORTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y23/GTREFCLK1 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gth_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y5/GTREFCLK1 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y22/GTREFCLK1 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y21/GTREFCLK1 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y20/GTREFCLK1 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y19/GTSOUTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gth_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y4/GTSOUTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y18/GTSOUTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y17/GTSOUTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y16/GTSOUTHREFCLK0 Phase 9 Depositing Routes | Checksum: 2822c1354 Time (s): cpu = 00:30:01 ; elapsed = 00:09:08 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4025 ; free virtual = 23217 Phase 10 Post Router Timing Phase 10.1 Update Timing Phase 10.1 Update Timing | Checksum: 1de2179a0 Time (s): cpu = 00:30:38 ; elapsed = 00:09:19 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4031 ; free virtual = 23223 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.186 | TNS=-11.250| WHS=0.010 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 10 Post Router Timing | Checksum: 1de2179a0 Time (s): cpu = 00:30:39 ; elapsed = 00:09:20 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4031 ; free virtual = 23223 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:30:39 ; elapsed = 00:09:20 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4359 ; free virtual = 23551 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 1554 Infos, 162 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:31:21 ; elapsed = 00:09:50 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4361 ; free virtual = 23554 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:49 ; elapsed = 00:00:21 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 3337 ; free virtual = 23416 INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:21 ; elapsed = 00:01:47 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 4125 ; free virtual = 23516 INFO: [runtcl-4] Executing : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx Command: report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Coretcl 2-168] The results of DRC are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:01:47 ; elapsed = 00:00:34 . Memory (MB): peak = 7938.488 ; gain = 0.000 ; free physical = 3938 ; free virtual = 23331 INFO: [runtcl-4] Executing : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx Command: report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 8 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:06:31 ; elapsed = 00:01:38 . Memory (MB): peak = 8491.820 ; gain = 553.332 ; free physical = 1798 ; free virtual = 21200 INFO: [runtcl-4] Executing : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx Command: report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 1566 Infos, 163 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:03:41 ; elapsed = 00:01:16 . Memory (MB): peak = 8955.473 ; gain = 463.652 ; free physical = 1467 ; free virtual = 20879 INFO: [runtcl-4] Executing : report_route_status -file top_route_status.rpt -pb top_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:01:02 ; elapsed = 00:00:19 . Memory (MB): peak = 9457.984 ; gain = 502.512 ; free physical = 1269 ; free virtual = 20687 INFO: [runtcl-4] Executing : report_incremental_reuse -file top_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. INFO: [runtcl-4] Executing : report_clock_utilization -file top_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:01:09 ; elapsed = 00:01:09 . Memory (MB): peak = 9457.984 ; gain = 0.000 ; free physical = 1263 ; free virtual = 20681 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs Command: phys_opt_design -directive AggressiveExplore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 99.8% nets are fully routed) INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AggressiveExplore INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Netlist sorting complete. Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.49 . Memory (MB): peak = 9490.000 ; gain = 0.000 ; free physical = 1249 ; free virtual = 20670 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.183 | TNS=-10.888 | WHS=0.010 | THS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1b914bab1 Time (s): cpu = 00:03:26 ; elapsed = 00:01:02 . Memory (MB): peak = 9490.000 ; gain = 0.000 ; free physical = 940 ; free virtual = 20361 Phase 2 Critical Path Optimization INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.183 | TNS=-10.888 | WHS=0.010 | THS=0.000 | INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/hdr_input_reg/pipeline_inst/gen_stages[1].rData_reg[1][173][97]. Optimizations did not improve timing on the net. INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.063 | TNS=-1.501 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Critial path length was reduced through logic transformation on cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1_comp. INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.045 | TNS=-1.059 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[0]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg[0] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[0]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.045 | TNS=-1.059 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/rPacketCounter_reg__0[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/E[0]. Critial path length was reduced through logic transformation on cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].input_pipeline_inst_/pipeline_inst/rPacketCounter[3]_i_1__0_comp. INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rPacketCounter_reg[0]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.040 | TNS=-0.878 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][157]_0[0]. Critial path length was reduced through logic transformation on cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData[1][157]_i_1__1_comp_1. INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_trans_inst/input_inst/pipeline_inst/wTxPktReady_repN. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.039 | TNS=-0.296 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][34]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[42] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][34]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.039 | TNS=-0.257 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][35]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[43] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][35]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.039 | TNS=-0.217 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][36]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[44] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][36]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.039 | TNS=-0.178 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][37]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[45] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][37]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.039 | TNS=-0.138 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][38]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[46] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][38]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.039 | TNS=-0.099 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][39]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[47] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][39]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.010 | TNS=-0.059 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][40]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[48] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][40]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.010 | TNS=-0.049 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-663] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][41]. Re-placed instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[49] INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][41]. Optimization improves timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.010 | TNS=-0.039 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][42]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/_wTxMuxSelectDataEndFlag. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/S[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag0[15]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][157][42]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/rCtrValue_reg[4]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/ready_reg/pipeline_inst/gen_stages[1].rData_reg[1][173]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/_wTxMuxSelectDataEndFlag. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/S[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_alignment_inst/pktctr_inst/_wTxMuxSelectDataEndFlag0[15]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/txhf_inst/fifo_inst/mem/wRdEn. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1. Optimizations did not improve timing on the net. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.010 | TNS=-0.039 | WHS=0.006 | THS=0.000 | Phase 2 Critical Path Optimization | Checksum: 1b914bab1 Time (s): cpu = 00:20:33 ; elapsed = 00:09:46 . Memory (MB): peak = 9685.402 ; gain = 195.402 ; free physical = 906 ; free virtual = 20327 Phase 3 Hold Fix Optimization INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.010 | TNS=-0.039 | WHS=0.006 | THS=0.000 | INFO: [Physopt 32-45] Identified 11 candidate nets for hold slack optimization. INFO: [Physopt 32-234] Optimized 11 nets. Inserted 0 new ZHOLD_DELAYs. Calibrated 0 existing ZHOLD_DELAYs. Inserted 11 buffers. INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.010 | TNS=-0.039 | WHS=0.006 | THS=0.000 | Phase 3 Hold Fix Optimization | Checksum: 1b914bab1 Time (s): cpu = 00:24:27 ; elapsed = 00:12:55 . Memory (MB): peak = 9685.402 ; gain = 195.402 ; free physical = 902 ; free virtual = 20324 Netlist sorting complete. Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.46 . Memory (MB): peak = 9685.402 ; gain = 0.000 ; free physical = 903 ; free virtual = 20324 INFO: [Physopt 32-669] Post Physical Optimization Timing Summary | WNS=-0.010 | TNS=-0.039 | WHS=0.006 | THS=0.000 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Critical Path | 0.173 | 10.849 | 0 | 0 | 13 | 0 | 1 | 00:08:41 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Summary of Hold Fix Optimizations ================================= -------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WHS Gain (ns) | THS Gain (ns) | Added LUTs | Added FFs | Optimized Nets | Dont Touch | Iterations | Elapsed | -------------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT1 and ZHOLD Insertion | 0.000 | 0.000 | 11 | 0 | 11 | 0 | 1 | 00:03:09 | | Total | 0.000 | 0.000 | 11 | 0 | 11 | 0 | 1 | 00:03:09 | -------------------------------------------------------------------------------------------------------------------------------------------------------------- Ending Physical Synthesis Task | Checksum: 1b914bab1 Time (s): cpu = 00:24:28 ; elapsed = 00:12:56 . Memory (MB): peak = 9685.402 ; gain = 195.402 ; free physical = 908 ; free virtual = 20330 INFO: [Common 17-83] Releasing license: Implementation 1651 Infos, 164 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:24:41 ; elapsed = 00:13:09 . Memory (MB): peak = 9685.402 ; gain = 227.418 ; free physical = 1644 ; free virtual = 21066 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:51 ; elapsed = 00:00:21 . Memory (MB): peak = 9685.402 ; gain = 0.000 ; free physical = 656 ; free virtual = 20963 INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_postroute_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:21 ; elapsed = 00:01:47 . Memory (MB): peak = 9685.402 ; gain = 0.000 ; free physical = 1403 ; free virtual = 21024 INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -warn_on_violation -file top_timing_summary_postroute_physopted.rpt -pb top_timing_summary_postroute_physopted.pb -rpx top_timing_summary_postroute_physopted.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:03:34 ; elapsed = 00:00:46 . Memory (MB): peak = 9685.402 ; gain = 0.000 ; free physical = 1510 ; free virtual = 21137 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_postroute_physopted.rpt -pb top_bus_skew_postroute_physopted.pb -rpx top_bus_skew_postroute_physopted.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ehndy8vbflb0gxuke3lnsjm_77/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ehndy8vbflb0gxuke3lnsjm_77/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/rc2oqgemebaubffc_998/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/rc2oqgemebaubffc_998/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xt6i6t0dtbr9k9ux4848l_2541/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xt6i6t0dtbr9k9ux4848l_2541/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/zmtz6gstdn71pkc38oscb260fx_746/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/zmtz6gstdn71pkc38oscb260fx_746/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xtsdogepbxcg3t8fqtbed8as0e1l_2610/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xtsdogepbxcg3t8fqtbed8as0e1l_2610/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. Command: write_bitstream -force top.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems. Evaluation cores found in this design: IP core 'axi_10g_ethernet_nonshared' (bd_7ad4) was generated with multiple features: IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license. IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license. IP core 'bd_7ad4_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license. IP core 'axi_10g_ethernet_shared' (bd_a1aa) was generated with multiple features: IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license. IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license. IP core 'bd_a1aa_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license. Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation. Running DRC as a precondition to command write_bitstream INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PLBUFGOPT-1] Non-Optimal connections to BUFG: A non-muxed BUFG control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1 is driven by another global buffer control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica. Remove non-muxed BUFG if it is not desired WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/ENBWREN (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[0] (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[1] (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[2] (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC RTSTAT-10] No routable loads: 350 net(s) have no routable loads. The problem bus(es) and/or net(s) are control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i... and (the first 15 of 70 listed). INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_4/editor_inst/PktFifo_inst/RAM/RAM_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/PktFifo_inst/RAM/RAM_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_10) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_8) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_10) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_8) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_10) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_8) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [Common 17-14] Message 'DRC REQP-181' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 52 Warnings, 422 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Bitstream compression saved 65812608 bits. Writing bitstream ./top.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Common 17-83] Releasing license: Implementation 1818 Infos, 217 Warnings, 2 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:08:09 ; elapsed = 00:04:06 . Memory (MB): peak = 9776.414 ; gain = 91.012 ; free physical = 1442 ; free virtual = 21096 INFO: [Common 17-206] Exiting Vivado at Mon Jul 29 20:16:10 2019... *** Running vivado with args -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source top.tcl -notrace Command: open_checkpoint top_postroute_physopt.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1183.336 ; gain = 0.000 ; free physical = 9123 ; free virtual = 28843 INFO: [Netlist 29-17] Analyzing 6081 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2018.2 INFO: [Device 21-403] Loading part xc7vx690tffg1761-3 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 4773.836 ; gain = 502.727 ; free physical = 5851 ; free virtual = 25581 Restored from archive | CPU: 20.850000 secs | Memory: 509.935951 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 4773.836 ; gain = 502.727 ; free physical = 5851 ; free virtual = 25581 INFO: [Project 1-111] Unisim Transformation Summary: A total of 840 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 2 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 79 instances RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 24 instances RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 525 instances RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 151 instances RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 24 instances SRLC16E => SRL16E: 1 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2018.2 (64-bit) build 2258646 open_checkpoint: Time (s): cpu = 00:02:07 ; elapsed = 00:03:19 . Memory (MB): peak = 4773.836 ; gain = 3590.500 ; free physical = 5966 ; free virtual = 25696 INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ehndy8vbflb0gxuke3lnsjm_77/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ehndy8vbflb0gxuke3lnsjm_77/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/rc2oqgemebaubffc_998/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/rc2oqgemebaubffc_998/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/d4cl8nwtlfqqa3qq1emn6smhnhrj_2144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xt6i6t0dtbr9k9ux4848l_2541/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xt6i6t0dtbr9k9ux4848l_2541/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/zmtz6gstdn71pkc38oscb260fx_746/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/zmtz6gstdn71pkc38oscb260fx_746/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/y0o0b5b83atg8om0jqdqe2p3pwoxl_1489/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vbsfwqsy6fejb9tjlqq1_2668/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/v25jqojnept4a2izwn4c0gio6doe0h_1269/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xtsdogepbxcg3t8fqtbed8as0e1l_2610/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xtsdogepbxcg3t8fqtbed8as0e1l_2610/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xpemdowtjrj47j8atnb65h4v07_1130/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lci0djz2hlarkew5g4z4wemft697fr_2582/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. Command: write_bitstream -force top.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems. Evaluation cores found in this design: IP core 'axi_10g_ethernet_nonshared' (bd_7ad4) was generated with multiple features: IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license. IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license. IP core 'bd_7ad4_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license. IP core 'axi_10g_ethernet_shared' (bd_a1aa) was generated with multiple features: IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license. IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license. IP core 'bd_a1aa_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license. Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PLBUFGOPT-1] Non-Optimal connections to BUFG: A non-muxed BUFG control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1 is driven by another global buffer control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica. Remove non-muxed BUFG if it is not desired WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/ENBWREN (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[0] (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[1] (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[2] (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC RTSTAT-10] No routable loads: 350 net(s) have no routable loads. The problem bus(es) and/or net(s) are nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i... and (the first 15 of 70 listed). INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_4/editor_inst/PktFifo_inst/RAM/RAM_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/PktFifo_inst/RAM/RAM_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_10) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_8) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_10) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_8) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_10) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_8) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [Common 17-14] Message 'DRC REQP-181' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 52 Warnings, 422 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/app.elf INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Bitstream compression saved 65365248 bits. Writing bitstream ./top.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Common 17-83] Releasing license: Implementation 174 Infos, 52 Warnings, 1 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:07:59 ; elapsed = 00:04:13 . Memory (MB): peak = 6222.715 ; gain = 1440.875 ; free physical = 5602 ; free virtual = 25347 INFO: [Common 17-206] Exiting Vivado at Mon Jul 29 20:28:12 2019... [Mon Jul 29 20:28:13 2019] impl_1 finished wait_on_run: Time (s): cpu = 00:10:16 ; elapsed = 00:07:42 . Memory (MB): peak = 2183.465 ; gain = 0.000 ; free physical = 9275 ; free virtual = 29028 # open_run impl_1 INFO: [Netlist 29-17] Analyzing 6081 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2018.2 INFO: [Device 21-403] Loading part xc7vx690tffg1761-3 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 4982.980 ; gain = 503.727 ; free physical = 6042 ; free virtual = 25795 Restored from archive | CPU: 20.630000 secs | Memory: 509.936699 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 4982.980 ; gain = 503.727 ; free physical = 6042 ; free virtual = 25795 Generating merged BMM file for the design top 'top'... INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/app.elf INFO: [Project 1-111] Unisim Transformation Summary: A total of 840 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 2 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 79 instances RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 24 instances RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 525 instances RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 151 instances RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 24 instances SRLC16E => SRL16E: 1 instances open_run: Time (s): cpu = 00:02:05 ; elapsed = 00:03:18 . Memory (MB): peak = 4982.980 ; gain = 2799.516 ; free physical = 6158 ; free virtual = 25911 # write_bitstream -force ../bitfiles/$design.bit Command: write_bitstream -force ../bitfiles/simple_sume_switch.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t' CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems. Evaluation cores found in this design: IP core 'axi_10g_ethernet_nonshared' (bd_7ad4) was generated with multiple features: IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license. IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license. IP core 'bd_7ad4_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license. IP core 'axi_10g_ethernet_shared' (bd_a1aa) was generated with multiple features: IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license. IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license. IP core 'bd_a1aa_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license. Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation. Running DRC as a precondition to command write_bitstream INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PLBUFGOPT-1] Non-Optimal connections to BUFG: A non-muxed BUFG control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1 is driven by another global buffer control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica. Remove non-muxed BUFG if it is not desired WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE} WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/ENBWREN (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[0] (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[1] (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[2] (net: nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC RTSTAT-10] No routable loads: 350 net(s) have no routable loads. The problem bus(es) and/or net(s) are control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i... and (the first 15 of 70 listed). INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/os6w64j5c7ppfk9mxdkhsxvbhzqbx02l_1578/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/s01rsqufj7k6k4vnqmz3teozsv22_143/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/qyfmxlhxtgqyj78i3mu2sw5_2306/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_4/editor_inst/PktFifo_inst/RAM/RAM_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_5/editor_inst/PktFifo_inst/RAM/RAM_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_dummy_table_for_netpfga_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_10) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_8) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/emsxcy8c153tkouy17br04f_2299/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/l7152fs74u8zwxog2cx_2460/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ow8vk1v7n14yey1jc5d040hf1440r1x_695/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/owseb8koh0tm5b2cm23kfowmsv_348/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v2x1yvitwpecodsxcz4bwdpizcg445_375/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/d7gumo82gk6md4n6jh72oukr_1045/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/vxh8gue8epq6gxze_685/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wdeecdhsjseok1s3v750r3jb_550/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wip2u61mji55unuwjs6ipl7grolkp_1787/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_10) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_8) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wneadextejr1frvvs0h8_344/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/c1szjispkb2i6ti1o_2213/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_10) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_13) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_7) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_8) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/dkcs1lf2vu5dwmt01vw9eqs5xby_452/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_9) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/gp2sxhuvbjmdw26h21zj5zo4h94_979/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/osugxrkciuq7h54lwjvabg_1385/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/du6df7ou4c9jzix9kt8y8sp35_875/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/s8zvr35avia82az9e4ga7z_2508/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [Common 17-14] Message 'DRC REQP-181' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 52 Warnings, 422 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. Generating merged BMM file for the design top 'top'... INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/app.elf INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Bitstream compression saved 65365248 bits. Writing bitstream ../bitfiles/simple_sume_switch.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Common 17-83] Releasing license: Implementation 121 Infos, 52 Warnings, 1 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:07:57 ; elapsed = 00:04:11 . Memory (MB): peak = 6390.672 ; gain = 1407.691 ; free physical = 5814 ; free virtual = 25596 # exit INFO: [Common 17-206] Exiting Vivado at Mon Jul 29 20:35:42 2019... make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw' + date Mon Jul 29 20:35:42 CEST 2019 + cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles + mv simple_sume_switch.bit minip4.bit + cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.sh ./ + date Mon Jul 29 20:35:43 CEST 2019 + cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles/ + pwd -P + chmod u+x /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles/program_switch.sh + pwd -P + sudo bash -c . /home/nico/master-thesis/netpfga/bashinit && /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles/program_switch.sh rmmod: ERROR: Module sume_riffa is not currently loaded rlwrap: warning: your $TERM is 'screen' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device RUN loading image file. minip4.bit attempting to launch hw_server ****** Xilinx hw_server v2018.2 **** Build date : Jun 14 2018-20:18:37 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. INFO: hw_server application started INFO: Use Ctrl-C to exit hw_server application INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121 no target with id: 1 invoked from within "::tcf::eval -progress ::xsdb::no_print_progress {::tcf::cache_enter tcfchan#0 {tcf_cache_eval {process_tcf_actions_cache_client ::tcfclient#0::arg}}}" (procedure "::tcf::cache_eval_with_progress" line 2) invoked from within "::tcf::cache_eval_with_progress [dict get $arg chan] [list process_tcf_actions_cache_client $argvar] $progress" (procedure "process_tcf_actions" line 1) invoked from within "process_tcf_actions $arg" (procedure "tid2ctx" line 31) invoked from within "tid2ctx $chan [lindex $args 0]" (procedure "targets" line 30) invoked from within "targets 1" (file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl" line 32) Check programming FPGA or Reboot machine ! rmmod: ERROR: Module sume_riffa is not currently loaded modprobe: FATAL: Module sume_riffa not found in directory /lib/modules/4.15.0-54-generic nf0: ERROR while getting interface flags: No such device nf1: ERROR while getting interface flags: No such device nf2: ERROR while getting interface flags: No such device nf3: ERROR while getting interface flags: No such device