93 lines
5.2 KiB
Tcl
93 lines
5.2 KiB
Tcl
#
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# Copyright (c) 2015 University of Cambridge
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# All rights reserved.
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#
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# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
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# under National Science Foundation under Grant No. CNS-0855268,
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# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
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# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
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# as part of the DARPA MRC research programme.
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#
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# @NETFPGA_LICENSE_HEADER_START@
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#
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# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
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# license agreements. See the NOTICE file distributed with this work for
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# additional information regarding copyright ownership. NetFPGA licenses this
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# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at:
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#
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# http://www.netfpga-cic.org
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#
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# Unless required by applicable law or agreed to in writing, Work distributed
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# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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# CONDITIONS OF ANY KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations under the License.
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#
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# @NETFPGA_LICENSE_HEADER_END@
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# Set variables
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# CORE CONFIG parameters
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set sharedLogic "FALSE"
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set tdataWidth 256
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set convWidth [expr $tdataWidth/8]
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if { $sharedLogic eq "True" || $sharedLogic eq "TRUE" || $sharedLogic eq "true" } {
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set supportLevel 1
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} else {
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set supportLevel 0
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}
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create_ip -name axi_10g_ethernet -vendor xilinx.com -library ip -version 3.1 -module_name axi_10g_ethernet_nonshared
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set_property -dict [list CONFIG.Management_Interface {false}] [get_ips axi_10g_ethernet_nonshared]
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set_property -dict [list CONFIG.base_kr {BASE-R}] [get_ips axi_10g_ethernet_nonshared]
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set_property -dict [list CONFIG.SupportLevel $supportLevel] [get_ips axi_10g_ethernet_nonshared]
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set_property -dict [list CONFIG.autonegotiation {0}] [get_ips axi_10g_ethernet_nonshared]
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set_property -dict [list CONFIG.fec {0}] [get_ips axi_10g_ethernet_nonshared]
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set_property -dict [list CONFIG.Statistics_Gathering {0}] [get_ips axi_10g_ethernet_nonshared]
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set_property generate_synth_checkpoint false [get_files axi_10g_ethernet_nonshared.xci]
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reset_target all [get_ips axi_10g_ethernet_nonshared]
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generate_target all [get_ips axi_10g_ethernet_nonshared]
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create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_status
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set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] [get_ips fifo_generator_status]
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set_property -dict [list CONFIG.Performance_Options {First_Word_Fall_Through}] [get_ips fifo_generator_status]
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set_property -dict [list CONFIG.Input_Data_Width {458} CONFIG.Input_Depth {16}] [get_ips fifo_generator_status]
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set_property -dict [list CONFIG.Reset_Pin {false}] [get_ips fifo_generator_status]
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set_property -dict [list CONFIG.Output_Data_Width {458} CONFIG.Output_Depth {16}] [get_ips fifo_generator_status]
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set_property -dict [list CONFIG.Full_Flags_Reset_Value {0}] [get_ips fifo_generator_status]
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set_property -dict [list CONFIG.Use_Dout_Reset {false}] [get_ips fifo_generator_status]
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set_property -dict [list CONFIG.Data_Count_Width {4}] [get_ips fifo_generator_status]
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set_property -dict [list CONFIG.Write_Data_Count_Width {4}] [get_ips fifo_generator_status]
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set_property -dict [list CONFIG.Read_Data_Count_Width {4}] [get_ips fifo_generator_status]
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set_property -dict [list CONFIG.Full_Threshold_Assert_Value {15}] [get_ips fifo_generator_status]
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set_property -dict [list CONFIG.Full_Threshold_Negate_Value {14}] [get_ips fifo_generator_status]
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set_property -dict [list CONFIG.Empty_Threshold_Assert_Value {4}] [get_ips fifo_generator_status]
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set_property -dict [list CONFIG.Empty_Threshold_Negate_Value {5}] [get_ips fifo_generator_status]
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set_property generate_synth_checkpoint false [get_files fifo_generator_status.xci]
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reset_target all [get_ips fifo_generator_status]
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generate_target all [get_ips fifo_generator_status]
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create_ip -name util_vector_logic -vendor xilinx.com -library ip -version 2.0 -module_name inverter_0
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set_property -dict [list CONFIG.C_SIZE {1}] [get_ips inverter_0]
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set_property -dict [list CONFIG.C_OPERATION {not}] [get_ips inverter_0]
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set_property generate_synth_checkpoint false [get_files inverter_0.xci]
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reset_target all [get_ips inverter_0]
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generate_target all [get_ips inverter_0]
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create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_1_9
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set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM} CONFIG.Performance_Options {First_Word_Fall_Through} CONFIG.Input_Data_Width {1} CONFIG.Input_Depth {16} CONFIG.Output_Data_Width {1} CONFIG.Output_Depth {16} CONFIG.Data_Count_Width {4} CONFIG.Write_Data_Count_Width {4} CONFIG.Read_Data_Count_Width {4} CONFIG.Full_Threshold_Assert_Value {13} CONFIG.Full_Threshold_Negate_Value {12}] [get_ips fifo_generator_1_9]
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set_property generate_synth_checkpoint false [get_files fifo_generator_1_9.xci]
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reset_target all [get_ips fifo_generator_1_9]
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generate_target all [get_ips fifo_generator_1_9]
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