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20807 lines
2.9 MiB
20807 lines
2.9 MiB
+ date |
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Mit Jul 24 09:57:30 CEST 2019 |
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4 |
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+ make |
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make -C src/ clean |
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src' |
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat |
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src' |
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make -C testdata/ clean |
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata' |
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py |
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata' |
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rm -rf nf_sume_sdnet_ip/ |
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rm -f |
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rm -f sw/config_tables.c |
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make -C src/ |
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src' |
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p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4 |
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat |
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src' |
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make -C testdata/ |
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata' |
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./gen_testdata.py |
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Applying pkt on nf0 at 1: |
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Applying pkt on nf1 at 2: |
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Applying pkt on nf2 at 3: |
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Applying pkt on nf3 at 4: |
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nf0_applied times: [1] |
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nf1_applied times: [2] |
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nf2_applied times: [3] |
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nf3_applied times: [4] |
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap |
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap |
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata' |
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sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts |
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Xilinx SDNet Compiler version 2018.2, build 2342300 |
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Compilation successful |
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_externs.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ ./testdata/ ./sw/ --base_address 0x44020000 |
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_API.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000 |
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_CLI.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000 |
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI' |
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cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API |
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cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API |
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cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o libcam.so libcam.o CAM.o -lsumereg |
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI' |
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# The following command only applies if running P4_SWITCH Questa Simulation with Ubuntu |
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sed -i 's/vsim/vsim \-ldflags \"\-B\/usr\/lib\/x86\_64\-linux-gnu\"/g' nf_sume_sdnet_ip/SimpleSumeSwitch/questa.bash |
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# modify the P4_SWITCH_tb so that it writes the table configuration writes to a file |
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/modify_P4_SWITCH_tb.py nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv |
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# Fix introduced for SDNet 2017.4 |
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sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash |
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sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash |
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# Fix introduced for SDNet 2018.2 |
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sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash |
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sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash |
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cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/ |
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cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/ |
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cp testdata/*.axi nf_sume_sdnet_ip/SimpleSumeSwitch/ |
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+ date |
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Mit Jul 24 09:57:33 CEST 2019 |
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch |
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+ ./vivado_sim.bash |
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+ find -name '*.v' -o -name '*.vp' -o -name '*.sv' |
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+ xargs -I % /opt/Xilinx/Vivado/2018.2/bin/xvlog -sv % |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v" into library work |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp" into library work |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_Engine |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_0 |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_lookup_table_sec |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_lookup_table_sec_compute_control_nextSection |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_lookup_table_sec_compute_control_increment_offset |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_1 |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_nextSection |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_increment_offset |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec_compute_sume_metadata_dst_port |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec_compute_control_nextSection |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec_compute_control_increment_offset |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_sume_metadata_dst_port |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_nextSection |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_increment_offset |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_TopPipe_fl_temp |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_p_ethernet_dstAddr |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_p_ethernet_srcAddr |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_sume_metadata_dst_port |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_control_nextSection |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_control_increment_offset |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_2 |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_nextSection |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_increment_offset |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v" into library work |
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INFO: [VRFC 10-311] analyzing module S_RESETTER_lookup |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v" into library work |
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INFO: [VRFC 10-311] analyzing module S_RESETTER_line |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v" into library work |
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INFO: [VRFC 10-311] analyzing module S_RESETTER_control |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp" into library work |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_Engine |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0 |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_ErrorCheck |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_remove |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_nextSection |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_increment_offset |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoWriter |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo_RAM |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_LatencyBuffer |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo_RAM |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo_RAM |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoReader |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterDown |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterUp |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterSelect |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_BarrelShifterDown |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_UniShifterDown |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterDown |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterUp |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate_UniShifter2X |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataMux |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1 |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1_ErrorCheck |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_nextSection |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_increment_offset |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2 |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_ErrorCheck |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0 |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_insert |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_dstAddr |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_srcAddr |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_etherType |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_nextSection |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_increment_offset |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoWriter |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo_RAM |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_LatencyBuffer |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo_RAM |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo_RAM |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoReader |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterDown |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterUp |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterSelect |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_BarrelShifterDown |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_UniShifterDown |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownMask |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownTuple |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterDown |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterUp |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate_UniShifter2X |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataMux |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v" into library work |
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INFO: [VRFC 10-311] analyzing module TopDeparser_t |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp" into library work |
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INFO: [VRFC 10-311] analyzing module TopParser_t_Engine |
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INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0 |
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INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ErrorCheck |
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INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ExtractShifter |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dma_q_size |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf3_q_size |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf2_q_size |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf1_q_size |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf0_q_size |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_send_dig_to_cpu |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_drop |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dst_port |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_src_port |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_pkt_len |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_isValid |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_dstAddr |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_srcAddr |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_etherType |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_extracts_size |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_meta_unused |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_digest_data_1_unused |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_isValid |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_dstAddr |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_srcAddr |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_etherType |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_unused |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_digest_data_unused |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_dma_q_size |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf3_q_size |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf2_q_size |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf1_q_size |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf0_q_size |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_send_dig_to_cpu |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_drop |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_dst_port |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_src_port |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_pkt_len |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_nextSection |
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INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_increment_offset |
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INFO: [VRFC 10-311] analyzing module TopParser_t_reject |
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INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_nextSection |
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INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_increment_offset |
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INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_TupleForward |
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INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1 |
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INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ErrorCheck |
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INFO: [VRFC 10-311] analyzing module TopParser_t_accept |
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INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_nextSection |
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INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_increment_offset |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v" into library work |
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INFO: [VRFC 10-311] analyzing module TopParser_t |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_lookup_table_tuple_in_request.v" into library work |
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INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_lookup_table_tuple_in_request |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v" into library work |
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INFO: [VRFC 10-311] analyzing module glbl |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv" into library work |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_base |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_rst |
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INFO: [VRFC 10-311] analyzing module xpm_counter_updn |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit |
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INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_sync |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_async |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_axis |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv" into library work |
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INFO: [VRFC 10-311] analyzing module xpm_memory_base |
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INFO: [VRFC 10-311] analyzing module asym_bwe_bb |
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INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram |
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INFO: [VRFC 10-311] analyzing module xpm_memory_dprom |
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INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram |
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INFO: [VRFC 10-311] analyzing module xpm_memory_spram |
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INFO: [VRFC 10-311] analyzing module xpm_memory_sprom |
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INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv" into library work |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_single |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_gray |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_lookup_table_tuple_in_request.vp" into library work |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp" into library work |
|
ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37] |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.v" into library work |
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INFO: [VRFC 10-311] analyzing module S_CONTROLLER_SimpleSumeSwitch |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.vp" into library work |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_Engine |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_EngineStage_0 |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_lookup_table_req_lookup_request_key |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_nextSection |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_increment_offset |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v" into library work |
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/lookup_table_t.vp" into library work |
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INFO: [VRFC 10-311] analyzing module lookup_table_t_Wrap |
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INFO: [VRFC 10-311] analyzing module lookup_table_t_IntTop |
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INFO: [VRFC 10-311] analyzing module lookup_table_t_Lookup |
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INFO: [VRFC 10-311] analyzing module lookup_table_t_Hash_Lookup |
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INFO: [VRFC 10-311] analyzing module lookup_table_t_RamR1RW1 |
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INFO: [VRFC 10-311] analyzing module lookup_table_t_Cam |
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INFO: [VRFC 10-311] analyzing module lookup_table_t_Update |
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INFO: [VRFC 10-311] analyzing module lookup_table_t_Hash_Update |
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INFO: [VRFC 10-311] analyzing module lookup_table_t_Randmod4 |
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INFO: [VRFC 10-311] analyzing module lookup_table_t_Randmod4_Rnd |
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INFO: [VRFC 10-311] analyzing module lookup_table_t_Randmod5 |
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INFO: [VRFC 10-311] analyzing module lookup_table_t_Randmod5_Rnd |
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INFO: [VRFC 10-311] analyzing module lookup_table_t_csr |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv" into library work |
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INFO: [VRFC 10-311] analyzing module xpm_memory_base |
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INFO: [VRFC 10-311] analyzing module asym_bwe_bb |
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INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram |
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INFO: [VRFC 10-311] analyzing module xpm_memory_dprom |
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INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram |
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INFO: [VRFC 10-311] analyzing module xpm_memory_spram |
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INFO: [VRFC 10-311] analyzing module xpm_memory_sprom |
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INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_cdc.sv" into library work |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_single |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_gray |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/lookup_table_t.v" into library work |
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INFO: [VRFC 10-311] analyzing module lookup_table_t |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" into library work |
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INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch_tb |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v" into library work |
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INFO: [VRFC 10-311] analyzing module TB_System_Stim |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" into library work |
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INFO: [VRFC 10-311] analyzing module Check |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v" into library work |
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INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_INGRESS |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp" into library work |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp" into library work |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v" into library work |
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INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_EGRESS |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v" into library work |
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INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v" into library work |
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INFO: [VRFC 10-311] analyzing module glbl |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v" into library work |
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopDeparser |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v" into library work |
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for__OUT_ |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_fifo.sv" into library work |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_base |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_rst |
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INFO: [VRFC 10-311] analyzing module xpm_counter_updn |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit |
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INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_sync |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_async |
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INFO: [VRFC 10-311] analyzing module xpm_fifo_axis |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv" into library work |
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INFO: [VRFC 10-311] analyzing module xpm_memory_base |
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INFO: [VRFC 10-311] analyzing module asym_bwe_bb |
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INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram |
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INFO: [VRFC 10-311] analyzing module xpm_memory_dprom |
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INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram |
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INFO: [VRFC 10-311] analyzing module xpm_memory_spram |
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INFO: [VRFC 10-311] analyzing module xpm_memory_sprom |
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INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v" into library work |
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopParser |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv" into library work |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_single |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_gray |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst |
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INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work |
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_TopDeparser |
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work |
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser |
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+ true |
|
+ mkdir -p xsim.dir/xsc |
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+ find -name '*.c' |
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+ xargs /opt/Xilinx/Vivado/2018.2/bin/xsc -mt off -v 1 |
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Turned off multi-threading. |
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Running compilation flow |
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/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/CAM.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" -DXILINX_SIMULATOR |
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/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/user.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -DXILINX_SIMULATOR |
|
./Testbench/user.c: In function ‘register_write_control’: |
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./Testbench/user.c:37:5: warning: implicit declaration of function ‘SV_write_control’ [-Wimplicit-function-declaration] |
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SV_write_control(&sv_addr, &sv_data); |
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^~~~~~~~~~~~~~~~ |
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./Testbench/user.c: In function ‘register_read_control’: |
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./Testbench/user.c:51:5: warning: implicit declaration of function ‘SV_read_control’ [-Wimplicit-function-declaration] |
|
SV_read_control(&sv_addr, &sv_data); |
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^~~~~~~~~~~~~~~ |
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./Testbench/user.c: In function ‘CAM_Init’: |
|
./Testbench/user.c:88:76: warning: passing argument 9 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types] |
|
if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level)) |
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^~~~~~~~~~~~~~ |
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In file included from ./Testbench/user.c:7:0: |
|
./Testbench/CAM.h:169:5: note: expected ‘void (*)(addr_t, uint32_t) {aka void (*)(long long unsigned int, unsigned int)}’ but argument is of type ‘void (*)(uint32_t, uint32_t) {aka void (*)(unsigned int, unsigned int)}’ |
|
int CAM_Init_ValidateContext(
|
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^~~~~~~~~~~~~~~~~~~~~~~~ |
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./Testbench/user.c:88:92: warning: passing argument 10 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types] |
|
if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level)) |
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^~~~~~~~~~~~~ |
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In file included from ./Testbench/user.c:7:0: |
|
./Testbench/CAM.h:169:5: note: expected ‘uint32_t (*)(addr_t) {aka unsigned int (*)(long long unsigned int)}’ but argument is of type ‘uint32_t (*)(uint32_t) {aka unsigned int (*)(unsigned int)}’ |
|
int CAM_Init_ValidateContext(
|
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^~~~~~~~~~~~~~~~~~~~~~~~ |
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Done compilation |
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Linking with command: |
|
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ |
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|
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Running command : /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ |
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Done linking: "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" |
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+ /opt/Xilinx/Vivado/2018.2/bin/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl |
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Vivado Simulator 2018.2 |
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Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
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Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl |
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Multi-threading is on. Using 6 slave threads. |
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Starting static elaboration |
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Completed static elaboration |
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Starting simulation data flow analysis |
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Completed simulation data flow analysis |
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Time Resolution for simulation is 1ps |
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Compiling module work.S_RESETTER_line |
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Compiling module work.S_RESETTER_lookup |
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Compiling module work.S_RESETTER_control |
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Compiling module work.TopParser_t_EngineStage_0_ErrorC... |
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Compiling module work.TopParser_t_EngineStage_0_Extrac... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_TopPar... |
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Compiling module work.TopParser_t_start_compute_p_ethe... |
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Compiling module work.TopParser_t_start_compute_p_ethe... |
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Compiling module work.TopParser_t_start_compute_p_ethe... |
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Compiling module work.TopParser_t_start_compute_p_ethe... |
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Compiling module work.TopParser_t_start_compute_user_m... |
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Compiling module work.TopParser_t_start_compute_digest... |
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Compiling module work.TopParser_t_start_compute_sume_m... |
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Compiling module work.TopParser_t_start_compute_sume_m... |
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Compiling module work.TopParser_t_start_compute_sume_m... |
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Compiling module work.TopParser_t_start_compute_sume_m... |
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Compiling module work.TopParser_t_start_compute_sume_m... |
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Compiling module work.TopParser_t_start_compute_sume_m... |
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Compiling module work.TopParser_t_start_compute_sume_m... |
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Compiling module work.TopParser_t_start_compute_sume_m... |
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Compiling module work.TopParser_t_start_compute_sume_m... |
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Compiling module work.TopParser_t_start_compute_sume_m... |
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Compiling module work.TopParser_t_start_compute_contro... |
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Compiling module work.TopParser_t_start_compute_contro... |
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Compiling module work.TopParser_t_start |
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Compiling module work.TopParser_t_reject_compute_contr... |
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Compiling module work.TopParser_t_reject_compute_contr... |
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Compiling module work.TopParser_t_reject |
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Compiling module work.TopParser_t_EngineStage_0_TupleF... |
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Compiling module work.TopParser_t_EngineStage_0 |
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Compiling module work.TopParser_t_EngineStage_1_ErrorC... |
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Compiling module work.TopParser_t_accept_compute_contr... |
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Compiling module work.TopParser_t_accept_compute_contr... |
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Compiling module work.TopParser_t_accept |
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Compiling module work.TopParser_t_EngineStage_1 |
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Compiling module work.TopParser_t_Engine |
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Compiling module work.TopParser_t |
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Compiling module work.TopPipe_lvl_t_setup_compute_look... |
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Compiling module work.TopPipe_lvl_t_setup_compute_cont... |
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Compiling module work.TopPipe_lvl_t_setup_compute_cont... |
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Compiling module work.TopPipe_lvl_t_setup |
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Compiling module work.TopPipe_lvl_t_EngineStage_0 |
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Compiling module work.TopPipe_lvl_t_Engine |
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Compiling module work.TopPipe_lvl_t |
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Compiling module work.lookup_table_t_Hash_Lookup |
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Compiling module work.xpm_memory_base(MEMORY_SIZE=880,... |
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Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=88... |
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Compiling module work.lookup_table_t_RamR1RW1 |
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Compiling module work.lookup_table_t_Cam |
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Compiling module work.lookup_table_t_Lookup |
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Compiling module work.lookup_table_t_Hash_Update |
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Compiling module work.lookup_table_t_Randmod4_Rnd |
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Compiling module work.lookup_table_t_Randmod4 |
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Compiling module work.lookup_table_t_Randmod5_Rnd |
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Compiling module work.lookup_table_t_Randmod5 |
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Compiling module work.lookup_table_t_Update |
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Compiling module work.lookup_table_t_IntTop |
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Compiling module work.lookup_table_t_Wrap |
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Compiling module work.lookup_table_t_csr |
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Compiling module work.lookup_table_t |
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Compiling module work.TopPipe_lvl_0_t_lookup_table_sec... |
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Compiling module work.TopPipe_lvl_0_t_lookup_table_sec... |
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Compiling module work.TopPipe_lvl_0_t_lookup_table_sec |
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Compiling module work.TopPipe_lvl_0_t_EngineStage_0 |
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Compiling module work.TopPipe_lvl_0_t_do_nothing_0_sec... |
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Compiling module work.TopPipe_lvl_0_t_do_nothing_0_sec... |
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Compiling module work.TopPipe_lvl_0_t_do_nothing_0_sec |
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Compiling module work.TopPipe_lvl_0_t_send_to_all_port... |
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Compiling module work.TopPipe_lvl_0_t_send_to_all_port... |
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Compiling module work.TopPipe_lvl_0_t_send_to_all_port... |
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Compiling module work.TopPipe_lvl_0_t_send_to_all_port... |
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Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_... |
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Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_... |
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Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_... |
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Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_... |
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Compiling module work.TopPipe_lvl_0_t_swap_eth_address... |
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Compiling module work.TopPipe_lvl_0_t_swap_eth_address... |
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Compiling module work.TopPipe_lvl_0_t_swap_eth_address... |
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Compiling module work.TopPipe_lvl_0_t_swap_eth_address... |
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Compiling module work.TopPipe_lvl_0_t_swap_eth_address... |
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Compiling module work.TopPipe_lvl_0_t_swap_eth_address... |
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Compiling module work.TopPipe_lvl_0_t_swap_eth_address... |
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Compiling module work.TopPipe_lvl_0_t_EngineStage_1 |
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Compiling module work.TopPipe_lvl_0_t_sink_compute_con... |
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Compiling module work.TopPipe_lvl_0_t_sink_compute_con... |
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Compiling module work.TopPipe_lvl_0_t_sink |
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Compiling module work.TopPipe_lvl_0_t_EngineStage_2 |
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Compiling module work.TopPipe_lvl_0_t_Engine |
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Compiling module work.TopPipe_lvl_0_t |
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Compiling module work.TopDeparser_t_EngineStage_0_Erro... |
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Compiling module work.TopDeparser_t_extract_headers_se... |
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Compiling module work.TopDeparser_t_extract_headers_se... |
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Compiling module work.TopDeparser_t_extract_headers_se... |
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Compiling module work.TopDeparser_t_extract_headers_se... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_0 |
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Compiling module work.TopDeparser_t_EngineStage_1_Erro... |
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Compiling module work.TopDeparser_t_act_sec_compute_co... |
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Compiling module work.TopDeparser_t_act_sec_compute_co... |
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Compiling module work.TopDeparser_t_act_sec |
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Compiling module work.TopDeparser_t_EngineStage_1 |
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Compiling module work.TopDeparser_t_EngineStage_2_Erro... |
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Compiling module work.TopDeparser_t_emit_0_compute_con... |
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Compiling module work.TopDeparser_t_emit_0_compute__ST... |
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Compiling module work.TopDeparser_t_emit_0_compute__ST... |
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Compiling module work.TopDeparser_t_emit_0_compute__ST... |
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Compiling module work.TopDeparser_t_emit_0_compute_con... |
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Compiling module work.TopDeparser_t_emit_0_compute_con... |
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Compiling module work.TopDeparser_t_emit_0 |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2_Edit... |
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Compiling module work.TopDeparser_t_EngineStage_2 |
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Compiling module work.TopDeparser_t_Engine |
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Compiling module work.TopDeparser_t |
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Compiling module work.xpm_cdc_sync_rst(DEST_SYNC_FF=2,... |
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Compiling module work.xpm_fifo_rst(COMMON_CLOCK=0) |
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Compiling module work.xpm_fifo_reg_bit |
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9... |
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8... |
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8... |
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... |
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Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT... |
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Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=8) |
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Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT... |
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Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=9) |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.S_BRIDGER_for_lookup_table_tuple... |
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Compiling module work.S_PROTOCOL_ADAPTER_INGRESS |
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Compiling module work.S_PROTOCOL_ADAPTER_EGRESS |
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Compiling module work.xpm_fifo_rst_default |
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1... |
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9... |
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9... |
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... |
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... |
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Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... |
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... |
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=2... |
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1... |
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Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... |
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.S_SYNCER_for_TopParser |
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... |
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Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... |
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1... |
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Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... |
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.S_SYNCER_for_S_SYNCER_for_S_SYNC... |
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... |
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Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... |
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1... |
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Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... |
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8... |
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7... |
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7... |
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... |
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Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT... |
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Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=7) |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.S_SYNCER_for_S_SYNCER_for_TopDep... |
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... |
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Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... |
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1... |
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Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.S_SYNCER_for_TopDeparser |
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME... |
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2... |
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Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="... |
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF... |
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=... |
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Compiling module work.S_SYNCER_for__OUT_ |
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Compiling module work.S_CONTROLLER_SimpleSumeSwitch |
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Compiling module work.SimpleSumeSwitch |
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Compiling module work.TB_System_Stim |
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Compiling module work.Check |
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Compiling module work.SimpleSumeSwitch_tb |
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Compiling module work.glbl |
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Built simulation snapshot work.SimpleSumeSwitch_tb#work.glbl |
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****** Webtalk v2018.2 (64-bit) |
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**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 |
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**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 |
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. |
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source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/xsim_webtalk.tcl -notrace |
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INFO: [Common 17-186] '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Wed Jul 24 09:58:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2018.2/doc/webtalk_introduction.html. |
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INFO: [Common 17-206] Exiting Webtalk at Wed Jul 24 09:58:15 2019... |
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+ /opt/Xilinx/Vivado/2018.2/bin/xsim --runall SimpleSumeSwitch_tb#work.glbl |
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****** xsim v2018.2 (64-bit) |
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**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 |
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**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 |
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. |
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source xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsim_script.tcl |
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# xsim {work.SimpleSumeSwitch_tb#work.glbl} -autoloadwcfg -runall |
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Vivado Simulator 2018.2 |
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Time resolution is 1 ps |
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run -all |
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_268 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_268 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_268 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_268 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_268 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_lookup_table_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_lookup_table_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_973 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.t7gspp3x6gqqhxx7ddqyjl1spw_589.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/t7gspp3x6gqqhxx7ddqyjl1spw_589/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1066 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.ifd589vv1rbgrs5trh_530.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/ifd589vv1rbgrs5trh_530/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1096 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.b0sgt9rbwdy99m86c52emrwnd_1624.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/b0sgt9rbwdy99m86c52emrwnd_1624/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1160 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.xu2d9apgueuf9rdupwrca_210.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/xu2d9apgueuf9rdupwrca_210/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1244 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.rjn4vy1rvt56q857inwe4640580h_1961.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rjn4vy1rvt56q857inwe4640580h_1961/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1066 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.h63j5h0s3nodje3bf_981.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/h63j5h0s3nodje3bf_981/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1096 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.jmqfxvu7jawl2i3slwqw2y7ahkgelg_1378.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmqfxvu7jawl2i3slwqw2y7ahkgelg_1378/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1425 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.gts73br1vrbffbjckqe6cn6povy4hy9_269.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gts73br1vrbffbjckqe6cn6povy4hy9_269/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1509 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.soouj7es7vmbj65i9010w3_995.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/soouj7es7vmbj65i9010w3_995/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1593 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.kk76wl7rz8294oaojjb9j_1533.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/kk76wl7rz8294oaojjb9j_1533/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1160 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.pgc4mub6mtilf8dl7r5jl_930.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/pgc4mub6mtilf8dl7r5jl_930/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1244 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.sxelu3nl6i1q52nj7kjfc6snztzhkji5_1309.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/sxelu3nl6i1q52nj7kjfc6snztzhkji5_1309/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1845 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.wiihmz3j8xq83truxpy6se7xhm67iao_1930.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/wiihmz3j8xq83truxpy6se7xhm67iao_1930/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1066 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.mces7ojjuqyf7bak4vw9ebk4o942_999.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/mces7ojjuqyf7bak4vw9ebk4o942_999/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1096 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.pviqtlemileiqj228n6vg4isyh_1428.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/pviqtlemileiqj228n6vg4isyh_1428/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2032 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.lcwcvucgzv932dkker1xp5q1an_1321.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/lcwcvucgzv932dkker1xp5q1an_1321/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1593 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.v2xt2jjhjlb7za2ofd_1168.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/v2xt2jjhjlb7za2ofd_1168/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2200 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.lpl6esoj9xrvkcs50k4r89y30berzse_685.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/lpl6esoj9xrvkcs50k4r89y30berzse_685/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1425 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.wfgbajc7mgldhsivbsvkxq_231.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/wfgbajc7mgldhsivbsvkxq_231/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1160 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.tejguhrpuz1gmjgbogsk0nohq9pets6_2284.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/tejguhrpuz1gmjgbogsk0nohq9pets6_2284/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1509 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.gdty5dio6nrptna44_775.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/gdty5dio6nrptna44_775/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2536 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.gjjwq9d9j88f07jywhuv9m3nfrmy_1423.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/gjjwq9d9j88f07jywhuv9m3nfrmy_1423/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1244 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.af12qeuwfvotxgcgq18yjrd8_177.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/af12qeuwfvotxgcgq18yjrd8_177/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1845 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.x1w5ti5f8qwiksiercske7tjt7ajpjv_1132.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/x1w5ti5f8qwiksiercske7tjt7ajpjv_1132/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1066 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.ngx4xngq5vhq7ckg6hgee5kwp_1096.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/ngx4xngq5vhq7ckg6hgee5kwp_1096/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1096 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.kh8atwc4gciaor4l0_2613.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/kh8atwc4gciaor4l0_2613/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1425 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.n4f97l9t3uf6tpufaab35seppn65v5fy_1108.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/n4f97l9t3uf6tpufaab35seppn65v5fy_1108/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1509 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.ro923u0c5a6w13tv06pb4c7fwzag_1690.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/ro923u0c5a6w13tv06pb4c7fwzag_1690/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1593 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.qktvccnm3gxg97lslqdnbmkdj95ogx_423.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/qktvccnm3gxg97lslqdnbmkdj95ogx_423/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1160 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.f84hsmd6e0a0prjysz33btam6e9_2138.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/f84hsmd6e0a0prjysz33btam6e9_2138/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1244 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.v4u2pnf3jt3lyg03dw_652.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/v4u2pnf3jt3lyg03dw_652/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1845 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.r6oj26moczdfooyjr35n6a1co1_1041.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/r6oj26moczdfooyjr35n6a1co1_1041/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_3390 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.m1imds37xner98azdnu8eczum5ar726n_2566.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/m1imds37xner98azdnu8eczum5ar726n_2566/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1096 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.dsbz9jvodg2i5hztsj_897.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/dsbz9jvodg2i5hztsj_897/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1593 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.wnpxt0tfgi13p5lv_780.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0 |
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/wnpxt0tfgi13p5lv_780/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1160 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv |
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[SW] CAM_Init() - start |
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[SW] CAM_Init() - done |
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[SW] CAM_EnableDevice() - start |
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SV_write_control()- start |
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SV_write_control()- done |
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SV_read_control()- start |
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SV_read_control()- done |
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SV_write_control()- start |
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SV_write_control()- done |
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[SW] CAM_EnableDevice() - done |
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[2280754] INFO: finished packet stimulus file |
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[2735572] INFO: packet 1 tuple OK < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 > |
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[2735572] INFO: packet 1 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208) |
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[2738904] INFO: packet 1 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000) |
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[2745568] INFO: packet 2 tuple OK < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001040000 > |
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[2745568] INFO: packet 2 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208) |
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[2748900] INFO: packet 2 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000) |
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[2755564] INFO: packet 3 tuple OK < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001100000 > |
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[2755564] INFO: packet 3 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208) |
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[2758896] INFO: packet 3 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000) |
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[2765560] INFO: packet 4 tuple OK < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001400000 > |
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[2765560] INFO: packet 4 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208) |
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[2768892] INFO: packet 4 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000) |
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[6104224] INFO: stopping simulation after 1000 idle cycles |
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[6104224] INFO: all expected data successfully received |
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[6104224] INFO: TEST PASSED |
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$finish called at time : 6104224 ps : File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" Line 207 |
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exit |
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INFO: [Common 17-206] Exiting xsim at Wed Jul 24 09:58:25 2019... |
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+ grep ^expected /home/nico/master-thesis/netpfga/log/compile-2019-07-24-095730-subparser-5.6 |
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+ sed -e s/.*= <// -e s/.*= (// |
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+ expected_line= |
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+ grep ^actual /home/nico/master-thesis/netpfga/log/compile-2019-07-24-095730-subparser-5.6 |
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+ sed -e s/.*= <// -e s/.*= (// |
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+ actual_line= |
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+ [ != ] |
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+ date |
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Mit Jul 24 09:58:25 CEST 2019 |
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4 |
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+ make config_writes |
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata |
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+ date |
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Mit Jul 24 09:58:25 CEST 2019 |
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4 |
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+ make uninstall_sdnet |
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rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip |
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+ make install_sdnet |
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rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip |
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cp -r nf_sume_sdnet_ip /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/ |
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mkdir /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper |
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cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/hdl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper/ |
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cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/tcl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ |
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cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/Makefile /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ |
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make -C /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ |
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip' |
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rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip |
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vivado -mode batch -source nf_sume_sdnet.tcl |
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****** Vivado v2018.2 (64-bit) |
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**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 |
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**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 |
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. |
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source nf_sume_sdnet.tcl |
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# set design nf_sume_sdnet |
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# set top nf_sume_sdnet |
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# set device xc7vx690t-3-ffg1761 |
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# set proj_dir ./ip_proj |
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# set ip_version 1.00 |
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# set lib_name NetFPGA |
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# create_project -name ${design} -force -dir "./${proj_dir}" -part ${device} |
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# set_property source_mgmt_mode All [current_project] |
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# set_property top ${top} [current_fileset] |
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# set_property ip_repo_paths $::env(SUME_FOLDER)/lib/hw/ [current_fileset] |
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# update_ip_catalog |
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INFO: [IP_Flow 19-234] Refreshing IP repositories |
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INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'. |
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WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.) |
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'. |
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# puts "nf_sume_sdnet" |
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nf_sume_sdnet |
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# read_verilog "./wrapper/sume_to_sdnet.v" |
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# read_verilog "./wrapper/nf_sume_sdnet.v" |
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# read_verilog "./wrapper/changeEndian.v" |
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# add_files -scan_for_includes ./SimpleSumeSwitch/ |
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# import_files -force |
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INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1' |
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# update_compile_order -fileset sources_1 |
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# update_compile_order -fileset sim_1 |
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# ipx::package_project |
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WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'. |
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WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/wrapper/changeEndian.v'. |
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WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv'. |
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WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv'. |
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WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v'. |
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WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp'. |
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WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp'. |
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WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v'. |
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WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM_INST0.h'. |
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/dpi.h'. |
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v'. |
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM.h'. |
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv'. |
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp'. |
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.h'. |
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_lookup_table_tuple_in_request.vp'. |
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv'. |
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv'. |
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv'. |
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v'. |
|
INFO: [IP_Flow 19-5169] Module 'nf_sume_sdnet' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager. |
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INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). |
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). |
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). |
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). |
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). |
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). |
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). |
|
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. |
|
INFO: [IP_Flow 19-4728] Bus Interface 'axis_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. |
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INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'S_AXI'. |
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INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. |
|
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'S_AXI_ARESETN'. |
|
INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'axis_resetn'. |
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INFO: [IP_Flow 19-2181] Payment Required is not set for this core. |
|
INFO: [IP_Flow 19-2187] The Product Guide file is missing. |
|
# set_property name ${design} [ipx::current_core] |
|
# set_property library ${lib_name} [ipx::current_core] |
|
# set_property vendor_display_name {NetFPGA} [ipx::current_core] |
|
# set_property company_url {http://www.netfpga.org} [ipx::current_core] |
|
# set_property vendor {NetFPGA} [ipx::current_core] |
|
# set_property supported_families {{virtex7} {Production}} [ipx::current_core] |
|
# set_property taxonomy {{/NetFPGA/Generic}} [ipx::current_core] |
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# set_property version ${ip_version} [ipx::current_core] |
|
# set_property display_name ${design} [ipx::current_core] |
|
# set_property description ${design} [ipx::current_core] |
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# ipx::add_user_parameter {C_M_AXIS_DATA_WIDTH} [ipx::current_core] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property display_name {C_M_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value {256} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]] |
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# ipx::add_user_parameter {C_S_AXIS_DATA_WIDTH} [ipx::current_core] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property display_name {C_S_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value {256} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]] |
|
# ipx::add_user_parameter {C_M_AXIS_TUSER_WIDTH} [ipx::current_core] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property display_name {C_M_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value {128} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]] |
|
# ipx::add_user_parameter {C_S_AXIS_TUSER_WIDTH} [ipx::current_core] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property display_name {C_S_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value {128} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]] |
|
# ipx::add_user_parameter {C_S_AXI_DATA_WIDTH} [ipx::current_core] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property display_name {C_S_AXI_DATA_WIDTH} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value {32} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_format {long} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]] |
|
# ipx::add_user_parameter {C_S_AXI_ADDR_WIDTH} [ipx::current_core] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property display_name {C_S_AXI_ADDR_WIDTH} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value {12} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_format {long} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]] |
|
# ipx::add_user_parameter {SDNET_ADDR_WIDTH} [ipx::current_core] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_resolve_type {user} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property display_name {SDNET_ADDR_WIDTH} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value {11} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]] |
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead |
|
# set_property value_format {long} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]] |
|
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagesynthesis -of_objects [ipx::current_core]] |
|
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagebehavioralsimulation -of_objects [ipx::current_core]] |
|
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects [ipx::current_core]] |
|
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects [ipx::current_core]] |
|
# update_ip_catalog -rebuild |
|
INFO: [IP_Flow 19-234] Refreshing IP repositories |
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'. |
|
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.) |
|
# ipx::infer_user_parameters [ipx::current_core] |
|
# ipx::check_integrity [ipx::current_core] |
|
INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nf_sume_sdnet_v1_0.tcl" does not have the current IP <name>_v<version> format. If the IP name or version was changed recently, recreate this file to update the file format. |
|
INFO: [IP_Flow 19-2181] Payment Required is not set for this core. |
|
INFO: [IP_Flow 19-2187] The Product Guide file is missing. |
|
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. |
|
# ipx::save_core [ipx::current_core] |
|
# update_ip_catalog |
|
# close_project |
|
INFO: [Common 17-206] Exiting Vivado at Wed Jul 24 09:58:45 2019... |
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip' |
|
+ date |
|
Mit Jul 24 09:58:45 CEST 2019 |
|
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default |
|
+ make |
|
rm -f config_writes.py* |
|
rm -f *.pyc |
|
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py ./ |
|
+ date |
|
Mit Jul 24 09:58:45 CEST 2019 |
|
+ cd /home/nico/projects/P4-NetFPGA |
|
+ ./tools/scripts/nf_test.py sim --major switch --minor default |
|
make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test' |
|
vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_defines.tcl |
|
|
|
****** Vivado v2018.2 (64-bit) |
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 |
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 |
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. |
|
|
|
source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_defines.tcl |
|
# set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
# set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
# set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
# set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
# set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
# set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
# set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
# set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
# set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
# set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
# set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
# set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
# set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
# set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
# set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
# set M00_BASEADDR 0x44000000 |
|
# set M00_HIGHADDR 0x44000FFF |
|
# set M00_SIZEADDR 0x1000 |
|
# set M01_BASEADDR 0x44010000 |
|
# set M01_HIGHADDR 0x44010FFF |
|
# set M01_SIZEADDR 0x1000 |
|
# set M02_BASEADDR 0x44020000 |
|
# set M02_HIGHADDR 0x44020FFF |
|
# set M02_SIZEADDR 0x1000 |
|
# set M03_BASEADDR 0x44030000 |
|
# set M03_HIGHADDR 0x44030FFF |
|
# set M03_SIZEADDR 0x1000 |
|
# set M04_BASEADDR 0x44040000 |
|
# set M04_HIGHADDR 0x44040FFF |
|
# set M04_SIZEADDR 0x1000 |
|
# set M05_BASEADDR 0x44050000 |
|
# set M05_HIGHADDR 0x44050FFF |
|
# set M05_SIZEADDR 0x1000 |
|
# set M06_BASEADDR 0x44060000 |
|
# set M06_HIGHADDR 0x44060FFF |
|
# set M06_SIZEADDR 0x1000 |
|
# set M07_BASEADDR 0x44070000 |
|
# set M07_HIGHADDR 0x44070FFF |
|
# set M07_SIZEADDR 0x1000 |
|
# set M08_BASEADDR 0x44080000 |
|
# set M08_HIGHADDR 0x44080FFF |
|
# set M08_SIZEADDR 0x1000 |
|
# set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
# set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
# set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
# set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
# set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
# set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
# set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
# set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
# set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
# set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
# set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
# set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
# set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
# set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
# set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
# set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
# set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
# set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
# set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
# set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
# set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
# set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
# set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
# set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
# set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
# set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
# set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
INFO: [Common 17-206] Exiting Vivado at Wed Jul 24 09:58:52 2019... |
|
vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/export_registers.tcl |
|
|
|
****** Vivado v2018.2 (64-bit) |
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 |
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 |
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. |
|
|
|
source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/export_registers.tcl |
|
# set DEF_LIST { |
|
# {MICROBLAZE_AXI_IIC 0 0 ""} \ |
|
# {MICROBLAZE_UARTLITE 0 0 ""} \ |
|
# {MICROBLAZE_DLMB_BRAM 0 0 ""} \ |
|
# {MICROBLAZE_ILMB_BRAM 0 0 ""} \ |
|
# {MICROBLAZE_AXI_INTC 0 0 ""} \ |
|
# {INPUT_ARBITER 0 1 input_arbiter_v1_0_0/data/input_arbiter_regs_defines.txt} \ |
|
# {OUTPUT_QUEUES 0 1 output_queues_v1_0_0/data/output_queues_regs_defines.txt} \ |
|
# {OUTPUT_PORT_LOOKUP 0 1 switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.txt} \ |
|
# {NF_10G_INTERFACE0 0 1 nf_10ge_interface_shared_v1_0_0/data/nf_10g_interface_shared_regs_defines.txt} \ |
|
# {NF_10G_INTERFACE1 1 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ |
|
# {NF_10G_INTERFACE2 2 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ |
|
# {NF_10G_INTERFACE3 3 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ |
|
# {NF_RIFFA_DMA 0 1 nf_riffa_dma_v1_0_0/data/nf_riffa_dma_regs_defines.txt} \ |
|
# |
|
# |
|
# } |
|
# set target_path $::env(NF_DESIGN_DIR)/sw/embedded/src/ |
|
# set target_file $target_path/sume_register_defines.h |
|
# proc write_header { target_file } { |
|
# |
|
# # creat a blank header file |
|
# # do a fresh rewrite in case the file already exits |
|
# file delete -force $target_file |
|
# open $target_file "w" |
|
# set h_file [open $target_file "w"] |
|
# |
|
# |
|
# puts $h_file "//-" |
|
# puts $h_file "// Copyright (c) 2015 University of Cambridge" |
|
# puts $h_file "// All rights reserved." |
|
# puts $h_file "//" |
|
# puts $h_file "// This software was developed by Stanford University and the University of Cambridge Computer Laboratory " |
|
# puts $h_file "// under National Science Foundation under Grant No. CNS-0855268," |
|
# puts $h_file "// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and" |
|
# puts $h_file "// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 (\"MRC2\"), " |
|
# puts $h_file "// as part of the DARPA MRC research programme." |
|
# puts $h_file "//" |
|
# puts $h_file "// @NETFPGA_LICENSE_HEADER_START@" |
|
# puts $h_file "//" |
|
# puts $h_file "// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor" |
|
# puts $h_file "// license agreements. See the NOTICE file distributed with this work for" |
|
# puts $h_file "// additional information regarding copyright ownership. NetFPGA licenses this" |
|
# puts $h_file "// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the" |
|
# puts $h_file "// \"License\"); you may not use this file except in compliance with the" |
|
# puts $h_file "// License. You may obtain a copy of the License at:" |
|
# puts $h_file "//" |
|
# puts $h_file "// http://www.netfpga-cic.org" |
|
# puts $h_file "//" |
|
# puts $h_file "// Unless required by applicable law or agreed to in writing, Work distributed" |
|
# puts $h_file "// under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR" |
|
# puts $h_file "// CONDITIONS OF ANY KIND, either express or implied. See the License for the" |
|
# puts $h_file "// specific language governing permissions and limitations under the License." |
|
# puts $h_file "//" |
|
# puts $h_file "// @NETFPGA_LICENSE_HEADER_END@" |
|
# puts $h_file "/////////////////////////////////////////////////////////////////////////////////" |
|
# puts $h_file "// This is an automatically generated header definitions file" |
|
# puts $h_file "/////////////////////////////////////////////////////////////////////////////////" |
|
# puts $h_file "" |
|
# |
|
# close $h_file |
|
# |
|
# }; |
|
# proc write_core {target_file prefix id has_registers lib_name} { |
|
# |
|
# |
|
# set h_file [open $target_file "a"] |
|
# |
|
# #First, read the memory map information from the reference_project defines file |
|
# source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl |
|
# set public_repo_dir $::env(SUME_FOLDER)/lib/hw/ |
|
# |
|
# |
|
# set baseaddr [set $prefix\_BASEADDR] |
|
# set highaddr [set $prefix\_HIGHADDR] |
|
# set sizeaddr [set $prefix\_SIZEADDR] |
|
# |
|
# puts $h_file "//######################################################" |
|
# puts $h_file "//# Definitions for $prefix" |
|
# puts $h_file "//######################################################" |
|
# |
|
# puts $h_file "#define SUME_$prefix\_BASEADDR $baseaddr" |
|
# puts $h_file "#define SUME_$prefix\_HIGHADDR $highaddr" |
|
# puts $h_file "#define SUME_$prefix\_SIZEADDR $sizeaddr" |
|
# puts $h_file "" |
|
# |
|
# #Second, read the registers information from the library defines file |
|
# if $has_registers { |
|
# set lib_path "$public_repo_dir/std/cores/$lib_name" |
|
# set regs_h_define_file $lib_path |
|
# set regs_h_define_file_read [open $regs_h_define_file r] |
|
# set regs_h_define_file_data [read $regs_h_define_file_read] |
|
# close $regs_h_define_file_read |
|
# set regs_h_define_file_data_line [split $regs_h_define_file_data "\n"] |
|
# |
|
# foreach read_line $regs_h_define_file_data_line { |
|
# if {[regexp "#define" $read_line]} { |
|
# puts $h_file "#define SUME_[lindex $read_line 2]\_$id\_[lindex $read_line 3]\_[lindex $read_line 4] [lindex $read_line 5]" |
|
# } |
|
# } |
|
# } |
|
# puts $h_file "" |
|
# close $h_file |
|
# }; |
|
# write_header $target_file |
|
# foreach lib_item $DEF_LIST { |
|
# write_core $target_file [lindex $lib_item 0] [lindex $lib_item 1] [lindex $lib_item 2] [lindex $lib_item 3] |
|
# } |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
INFO: [Common 17-206] Exiting Vivado at Wed Jul 24 09:58:59 2019... |
|
cd ../sw/embedded/src && cp /home/nico/projects/P4-NetFPGA/tools/scripts/xparam2regdefines.py . && python xparam2regdefines.py |
|
cd ../sw/embedded/src && rm -f xparam2regdefines.py && mv reg_defines.h ../ |
|
cd ../sw/embedded && cp /home/nico/projects/P4-NetFPGA/tools/scripts/python_parser.py . && python python_parser.py |
|
cd ../sw/embedded && rm -f python_parser.py && mv reg_defines.py ../../test/reg_defines_simple_sume_switch.py |
|
make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test' |
|
make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test' |
|
rm -rf proj_* vivado*.* *.*~ .Xil* /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/ |
|
rm -rf *[0-9]_{stim,expected,log}.axi |
|
rm -f *.axi |
|
rm -f portconfig.sim |
|
rm -f seed |
|
rm -f *.log |
|
rm -f ../test/Makefile |
|
rm -rf ../test/*.log |
|
rm -rf ../test/*.axi |
|
rm -rf ../test/seed |
|
rm -rf ../test/*.sim |
|
rm -rf ../test/proj_* |
|
rm -rf ../test/ip_repo |
|
rm -f ../test/vivado*.* |
|
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.py |
|
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.pyc |
|
rm -f ../hw/create_ip/id_rom16x32.coe |
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh |
|
echo 16028002 >> rom_data.txt |
|
echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt |
|
grep: ../../../RELEASE_NOTES: No such file or directory |
|
echo 00000204 >> rom_data.txt |
|
echo 0000FFFF >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py |
|
16 |
|
|
|
mv -f id_rom16x32.coe ../hw/create_ip/ |
|
mv -f rom_data.txt ../hw/create_ip/ |
|
cp -f /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_defines_simple_sume_switch.py /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/reg_defines_simple_sume_switch.py |
|
vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl -tclargs sim_switch_default |
|
|
|
****** Vivado v2018.2 (64-bit) |
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 |
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 |
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. |
|
|
|
source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl |
|
# set design $::env(NF_PROJECT_NAME) |
|
# set top top_sim |
|
# set sim_top top_tb |
|
# set device xc7vx690t-3-ffg1761 |
|
# set proj_dir ./project |
|
# set public_repo_dir $::env(SUME_FOLDER)/lib/hw/ |
|
# set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/ |
|
# set repo_dir ./ip_repo |
|
# set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc |
|
# set project_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_general.xdc |
|
# set nf_10g_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_10g.xdc |
|
# set test_name [lindex $argv 0] |
|
# source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
# create_project -name ${design} -force -dir "$::env(NF_DESIGN_DIR)/hw/${proj_dir}" -part ${device} |
|
# set_property source_mgmt_mode DisplayOnly [current_project] |
|
# set_property top ${top} [current_fileset] |
|
# puts "Creating User Datapath reference project" |
|
Creating User Datapath reference project |
|
# create_fileset -constrset -quiet constraints |
|
# file copy ${public_repo_dir}/ ${repo_dir} |
|
# set_property ip_repo_paths ${repo_dir} [current_fileset] |
|
# add_files -fileset constraints -norecurse ${bit_settings} |
|
# add_files -fileset constraints -norecurse ${project_constraints} |
|
# add_files -fileset constraints -norecurse ${nf_10g_constraints} |
|
# set_property is_enabled true [get_files ${project_constraints}] |
|
# set_property is_enabled true [get_files ${bit_settings}] |
|
# set_property is_enabled true [get_files ${project_constraints}] |
|
# update_ip_catalog |
|
INFO: [IP_Flow 19-234] Refreshing IP repositories |
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/ip_repo'. |
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'. |
|
# create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip |
|
# set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci] |
|
# reset_target all [get_ips nf_sume_sdnet_ip] |
|
# generate_target all [get_ips nf_sume_sdnet_ip] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_sume_sdnet_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_sume_sdnet_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_sume_sdnet_ip'... |
|
# create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip |
|
# set_property -dict [list CONFIG.C_BASEADDR $INPUT_ARBITER_BASEADDR] [get_ips input_arbiter_ip] |
|
# set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci] |
|
# reset_target all [get_ips input_arbiter_ip] |
|
# generate_target all [get_ips input_arbiter_ip] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'input_arbiter_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'input_arbiter_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'input_arbiter_ip'... |
|
# create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip |
|
# set_property -dict [list CONFIG.C_BASEADDR $OUTPUT_QUEUES_BASEADDR] [get_ips sss_output_queues_ip] |
|
# set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci] |
|
# reset_target all [get_ips sss_output_queues_ip] |
|
# generate_target all [get_ips sss_output_queues_ip] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'sss_output_queues_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'sss_output_queues_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'sss_output_queues_ip'... |
|
# create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip |
|
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3 |
|
create_ip: Time (s): cpu = 00:00:22 ; elapsed = 00:01:00 . Memory (MB): peak = 1696.844 ; gain = 390.395 ; free physical = 2404 ; free virtual = 28668 |
|
# set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {1024} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip] |
|
# set_property generate_synth_checkpoint false [get_files identifier_ip.xci] |
|
# reset_target all [get_ips identifier_ip] |
|
# generate_target all [get_ips identifier_ip] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'identifier_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'identifier_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'identifier_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'identifier_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'identifier_ip'... |
|
# create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip |
|
# set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip] |
|
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '5.000' to '5.0' has been ignored for IP 'clk_wiz_ip' |
|
# set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci] |
|
# reset_target all [get_ips clk_wiz_ip] |
|
# generate_target all [get_ips clk_wiz_ip] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz_ip'... |
|
# create_ip -name barrier -vendor NetFPGA -library NetFPGA -module_name barrier_ip |
|
# reset_target all [get_ips barrier_ip] |
|
# generate_target all [get_ips barrier_ip] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'barrier_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'barrier_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'barrier_ip'... |
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip0 |
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_0_log.axi] [get_ips axis_sim_record_ip0] |
|
# reset_target all [get_ips axis_sim_record_ip0] |
|
# generate_target all [get_ips axis_sim_record_ip0] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip0'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip0'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip0'... |
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip1 |
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_1_log.axi] [get_ips axis_sim_record_ip1] |
|
# reset_target all [get_ips axis_sim_record_ip1] |
|
# generate_target all [get_ips axis_sim_record_ip1] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip1'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip1'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip1'... |
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip2 |
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_2_log.axi] [get_ips axis_sim_record_ip2] |
|
# reset_target all [get_ips axis_sim_record_ip2] |
|
# generate_target all [get_ips axis_sim_record_ip2] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip2'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip2'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip2'... |
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip3 |
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_3_log.axi] [get_ips axis_sim_record_ip3] |
|
# reset_target all [get_ips axis_sim_record_ip3] |
|
# generate_target all [get_ips axis_sim_record_ip3] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip3'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip3'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip3'... |
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip4 |
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/dma_0_log.axi] [get_ips axis_sim_record_ip4] |
|
# reset_target all [get_ips axis_sim_record_ip4] |
|
# generate_target all [get_ips axis_sim_record_ip4] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip4'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip4'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip4'... |
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip0 |
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_0_stim.axi] [get_ips axis_sim_stim_ip0] |
|
# generate_target all [get_ips axis_sim_stim_ip0] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip0'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip0'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip0'... |
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip1 |
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_1_stim.axi] [get_ips axis_sim_stim_ip1] |
|
# generate_target all [get_ips axis_sim_stim_ip1] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip1'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip1'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip1'... |
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip2 |
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_2_stim.axi] [get_ips axis_sim_stim_ip2] |
|
# generate_target all [get_ips axis_sim_stim_ip2] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip2'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip2'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip2'... |
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip3 |
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_3_stim.axi] [get_ips axis_sim_stim_ip3] |
|
# generate_target all [get_ips axis_sim_stim_ip3] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip3'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip3'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip3'... |
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip4 |
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/dma_0_stim.axi] [get_ips axis_sim_stim_ip4] |
|
# generate_target all [get_ips axis_sim_stim_ip4] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip4'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip4'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip4'... |
|
# create_ip -name axi_sim_transactor -vendor NetFPGA -library NetFPGA -module_name axi_sim_transactor_ip |
|
# set_property -dict [list CONFIG.STIM_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.axi CONFIG.EXPECT_FILE $::env(NF_DESIGN_DIR)/test/reg_expect.axi CONFIG.LOG_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.log] [get_ips axi_sim_transactor_ip] |
|
# reset_target all [get_ips axi_sim_transactor_ip] |
|
# generate_target all [get_ips axi_sim_transactor_ip] |
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_sim_transactor_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_sim_transactor_ip'... |
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_sim_transactor_ip'... |
|
# update_ip_catalog |
|
# source $::env(NF_DESIGN_DIR)/hw/tcl/control_sub_sim.tcl |
|
## set scripts_vivado_version 2018.2 |
|
## set current_vivado_version [version -short] |
|
## if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { |
|
## puts "" |
|
## puts "ERROR: This script was created for Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script." |
|
## |
|
## return 1 |
|
## } |
|
## set design_name control_sub |
|
## if { [get_projects -quiet] eq "" } { |
|
## puts "ERROR: Please open or create a project!" |
|
## return 1 |
|
## } |
|
## set errMsg "" |
|
## set nRet 0 |
|
## set cur_design [current_bd_design -quiet] |
|
## set list_cells [get_bd_cells -quiet] |
|
## if { ${design_name} eq "" } { |
|
## # USE CASES: |
|
## # 1) Design_name not set |
|
## |
|
## set errMsg "ERROR: Please set the variable <design_name> to a non-empty value." |
|
## set nRet 1 |
|
## |
|
## } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { |
|
## # USE CASES: |
|
## # 2): Current design opened AND is empty AND names same. |
|
## # 3): Current design opened AND is empty AND names diff; design_name NOT in project. |
|
## # 4): Current design opened AND is empty AND names diff; design_name exists in project. |
|
## |
|
## if { $cur_design ne $design_name } { |
|
## puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty." |
|
## set design_name [get_property NAME $cur_design] |
|
## } |
|
## puts "INFO: Constructing design in IPI design <$cur_design>..." |
|
## |
|
## } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { |
|
## # USE CASES: |
|
## # 5) Current design opened AND has components AND same names. |
|
## |
|
## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value." |
|
## set nRet 1 |
|
## } elseif { [get_files -quiet ${design_name}.bd] ne "" } { |
|
## # USE CASES: |
|
## # 6) Current opened design, has components, but diff names, design_name exists in project. |
|
## # 7) No opened design, design_name exists in project. |
|
## |
|
## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value." |
|
## set nRet 2 |
|
## |
|
## } else { |
|
## # USE CASES: |
|
## # 8) No opened design, design_name not in project. |
|
## # 9) Current opened design, has components, but diff names, design_name not in project. |
|
## |
|
## puts "INFO: Currently there is no design <$design_name> in project, so creating one..." |
|
## |
|
## create_bd_design $design_name |
|
## |
|
## puts "INFO: Making design <$design_name> as current_bd_design." |
|
## current_bd_design $design_name |
|
## |
|
## } |
|
INFO: Currently there is no design <control_sub> in project, so creating one... |
|
Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd> |
|
INFO: Making design <control_sub> as current_bd_design. |
|
## puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"." |
|
INFO: Currently the variable <design_name> is equal to "control_sub". |
|
## if { $nRet != 0 } { |
|
## puts $errMsg |
|
## return $nRet |
|
## } |
|
## proc create_root_design { parentCell } { |
|
## |
|
## if { $parentCell eq "" } { |
|
## set parentCell [get_bd_cells /] |
|
## } |
|
## |
|
## # Get object for parentCell |
|
## set parentObj [get_bd_cells $parentCell] |
|
## if { $parentObj == "" } { |
|
## puts "ERROR: Unable to find parent cell <$parentCell>!" |
|
## return |
|
## } |
|
## |
|
## # Make sure parentObj is hier blk |
|
## set parentType [get_property TYPE $parentObj] |
|
## if { $parentType ne "hier" } { |
|
## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>." |
|
## return |
|
## } |
|
## |
|
## # Save current instance; Restore later |
|
## set oldCurInst [current_bd_instance .] |
|
## |
|
## # Set parent object as current |
|
## current_bd_instance $parentObj |
|
## |
|
## |
|
## # Create interface ports |
|
## set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ] |
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M00_AXI |
|
## set M01_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ] |
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## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M01_AXI |
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## set M02_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ] |
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## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M02_AXI |
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## set M03_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI ] |
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## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M03_AXI |
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## set M04_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI ] |
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## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M04_AXI |
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## set M05_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI ] |
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## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M05_AXI |
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## set M06_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI ] |
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## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M06_AXI |
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## set M07_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI ] |
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## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M07_AXI |
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## set S00_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI ] |
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## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.ARUSER_WIDTH {0} CONFIG.AWUSER_WIDTH {0} CONFIG.BUSER_WIDTH {0} CONFIG.CLK_DOMAIN {} CONFIG.DATA_WIDTH {32} CONFIG.FREQ_HZ {100000000} CONFIG.ID_WIDTH {0} CONFIG.MAX_BURST_LENGTH {256} CONFIG.NUM_READ_OUTSTANDING {2} CONFIG.NUM_WRITE_OUTSTANDING {2} CONFIG.PHASE {0.000} CONFIG.PROTOCOL {AXI4} CONFIG.READ_WRITE_MODE {READ_WRITE} CONFIG.RUSER_WIDTH {0} CONFIG.SUPPORTS_NARROW_BURST {1} CONFIG.WUSER_WIDTH {0} ] $S00_AXI |
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## |
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## # Create ports |
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## set axi_lite_aclk [ create_bd_port -dir I -type clk axi_lite_aclk ] |
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## set axi_lite_areset [ create_bd_port -dir I -type rst axi_lite_areset ] |
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## set core_clk [ create_bd_port -dir I -type clk core_clk ] |
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## set_property -dict [ list CONFIG.FREQ_HZ {200000000} ] $core_clk |
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## set core_resetn [ create_bd_port -dir I -type rst core_resetn ] |
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## |
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## |
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## |
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## |
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## # Create instance: axi_interconnect_0, and set properties |
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## set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] |
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## set_property -dict [ list CONFIG.NUM_MI {8} CONFIG.TRANSLATION_MODE {0} ] $axi_interconnect_0 |
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## set_property -dict [list CONFIG.M00_HAS_REGSLICE {3} CONFIG.M00_HAS_DATA_FIFO {1} ] $axi_interconnect_0 |
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## set_property -dict [list CONFIG.M01_HAS_REGSLICE {3} CONFIG.M01_HAS_DATA_FIFO {1} ] $axi_interconnect_0 |
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## set_property -dict [list CONFIG.M02_HAS_REGSLICE {3} CONFIG.M02_HAS_DATA_FIFO {1} ] $axi_interconnect_0 |
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## set_property -dict [list CONFIG.M03_HAS_REGSLICE {3} CONFIG.M03_HAS_DATA_FIFO {1} ] $axi_interconnect_0 |
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## set_property -dict [list CONFIG.M04_HAS_REGSLICE {3} CONFIG.M04_HAS_DATA_FIFO {1} ] $axi_interconnect_0 |
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## set_property -dict [list CONFIG.M05_HAS_REGSLICE {3} CONFIG.M05_HAS_DATA_FIFO {1} ] $axi_interconnect_0 |
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## set_property -dict [list CONFIG.M06_HAS_REGSLICE {3} CONFIG.M06_HAS_DATA_FIFO {1} ] $axi_interconnect_0 |
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## set_property -dict [list CONFIG.M07_HAS_REGSLICE {3} CONFIG.M07_HAS_DATA_FIFO {1} ] $axi_interconnect_0 |
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## set_property -dict [list CONFIG.S00_HAS_REGSLICE {3} CONFIG.S00_HAS_DATA_FIFO {1} ] $axi_interconnect_0 |
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## |
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## |
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## # Add AXI clock converter |
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## create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 |
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## connect_bd_intf_net [get_bd_intf_ports S00_AXI] [get_bd_intf_pins axi_clock_converter_0/S_AXI] |
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## connect_bd_intf_net [get_bd_intf_pins axi_clock_converter_0/M_AXI] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S00_AXI] |
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## |
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## # Create interface connections |
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## connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI] |
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## connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports M01_AXI] [get_bd_intf_pins axi_interconnect_0/M01_AXI] |
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## connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports M02_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI] |
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## connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports M03_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI] |
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## connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports M04_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI] |
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## connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_ports M05_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI] |
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## connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_ports M06_AXI] [get_bd_intf_pins axi_interconnect_0/M06_AXI] |
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## connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_ports M07_AXI] [get_bd_intf_pins axi_interconnect_0/M07_AXI] |
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## |
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## # Create port connections |
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## connect_bd_net -net axi_lite_aclk_1 [get_bd_ports axi_lite_aclk] [get_bd_pins axi_clock_converter_0/s_axi_aclk] |
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## connect_bd_net -net core_clk_1 [get_bd_ports core_clk] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] |
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## connect_bd_net -net axi_lite_areset_1 [get_bd_ports axi_lite_areset] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] |
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## connect_bd_net -net core_resetn_1 [get_bd_ports core_resetn] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] |
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## |
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## # Create address segments |
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## source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl |
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## assign_bd_address [get_bd_addr_segs {M00_AXI/Reg }] |
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## set_property offset $M00_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}] |
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## set_property range $M00_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}] |
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## |
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## assign_bd_address [get_bd_addr_segs {M01_AXI/Reg }] |
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## set_property offset $M01_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}] |
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## set_property range $M01_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}] |
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## |
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## |
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## assign_bd_address [get_bd_addr_segs {M02_AXI/Reg }] |
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## set_property offset $M02_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}] |
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## set_property range $M02_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}] |
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## |
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## assign_bd_address [get_bd_addr_segs {M03_AXI/Reg }] |
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## set_property offset $M03_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}] |
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## set_property range $M03_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}] |
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## |
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## |
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## # Restore current instance |
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## current_bd_instance $oldCurInst |
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## |
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## save_bd_design |
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## } |
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## create_root_design "" |
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CRITICAL WARNING: [BD 41-737] Cannot set the parameter TRANSLATION_MODE on /axi_interconnect_0. It is read-only. |
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### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
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### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
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### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
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### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
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### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
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### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
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### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
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### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
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### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
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### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
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### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
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### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
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### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
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### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
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### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
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### set M00_BASEADDR 0x44000000 |
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### set M00_HIGHADDR 0x44000FFF |
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### set M00_SIZEADDR 0x1000 |
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### set M01_BASEADDR 0x44010000 |
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### set M01_HIGHADDR 0x44010FFF |
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### set M01_SIZEADDR 0x1000 |
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### set M02_BASEADDR 0x44020000 |
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### set M02_HIGHADDR 0x44020FFF |
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### set M02_SIZEADDR 0x1000 |
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### set M03_BASEADDR 0x44030000 |
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### set M03_HIGHADDR 0x44030FFF |
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### set M03_SIZEADDR 0x1000 |
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### set M04_BASEADDR 0x44040000 |
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### set M04_HIGHADDR 0x44040FFF |
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### set M04_SIZEADDR 0x1000 |
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### set M05_BASEADDR 0x44050000 |
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### set M05_HIGHADDR 0x44050FFF |
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### set M05_SIZEADDR 0x1000 |
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### set M06_BASEADDR 0x44060000 |
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### set M06_HIGHADDR 0x44060FFF |
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### set M06_SIZEADDR 0x1000 |
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### set M07_BASEADDR 0x44070000 |
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### set M07_HIGHADDR 0x44070FFF |
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### set M07_SIZEADDR 0x1000 |
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### set M08_BASEADDR 0x44080000 |
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### set M08_HIGHADDR 0x44080FFF |
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### set M08_SIZEADDR 0x1000 |
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### set IDENTIFIER_BASEADDR $M00_BASEADDR |
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### set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
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### set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
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### set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
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### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
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### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
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### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
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### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
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### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
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### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
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### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
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### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
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### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
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### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
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### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
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### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
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### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
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### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
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### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
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### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
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### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
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### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
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### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
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### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
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### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
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### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
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### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
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</M00_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]> |
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</M01_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]> |
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</M02_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]> |
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</M03_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]> |
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Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd> |
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# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/axi_clocking.v" |
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# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/nf_datapath.v" |
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# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_sim.v" |
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# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_tb.v" |
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# update_compile_order -fileset sources_1 |
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# update_compile_order -fileset sim_1 |
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# set_property top ${sim_top} [get_filesets sim_1] |
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# set_property include_dirs ${proj_dir} [get_filesets sim_1] |
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# set_property simulator_language Mixed [current_project] |
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# set_property verilog_define { {SIMULATION=1} } [get_filesets sim_1] |
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# set_property -name xsim.more_options -value {-testplusarg TESTNAME=basic_test} -objects [get_filesets sim_1] |
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# set_property runtime {} [get_filesets sim_1] |
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# set_property target_simulator xsim [current_project] |
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# set_property compxlib.xsim_compiled_library_dir {} [current_project] |
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# set_property top_lib xil_defaultlib [get_filesets sim_1] |
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# update_compile_order -fileset sim_1 |
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update_compile_order: Time (s): cpu = 00:00:20 ; elapsed = 00:00:08 . Memory (MB): peak = 2035.992 ; gain = 8.004 ; free physical = 2271 ; free virtual = 28557 |
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loading libsume.. |
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Traceback (most recent call last): |
|
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py", line 42, in <module> |
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import config_writes |
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File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py", line 7 |
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|
|
^ |
|
IndentationError: expected an indented block |
|
while executing |
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"exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py" |
|
invoked from within |
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"set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]" |
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(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 177) |
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INFO: [Common 17-206] Exiting Vivado at Wed Jul 24 10:00:28 2019... |
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Makefile:120: recipe for target 'sim' failed |
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make: *** [sim] Error 1 |
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make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test' |
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory |
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_stim.axi': No such file or directory |
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_expected.axi': No such file or directory |
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory |
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_stim.axi': No such file or directory |
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_expected.axi': No such file or directory |
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory |
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_stim.axi': No such file or directory |
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_expected.axi': No such file or directory |
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory |
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_stim.axi': No such file or directory |
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_expected.axi': No such file or directory |
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory |
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_expected.axi': No such file or directory |
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.log': No such file or directory |
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_expect.axi': No such file or directory |
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.axi': No such file or directory |
|
NetFPGA environment: |
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Root dir: /home/nico/projects/P4-NetFPGA |
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Project name: simple_sume_switch |
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Project dir: /tmp/nico/test/simple_sume_switch |
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Work dir: /tmp/nico |
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512 |
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=== Work directory is /tmp/nico/test/simple_sume_switch |
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=== Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default |
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=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim'] |
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+ date |
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Mit Jul 24 10:00:28 CEST 2019 |
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+ [ = no ] |
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch |
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+ make |
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make -C hw distclean |
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw' |
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rm -rf proj_* vivado*.* *.*~ .Xil* /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/ |
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rm -rf *[0-9]_{stim,expected,log}.axi |
|
rm -f *.axi |
|
rm -f portconfig.sim |
|
rm -f seed |
|
rm -f *.log |
|
rm -f ../test/Makefile |
|
rm -rf ../test/*.log |
|
rm -rf ../test/*.axi |
|
rm -rf ../test/seed |
|
rm -rf ../test/*.sim |
|
rm -rf ../test/proj_* |
|
rm -rf ../test/ip_repo |
|
rm -f ../test/vivado*.* |
|
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.py |
|
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.pyc |
|
rm -rfv project;\ |
|
rm -rfv ../sw/embedded/project;\ |
|
rm -rfv vivado*;\ |
|
rm -rfv *.log;\ |
|
rm -rfv .Xil;\ |
|
rm -rfv ..rej;\ |
|
rm -rfv .srcs;\ |
|
rm -rfv webtalk*;\ |
|
rm -rfv *.*~;\ |
|
rm -rfv ip_repo;\ |
|
rm -rfv ip_proj;\ |
|
rm -rfv std;\ |
|
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw' |
|
make -C sw/embedded/ distclean |
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded' |
|
rm -rf `find . -name "SDK_Workspace"` |
|
rm -rf `find . -name "*.log"` |
|
rm -rf `find . -name "*.jou"` |
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded' |
|
rm -rfv vivado*;\ |
|
|
|
make -C hw project |
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw' |
|
rm -f ../hw/create_ip/id_rom16x32.coe |
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh |
|
echo 16028002 >> rom_data.txt |
|
echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt |
|
grep: ../../../RELEASE_NOTES: No such file or directory |
|
echo 00000204 >> rom_data.txt |
|
echo 0000FFFF >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
echo FFFF0000 >> rom_data.txt |
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py |
|
16 |
|
|
|
mv -f id_rom16x32.coe ../hw/create_ip/ |
|
mv -f rom_data.txt ../hw/create_ip/ |
|
echo "Create reference project under folder /project";\ |
|
if test -d project/; then\ |
|
echo "Project already exists"; \ |
|
else \ |
|
vivado -mode batch -source tcl/simple_sume_switch.tcl;\ |
|
if [ -f patch/simple_sume_switch.patch ]; then\ |
|
patch -p1 < patch/simple_sume_switch.patch;\ |
|
fi;\ |
|
fi;\ |
|
|
|
Create reference project under folder /project |
|
|
|
****** Vivado v2018.2 (64-bit) |
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 |
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 |
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. |
|
|
|
source tcl/simple_sume_switch.tcl |
|
# set design $::env(NF_PROJECT_NAME) |
|
# set top top |
|
# set device xc7vx690t-3-ffg1761 |
|
# set proj_dir ./project |
|
# set public_repo_dir $::env(SUME_FOLDER)/lib/hw/ |
|
# set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/ |
|
# set repo_dir ./ip_repo |
|
# set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc |
|
# set project_constraints ./constraints/nf_sume_general.xdc |
|
# set nf_10g_constraints ./constraints/nf_sume_10g.xdc |
|
# source ./tcl/$::env(NF_PROJECT_NAME)_defines.tcl |
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
## set M00_BASEADDR 0x44000000 |
|
## set M00_HIGHADDR 0x44000FFF |
|
## set M00_SIZEADDR 0x1000 |
|
## set M01_BASEADDR 0x44010000 |
|
## set M01_HIGHADDR 0x44010FFF |
|
## set M01_SIZEADDR 0x1000 |
|
## set M02_BASEADDR 0x44020000 |
|
## set M02_HIGHADDR 0x44020FFF |
|
## set M02_SIZEADDR 0x1000 |
|
## set M03_BASEADDR 0x44030000 |
|
## set M03_HIGHADDR 0x44030FFF |
|
## set M03_SIZEADDR 0x1000 |
|
## set M04_BASEADDR 0x44040000 |
|
## set M04_HIGHADDR 0x44040FFF |
|
## set M04_SIZEADDR 0x1000 |
|
## set M05_BASEADDR 0x44050000 |
|
## set M05_HIGHADDR 0x44050FFF |
|
## set M05_SIZEADDR 0x1000 |
|
## set M06_BASEADDR 0x44060000 |
|
## set M06_HIGHADDR 0x44060FFF |
|
## set M06_SIZEADDR 0x1000 |
|
## set M07_BASEADDR 0x44070000 |
|
## set M07_HIGHADDR 0x44070FFF |
|
## set M07_SIZEADDR 0x1000 |
|
## set M08_BASEADDR 0x44080000 |
|
## set M08_HIGHADDR 0x44080FFF |
|
## set M08_SIZEADDR 0x1000 |
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
# source ./tcl/export_registers.tcl |
|
## set DEF_LIST { |
|
## {MICROBLAZE_AXI_IIC 0 0 ""} \ |
|
## {MICROBLAZE_UARTLITE 0 0 ""} \ |
|
## {MICROBLAZE_DLMB_BRAM 0 0 ""} \ |
|
## {MICROBLAZE_ILMB_BRAM 0 0 ""} \ |
|
## {MICROBLAZE_AXI_INTC 0 0 ""} \ |
|
## {INPUT_ARBITER 0 1 input_arbiter_v1_0_0/data/input_arbiter_regs_defines.txt} \ |
|
## {OUTPUT_QUEUES 0 1 output_queues_v1_0_0/data/output_queues_regs_defines.txt} \ |
|
## {OUTPUT_PORT_LOOKUP 0 1 switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.txt} \ |
|
## {NF_10G_INTERFACE0 0 1 nf_10ge_interface_shared_v1_0_0/data/nf_10g_interface_shared_regs_defines.txt} \ |
|
## {NF_10G_INTERFACE1 1 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ |
|
## {NF_10G_INTERFACE2 2 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ |
|
## {NF_10G_INTERFACE3 3 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \ |
|
## {NF_RIFFA_DMA 0 1 nf_riffa_dma_v1_0_0/data/nf_riffa_dma_regs_defines.txt} \ |
|
## |
|
## |
|
## } |
|
## set target_path $::env(NF_DESIGN_DIR)/sw/embedded/src/ |
|
## set target_file $target_path/sume_register_defines.h |
|
## proc write_header { target_file } { |
|
## |
|
## # creat a blank header file |
|
## # do a fresh rewrite in case the file already exits |
|
## file delete -force $target_file |
|
## open $target_file "w" |
|
## set h_file [open $target_file "w"] |
|
## |
|
## |
|
## puts $h_file "//-" |
|
## puts $h_file "// Copyright (c) 2015 University of Cambridge" |
|
## puts $h_file "// All rights reserved." |
|
## puts $h_file "//" |
|
## puts $h_file "// This software was developed by Stanford University and the University of Cambridge Computer Laboratory " |
|
## puts $h_file "// under National Science Foundation under Grant No. CNS-0855268," |
|
## puts $h_file "// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and" |
|
## puts $h_file "// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 (\"MRC2\"), " |
|
## puts $h_file "// as part of the DARPA MRC research programme." |
|
## puts $h_file "//" |
|
## puts $h_file "// @NETFPGA_LICENSE_HEADER_START@" |
|
## puts $h_file "//" |
|
## puts $h_file "// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor" |
|
## puts $h_file "// license agreements. See the NOTICE file distributed with this work for" |
|
## puts $h_file "// additional information regarding copyright ownership. NetFPGA licenses this" |
|
## puts $h_file "// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the" |
|
## puts $h_file "// \"License\"); you may not use this file except in compliance with the" |
|
## puts $h_file "// License. You may obtain a copy of the License at:" |
|
## puts $h_file "//" |
|
## puts $h_file "// http://www.netfpga-cic.org" |
|
## puts $h_file "//" |
|
## puts $h_file "// Unless required by applicable law or agreed to in writing, Work distributed" |
|
## puts $h_file "// under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR" |
|
## puts $h_file "// CONDITIONS OF ANY KIND, either express or implied. See the License for the" |
|
## puts $h_file "// specific language governing permissions and limitations under the License." |
|
## puts $h_file "//" |
|
## puts $h_file "// @NETFPGA_LICENSE_HEADER_END@" |
|
## puts $h_file "/////////////////////////////////////////////////////////////////////////////////" |
|
## puts $h_file "// This is an automatically generated header definitions file" |
|
## puts $h_file "/////////////////////////////////////////////////////////////////////////////////" |
|
## puts $h_file "" |
|
## |
|
## close $h_file |
|
## |
|
## }; |
|
## proc write_core {target_file prefix id has_registers lib_name} { |
|
## |
|
## |
|
## set h_file [open $target_file "a"] |
|
## |
|
## #First, read the memory map information from the reference_project defines file |
|
## source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl |
|
## set public_repo_dir $::env(SUME_FOLDER)/lib/hw/ |
|
## |
|
## |
|
## set baseaddr [set $prefix\_BASEADDR] |
|
## set highaddr [set $prefix\_HIGHADDR] |
|
## set sizeaddr [set $prefix\_SIZEADDR] |
|
## |
|
## puts $h_file "//######################################################" |
|
## puts $h_file "//# Definitions for $prefix" |
|
## puts $h_file "//######################################################" |
|
## |
|
## puts $h_file "#define SUME_$prefix\_BASEADDR $baseaddr" |
|
## puts $h_file "#define SUME_$prefix\_HIGHADDR $highaddr" |
|
## puts $h_file "#define SUME_$prefix\_SIZEADDR $sizeaddr" |
|
## puts $h_file "" |
|
## |
|
## #Second, read the registers information from the library defines file |
|
## if $has_registers { |
|
## set lib_path "$public_repo_dir/std/cores/$lib_name" |
|
## set regs_h_define_file $lib_path |
|
## set regs_h_define_file_read [open $regs_h_define_file r] |
|
## set regs_h_define_file_data [read $regs_h_define_file_read] |
|
## close $regs_h_define_file_read |
|
## set regs_h_define_file_data_line [split $regs_h_define_file_data "\n"] |
|
## |
|
## foreach read_line $regs_h_define_file_data_line { |
|
## if {[regexp "#define" $read_line]} { |
|
## puts $h_file "#define SUME_[lindex $read_line 2]\_$id\_[lindex $read_line 3]\_[lindex $read_line 4] [lindex $read_line 5]" |
|
## } |
|
## } |
|
## } |
|
## puts $h_file "" |
|
## close $h_file |
|
## }; |
|
## write_header $target_file |
|
## foreach lib_item $DEF_LIST { |
|
## write_core $target_file [lindex $lib_item 0] [lindex $lib_item 1] [lindex $lib_item 2] [lindex $lib_item 3] |
|
## } |
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
### set M00_BASEADDR 0x44000000 |
|
### set M00_HIGHADDR 0x44000FFF |
|
### set M00_SIZEADDR 0x1000 |
|
### set M01_BASEADDR 0x44010000 |
|
### set M01_HIGHADDR 0x44010FFF |
|
### set M01_SIZEADDR 0x1000 |
|
### set M02_BASEADDR 0x44020000 |
|
### set M02_HIGHADDR 0x44020FFF |
|
### set M02_SIZEADDR 0x1000 |
|
### set M03_BASEADDR 0x44030000 |
|
### set M03_HIGHADDR 0x44030FFF |
|
### set M03_SIZEADDR 0x1000 |
|
### set M04_BASEADDR 0x44040000 |
|
### set M04_HIGHADDR 0x44040FFF |
|
### set M04_SIZEADDR 0x1000 |
|
### set M05_BASEADDR 0x44050000 |
|
### set M05_HIGHADDR 0x44050FFF |
|
### set M05_SIZEADDR 0x1000 |
|
### set M06_BASEADDR 0x44060000 |
|
### set M06_HIGHADDR 0x44060FFF |
|
### set M06_SIZEADDR 0x1000 |
|
### set M07_BASEADDR 0x44070000 |
|
### set M07_HIGHADDR 0x44070FFF |
|
### set M07_SIZEADDR 0x1000 |
|
### set M08_BASEADDR 0x44080000 |
|
### set M08_HIGHADDR 0x44080FFF |
|
### set M08_SIZEADDR 0x1000 |
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
### set M00_BASEADDR 0x44000000 |
|
### set M00_HIGHADDR 0x44000FFF |
|
### set M00_SIZEADDR 0x1000 |
|
### set M01_BASEADDR 0x44010000 |
|
### set M01_HIGHADDR 0x44010FFF |
|
### set M01_SIZEADDR 0x1000 |
|
### set M02_BASEADDR 0x44020000 |
|
### set M02_HIGHADDR 0x44020FFF |
|
### set M02_SIZEADDR 0x1000 |
|
### set M03_BASEADDR 0x44030000 |
|
### set M03_HIGHADDR 0x44030FFF |
|
### set M03_SIZEADDR 0x1000 |
|
### set M04_BASEADDR 0x44040000 |
|
### set M04_HIGHADDR 0x44040FFF |
|
### set M04_SIZEADDR 0x1000 |
|
### set M05_BASEADDR 0x44050000 |
|
### set M05_HIGHADDR 0x44050FFF |
|
### set M05_SIZEADDR 0x1000 |
|
### set M06_BASEADDR 0x44060000 |
|
### set M06_HIGHADDR 0x44060FFF |
|
### set M06_SIZEADDR 0x1000 |
|
### set M07_BASEADDR 0x44070000 |
|
### set M07_HIGHADDR 0x44070FFF |
|
### set M07_SIZEADDR 0x1000 |
|
### set M08_BASEADDR 0x44080000 |
|
### set M08_HIGHADDR 0x44080FFF |
|
### set M08_SIZEADDR 0x1000 |
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
### set M00_BASEADDR 0x44000000 |
|
### set M00_HIGHADDR 0x44000FFF |
|
### set M00_SIZEADDR 0x1000 |
|
### set M01_BASEADDR 0x44010000 |
|
### set M01_HIGHADDR 0x44010FFF |
|
### set M01_SIZEADDR 0x1000 |
|
### set M02_BASEADDR 0x44020000 |
|
### set M02_HIGHADDR 0x44020FFF |
|
### set M02_SIZEADDR 0x1000 |
|
### set M03_BASEADDR 0x44030000 |
|
### set M03_HIGHADDR 0x44030FFF |
|
### set M03_SIZEADDR 0x1000 |
|
### set M04_BASEADDR 0x44040000 |
|
### set M04_HIGHADDR 0x44040FFF |
|
### set M04_SIZEADDR 0x1000 |
|
### set M05_BASEADDR 0x44050000 |
|
### set M05_HIGHADDR 0x44050FFF |
|
### set M05_SIZEADDR 0x1000 |
|
### set M06_BASEADDR 0x44060000 |
|
### set M06_HIGHADDR 0x44060FFF |
|
### set M06_SIZEADDR 0x1000 |
|
### set M07_BASEADDR 0x44070000 |
|
### set M07_HIGHADDR 0x44070FFF |
|
### set M07_SIZEADDR 0x1000 |
|
### set M08_BASEADDR 0x44080000 |
|
### set M08_HIGHADDR 0x44080FFF |
|
### set M08_SIZEADDR 0x1000 |
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
### set M00_BASEADDR 0x44000000 |
|
### set M00_HIGHADDR 0x44000FFF |
|
### set M00_SIZEADDR 0x1000 |
|
### set M01_BASEADDR 0x44010000 |
|
### set M01_HIGHADDR 0x44010FFF |
|
### set M01_SIZEADDR 0x1000 |
|
### set M02_BASEADDR 0x44020000 |
|
### set M02_HIGHADDR 0x44020FFF |
|
### set M02_SIZEADDR 0x1000 |
|
### set M03_BASEADDR 0x44030000 |
|
### set M03_HIGHADDR 0x44030FFF |
|
### set M03_SIZEADDR 0x1000 |
|
### set M04_BASEADDR 0x44040000 |
|
### set M04_HIGHADDR 0x44040FFF |
|
### set M04_SIZEADDR 0x1000 |
|
### set M05_BASEADDR 0x44050000 |
|
### set M05_HIGHADDR 0x44050FFF |
|
### set M05_SIZEADDR 0x1000 |
|
### set M06_BASEADDR 0x44060000 |
|
### set M06_HIGHADDR 0x44060FFF |
|
### set M06_SIZEADDR 0x1000 |
|
### set M07_BASEADDR 0x44070000 |
|
### set M07_HIGHADDR 0x44070FFF |
|
### set M07_SIZEADDR 0x1000 |
|
### set M08_BASEADDR 0x44080000 |
|
### set M08_HIGHADDR 0x44080FFF |
|
### set M08_SIZEADDR 0x1000 |
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
### set M00_BASEADDR 0x44000000 |
|
### set M00_HIGHADDR 0x44000FFF |
|
### set M00_SIZEADDR 0x1000 |
|
### set M01_BASEADDR 0x44010000 |
|
### set M01_HIGHADDR 0x44010FFF |
|
### set M01_SIZEADDR 0x1000 |
|
### set M02_BASEADDR 0x44020000 |
|
### set M02_HIGHADDR 0x44020FFF |
|
### set M02_SIZEADDR 0x1000 |
|
### set M03_BASEADDR 0x44030000 |
|
### set M03_HIGHADDR 0x44030FFF |
|
### set M03_SIZEADDR 0x1000 |
|
### set M04_BASEADDR 0x44040000 |
|
### set M04_HIGHADDR 0x44040FFF |
|
### set M04_SIZEADDR 0x1000 |
|
### set M05_BASEADDR 0x44050000 |
|
### set M05_HIGHADDR 0x44050FFF |
|
### set M05_SIZEADDR 0x1000 |
|
### set M06_BASEADDR 0x44060000 |
|
### set M06_HIGHADDR 0x44060FFF |
|
### set M06_SIZEADDR 0x1000 |
|
### set M07_BASEADDR 0x44070000 |
|
### set M07_HIGHADDR 0x44070FFF |
|
### set M07_SIZEADDR 0x1000 |
|
### set M08_BASEADDR 0x44080000 |
|
### set M08_HIGHADDR 0x44080FFF |
|
### set M08_SIZEADDR 0x1000 |
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
### set M00_BASEADDR 0x44000000 |
|
### set M00_HIGHADDR 0x44000FFF |
|
### set M00_SIZEADDR 0x1000 |
|
### set M01_BASEADDR 0x44010000 |
|
### set M01_HIGHADDR 0x44010FFF |
|
### set M01_SIZEADDR 0x1000 |
|
### set M02_BASEADDR 0x44020000 |
|
### set M02_HIGHADDR 0x44020FFF |
|
### set M02_SIZEADDR 0x1000 |
|
### set M03_BASEADDR 0x44030000 |
|
### set M03_HIGHADDR 0x44030FFF |
|
### set M03_SIZEADDR 0x1000 |
|
### set M04_BASEADDR 0x44040000 |
|
### set M04_HIGHADDR 0x44040FFF |
|
### set M04_SIZEADDR 0x1000 |
|
### set M05_BASEADDR 0x44050000 |
|
### set M05_HIGHADDR 0x44050FFF |
|
### set M05_SIZEADDR 0x1000 |
|
### set M06_BASEADDR 0x44060000 |
|
### set M06_HIGHADDR 0x44060FFF |
|
### set M06_SIZEADDR 0x1000 |
|
### set M07_BASEADDR 0x44070000 |
|
### set M07_HIGHADDR 0x44070FFF |
|
### set M07_SIZEADDR 0x1000 |
|
### set M08_BASEADDR 0x44080000 |
|
### set M08_HIGHADDR 0x44080FFF |
|
### set M08_SIZEADDR 0x1000 |
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
|
### set M00_BASEADDR 0x44000000 |
|
### set M00_HIGHADDR 0x44000FFF |
|
### set M00_SIZEADDR 0x1000 |
|
### set M01_BASEADDR 0x44010000 |
|
### set M01_HIGHADDR 0x44010FFF |
|
### set M01_SIZEADDR 0x1000 |
|
### set M02_BASEADDR 0x44020000 |
|
### set M02_HIGHADDR 0x44020FFF |
|
### set M02_SIZEADDR 0x1000 |
|
### set M03_BASEADDR 0x44030000 |
|
### set M03_HIGHADDR 0x44030FFF |
|
### set M03_SIZEADDR 0x1000 |
|
### set M04_BASEADDR 0x44040000 |
|
### set M04_HIGHADDR 0x44040FFF |
|
### set M04_SIZEADDR 0x1000 |
|
### set M05_BASEADDR 0x44050000 |
|
### set M05_HIGHADDR 0x44050FFF |
|
### set M05_SIZEADDR 0x1000 |
|
### set M06_BASEADDR 0x44060000 |
|
### set M06_HIGHADDR 0x44060FFF |
|
### set M06_SIZEADDR 0x1000 |
|
### set M07_BASEADDR 0x44070000 |
|
### set M07_HIGHADDR 0x44070FFF |
|
### set M07_SIZEADDR 0x1000 |
|
### set M08_BASEADDR 0x44080000 |
|
### set M08_HIGHADDR 0x44080FFF |
|
### set M08_SIZEADDR 0x1000 |
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR |
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR |
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR |
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR |
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR |
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR |
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR |
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR |
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR |
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR |
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR |
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR |
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR |
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR |
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR |
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR |
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR |
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR |
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR |
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR |
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR |
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR |
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR |
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR |
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000 |
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF |
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000 |
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000 |
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### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF |
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### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000 |
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### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000 |
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### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF |
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### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000 |
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### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000 |
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### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF |
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### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000 |
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### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000 |
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### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF |
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### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000 |
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### set M00_BASEADDR 0x44000000 |
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### set M00_HIGHADDR 0x44000FFF |
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### set M00_SIZEADDR 0x1000 |
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### set M01_BASEADDR 0x44010000 |
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### set M01_HIGHADDR 0x44010FFF |
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### set M01_SIZEADDR 0x1000 |
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### set M02_BASEADDR 0x44020000 |
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### set M02_HIGHADDR 0x44020FFF |
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### set M02_SIZEADDR 0x1000 |
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### set M03_BASEADDR 0x44030000 |
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### set M03_HIGHADDR 0x44030FFF |
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### set M03_SIZEADDR 0x1000 |
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### set M04_BASEADDR 0x44040000 |
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### set M04_HIGHADDR 0x44040FFF |
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### set M04_SIZEADDR 0x1000 |
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### set M05_BASEADDR 0x44050000 |
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### set M05_HIGHADDR 0x44050FFF |
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### set M05_SIZEADDR 0x1000 |
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### set M06_BASEADDR 0x44060000 |
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### set M06_HIGHADDR 0x44060FFF |
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### set M06_SIZEADDR 0x1000 |
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### set M07_BASEADDR 0x44070000 |
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### set M07_HIGHADDR 0x44070FFF |
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### set M07_SIZEADDR 0x1000 |
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### set M08_BASEADDR 0x44080000 |
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### set M08_HIGHADDR 0x44080FFF |
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### set M08_SIZEADDR 0x1000 |
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### set IDENTIFIER_BASEADDR $M00_BASEADDR |
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### set IDENTIFIER_HIGHADDR $M00_HIGHADDR |
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### set IDENTIFIER_SIZEADDR $M00_SIZEADDR |
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### set INPUT_ARBITER_BASEADDR $M01_BASEADDR |
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### se |