master-thesis/netpfga/log/compile-2019-07-23-133337

1276 lines
125 KiB
Plaintext
Raw Blame History

This file contains ambiguous Unicode characters

This file contains Unicode characters that might be confused with other characters. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

+ date
Die Jul 23 13:33:37 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
+ make
make -C src/ clean
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
make -C testdata/ clean
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
rm -rf nf_sume_sdnet_ip/
rm -f ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk_23057.backup.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xelab.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xvlog.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.jou ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsc.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsimcrash.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsimkernel.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk_23057.backup.jou ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk.jou
rm -f sw/config_tables.c
make -C src/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
minip4_solution.p4(54): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when TopParser terminates
out metadata meta,
^^^^
minip4_solution.p4(52)
parser TopParser(packet_in packet,
^^^^^^^^^
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
make -C testdata/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
./gen_testdata.py
Applying pkt on nf0 at 1:
Applying pkt on nf1 at 2:
Applying pkt on nf2 at 3:
Applying pkt on nf3 at 4:
nf0_applied times: [1]
nf1_applied times: [2]
nf2_applied times: [3]
nf3_applied times: [4]
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
Xilinx SDNet Compiler version 2018.2, build 2342300
Compilation successful
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_externs.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ ./testdata/ ./sw/ --base_address 0x44020000
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_API.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_CLI.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o libcam.so libcam.o CAM.o -lsumereg
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
# The following command only applies if running P4_SWITCH Questa Simulation with Ubuntu
sed -i 's/vsim/vsim \-ldflags \"\-B\/usr\/lib\/x86\_64\-linux-gnu\"/g' nf_sume_sdnet_ip/SimpleSumeSwitch/questa.bash
# modify the P4_SWITCH_tb so that it writes the table configuration writes to a file
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/modify_P4_SWITCH_tb.py nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv
# Fix introduced for SDNet 2017.4
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
# Fix introduced for SDNet 2018.2
sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/
cp testdata/*.axi nf_sume_sdnet_ip/SimpleSumeSwitch/
+ date
Die Jul 23 13:33:41 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch
+ ./vivado_sim.bash
+ find -name '*.v' -o -name '*.vp' -o -name '*.sv'
+ xargs -I % /opt/Xilinx/Vivado/2018.2/bin/xvlog -sv %
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_Engine
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_lookup_table_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_lookup_table_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_lookup_table_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_TopPipe_fl_temp
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_hdr_ethernet_dst_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_hdr_ethernet_src_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v" into library work
INFO: [VRFC 10-311] analyzing module S_RESETTER_lookup
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v" into library work
INFO: [VRFC 10-311] analyzing module S_RESETTER_line
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v" into library work
INFO: [VRFC 10-311] analyzing module S_RESETTER_control
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopDeparser_t_Engine
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_remove
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_dst_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_src_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_ethertype
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataMux
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopDeparser_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopParser_t_Engine
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ExtractShifter
INFO: [VRFC 10-311] analyzing module TopParser_t_start
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_icmp
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_icmp6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_icmp6_na_ns
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_ipv4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_udp_v6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_udp_v4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_tcp_v6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_tcp_v4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_v4sum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_v6sum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_headerdiff
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_digest_data_unused
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_ethertype
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_reject
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_TupleForward
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ExtractShifter
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_version
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_ihl
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_diff_serv
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_ecn
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_totalLen
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_identification
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_flags
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_fragOffset
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_ttl
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_protocol
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_meta_length_without_ip_header
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_version
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_traffic_class
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_flow_label
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_payload_length
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_next_header
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_hop_limit
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_meta_length_without_ip_header
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_arp
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_hw_type
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_protocol
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_hw_size
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_protocol_size
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_opcode
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_src_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_src_ipv4_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_dst_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_dst_ipv4_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_TupleForward
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_ExtractShifter
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_type
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_code
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_seqNo
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_ackNo
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_data_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_res
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_cwr
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_ece
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_urg
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_ack
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_psh
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_rst
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_syn
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_fin
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_window
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_urgentPtr
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_udp
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_payload_length
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_type
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_code
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_TupleForward
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_ExtractShifter
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_router
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_solicitated
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_override
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_reserved
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_target_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_type
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_ll_length
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_TupleForward
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_4
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_4_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_accept
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopParser_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_lookup_table_tuple_in_request.v" into library work
INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_lookup_table_tuple_in_request
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_fifo_base
INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
INFO: [VRFC 10-311] analyzing module xpm_counter_updn
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
INFO: [VRFC 10-311] analyzing module xpm_fifo_async
INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_lookup_table_tuple_in_request.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp" into library work
ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.v" into library work
INFO: [VRFC 10-311] analyzing module S_CONTROLLER_SimpleSumeSwitch
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_Engine
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_lookup_table_req_lookup_request_key
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/lookup_table_t.vp" into library work
INFO: [VRFC 10-311] analyzing module lookup_table_t_Wrap
INFO: [VRFC 10-311] analyzing module lookup_table_t_IntTop
INFO: [VRFC 10-311] analyzing module lookup_table_t_Lookup
INFO: [VRFC 10-311] analyzing module lookup_table_t_Hash_Lookup
INFO: [VRFC 10-311] analyzing module lookup_table_t_RamR1RW1
INFO: [VRFC 10-311] analyzing module lookup_table_t_Cam
INFO: [VRFC 10-311] analyzing module lookup_table_t_Update
INFO: [VRFC 10-311] analyzing module lookup_table_t_Hash_Update
INFO: [VRFC 10-311] analyzing module lookup_table_t_Randmod4
INFO: [VRFC 10-311] analyzing module lookup_table_t_Randmod4_Rnd
INFO: [VRFC 10-311] analyzing module lookup_table_t_Randmod5
INFO: [VRFC 10-311] analyzing module lookup_table_t_Randmod5_Rnd
INFO: [VRFC 10-311] analyzing module lookup_table_t_csr
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/lookup_table_t.v" into library work
INFO: [VRFC 10-311] analyzing module lookup_table_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" into library work
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch_tb
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v" into library work
INFO: [VRFC 10-311] analyzing module TB_System_Stim
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" into library work
INFO: [VRFC 10-311] analyzing module Check
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v" into library work
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_INGRESS
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v" into library work
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_EGRESS
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v" into library work
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for__OUT_
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_fifo.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_fifo_base
INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
INFO: [VRFC 10-311] analyzing module xpm_counter_updn
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
INFO: [VRFC 10-311] analyzing module xpm_fifo_async
INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopParser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
+ true
+ mkdir -p xsim.dir/xsc
+ find -name '*.c'
+ xargs /opt/Xilinx/Vivado/2018.2/bin/xsc -mt off -v 1
Turned off multi-threading.
Running compilation flow
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/CAM.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" -DXILINX_SIMULATOR
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/user.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -DXILINX_SIMULATOR
./Testbench/user.c: In function register_write_control:
./Testbench/user.c:37:5: warning: implicit declaration of function SV_write_control [-Wimplicit-function-declaration]
SV_write_control(&sv_addr, &sv_data);
^~~~~~~~~~~~~~~~
./Testbench/user.c: In function register_read_control:
./Testbench/user.c:51:5: warning: implicit declaration of function SV_read_control [-Wimplicit-function-declaration]
SV_read_control(&sv_addr, &sv_data);
^~~~~~~~~~~~~~~
./Testbench/user.c: In function CAM_Init:
./Testbench/user.c:88:76: warning: passing argument 9 of CAM_Init_ValidateContext from incompatible pointer type [-Wincompatible-pointer-types]
if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
^~~~~~~~~~~~~~
In file included from ./Testbench/user.c:7:0:
./Testbench/CAM.h:169:5: note: expected void (*)(addr_t, uint32_t) {aka void (*)(long long unsigned int, unsigned int)} but argument is of type void (*)(uint32_t, uint32_t) {aka void (*)(unsigned int, unsigned int)}
int CAM_Init_ValidateContext(
^~~~~~~~~~~~~~~~~~~~~~~~
./Testbench/user.c:88:92: warning: passing argument 10 of CAM_Init_ValidateContext from incompatible pointer type [-Wincompatible-pointer-types]
if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
^~~~~~~~~~~~~
In file included from ./Testbench/user.c:7:0:
./Testbench/CAM.h:169:5: note: expected uint32_t (*)(addr_t) {aka unsigned int (*)(long long unsigned int)} but argument is of type uint32_t (*)(uint32_t) {aka unsigned int (*)(unsigned int)}
int CAM_Init_ValidateContext(
^~~~~~~~~~~~~~~~~~~~~~~~
Done compilation
Linking with command:
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/
Running command : /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/
Done linking: "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so"
+ /opt/Xilinx/Vivado/2018.2/bin/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl
Multi-threading is on. Using 6 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module work.S_RESETTER_line
Compiling module work.S_RESETTER_lookup
Compiling module work.S_RESETTER_control
Compiling module work.TopParser_t_EngineStage_0_ErrorC...
Compiling module work.TopParser_t_EngineStage_0_Extrac...
Compiling module work.TopParser_t_start_compute_meta_c...
Compiling module work.TopParser_t_start_compute_meta_c...
Compiling module work.TopParser_t_start_compute_meta_c...
Compiling module work.TopParser_t_start_compute_meta_c...
Compiling module work.TopParser_t_start_compute_meta_c...
Compiling module work.TopParser_t_start_compute_meta_c...
Compiling module work.TopParser_t_start_compute_meta_c...
Compiling module work.TopParser_t_start_compute_meta_c...
Compiling module work.TopParser_t_start_compute_meta_v...
Compiling module work.TopParser_t_start_compute_meta_v...
Compiling module work.TopParser_t_start_compute_meta_h...
Compiling module work.TopParser_t_start_compute_digest...
Compiling module work.TopParser_t_start_compute_hdr_et...
Compiling module work.TopParser_t_start_compute_hdr_et...
Compiling module work.TopParser_t_start_compute_hdr_et...
Compiling module work.TopParser_t_start_compute_hdr_et...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_contro...
Compiling module work.TopParser_t_start_compute_contro...
Compiling module work.TopParser_t_start
Compiling module work.TopParser_t_reject_compute_contr...
Compiling module work.TopParser_t_reject_compute_contr...
Compiling module work.TopParser_t_reject
Compiling module work.TopParser_t_EngineStage_0_TupleF...
Compiling module work.TopParser_t_EngineStage_0
Compiling module work.TopParser_t_EngineStage_1_ErrorC...
Compiling module work.TopParser_t_EngineStage_1_Extrac...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv4_compute_TopPars...
Compiling module work.TopParser_t_ipv4_compute_meta_le...
Compiling module work.TopParser_t_ipv4_compute_control...
Compiling module work.TopParser_t_ipv4_compute_control...
Compiling module work.TopParser_t_ipv4
Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
Compiling module work.TopParser_t_ipv6_compute_TopPars...
Compiling module work.TopParser_t_ipv6_compute_meta_le...
Compiling module work.TopParser_t_ipv6_compute_control...
Compiling module work.TopParser_t_ipv6_compute_control...
Compiling module work.TopParser_t_ipv6
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
Compiling module work.TopParser_t_arp_compute_TopParse...
Compiling module work.TopParser_t_arp_compute_control_...
Compiling module work.TopParser_t_arp_compute_control_...
Compiling module work.TopParser_t_arp
Compiling module work.TopParser_t_EngineStage_1_TupleF...
Compiling module work.TopParser_t_EngineStage_1
Compiling module work.TopParser_t_EngineStage_2_ErrorC...
Compiling module work.TopParser_t_EngineStage_2_Extrac...
Compiling module work.TopParser_t_icmp6_compute_hdr_ic...
Compiling module work.TopParser_t_icmp6_compute_hdr_ic...
Compiling module work.TopParser_t_icmp6_compute_hdr_ic...
Compiling module work.TopParser_t_icmp6_compute_hdr_ic...
Compiling module work.TopParser_t_icmp6_compute_TopPar...
Compiling module work.TopParser_t_icmp6_compute_contro...
Compiling module work.TopParser_t_icmp6_compute_contro...
Compiling module work.TopParser_t_icmp6
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
Compiling module work.TopParser_t_tcp_compute_TopParse...
Compiling module work.TopParser_t_tcp_compute_control_...
Compiling module work.TopParser_t_tcp_compute_control_...
Compiling module work.TopParser_t_tcp
Compiling module work.TopParser_t_udp_compute_hdr_udp_...
Compiling module work.TopParser_t_udp_compute_hdr_udp_...
Compiling module work.TopParser_t_udp_compute_hdr_udp_...
Compiling module work.TopParser_t_udp_compute_hdr_udp_...
Compiling module work.TopParser_t_udp_compute_hdr_udp_...
Compiling module work.TopParser_t_udp_compute_TopParse...
Compiling module work.TopParser_t_udp_compute_control_...
Compiling module work.TopParser_t_udp_compute_control_...
Compiling module work.TopParser_t_udp
Compiling module work.TopParser_t_icmp_compute_hdr_icm...
Compiling module work.TopParser_t_icmp_compute_hdr_icm...
Compiling module work.TopParser_t_icmp_compute_hdr_icm...
Compiling module work.TopParser_t_icmp_compute_hdr_icm...
Compiling module work.TopParser_t_icmp_compute_TopPars...
Compiling module work.TopParser_t_icmp_compute_control...
Compiling module work.TopParser_t_icmp_compute_control...
Compiling module work.TopParser_t_icmp
Compiling module work.TopParser_t_EngineStage_2_TupleF...
Compiling module work.TopParser_t_EngineStage_2
Compiling module work.TopParser_t_EngineStage_3_ErrorC...
Compiling module work.TopParser_t_EngineStage_3_Extrac...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_icmp6_neighbor_solic...
Compiling module work.TopParser_t_EngineStage_3_TupleF...
Compiling module work.TopParser_t_EngineStage_3
Compiling module work.TopParser_t_EngineStage_4_ErrorC...
Compiling module work.TopParser_t_accept_compute_contr...
Compiling module work.TopParser_t_accept_compute_contr...
Compiling module work.TopParser_t_accept
Compiling module work.TopParser_t_EngineStage_4
Compiling module work.TopParser_t_Engine
Compiling module work.TopParser_t
Compiling module work.TopPipe_lvl_t_setup_compute_look...
Compiling module work.TopPipe_lvl_t_setup_compute_cont...
Compiling module work.TopPipe_lvl_t_setup_compute_cont...
Compiling module work.TopPipe_lvl_t_setup
Compiling module work.TopPipe_lvl_t_EngineStage_0
Compiling module work.TopPipe_lvl_t_Engine
Compiling module work.TopPipe_lvl_t
Compiling module work.lookup_table_t_Hash_Lookup
Compiling module work.xpm_memory_base(MEMORY_SIZE=880,...
Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=88...
Compiling module work.lookup_table_t_RamR1RW1
Compiling module work.lookup_table_t_Cam
Compiling module work.lookup_table_t_Lookup
Compiling module work.lookup_table_t_Hash_Update
Compiling module work.lookup_table_t_Randmod4_Rnd
Compiling module work.lookup_table_t_Randmod4
Compiling module work.lookup_table_t_Randmod5_Rnd
Compiling module work.lookup_table_t_Randmod5
Compiling module work.lookup_table_t_Update
Compiling module work.lookup_table_t_IntTop
Compiling module work.lookup_table_t_Wrap
Compiling module work.lookup_table_t_csr
Compiling module work.lookup_table_t
Compiling module work.TopPipe_lvl_0_t_lookup_table_sec...
Compiling module work.TopPipe_lvl_0_t_lookup_table_sec...
Compiling module work.TopPipe_lvl_0_t_lookup_table_sec
Compiling module work.TopPipe_lvl_0_t_EngineStage_0
Compiling module work.TopPipe_lvl_0_t_do_nothing_0_sec...
Compiling module work.TopPipe_lvl_0_t_do_nothing_0_sec...
Compiling module work.TopPipe_lvl_0_t_do_nothing_0_sec
Compiling module work.TopPipe_lvl_0_t_send_to_all_port...
Compiling module work.TopPipe_lvl_0_t_send_to_all_port...
Compiling module work.TopPipe_lvl_0_t_send_to_all_port...
Compiling module work.TopPipe_lvl_0_t_send_to_all_port...
Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_...
Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_...
Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_...
Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_...
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
Compiling module work.TopPipe_lvl_0_t_EngineStage_1
Compiling module work.TopPipe_lvl_0_t_sink_compute_con...
Compiling module work.TopPipe_lvl_0_t_sink_compute_con...
Compiling module work.TopPipe_lvl_0_t_sink
Compiling module work.TopPipe_lvl_0_t_EngineStage_2
Compiling module work.TopPipe_lvl_0_t_Engine
Compiling module work.TopPipe_lvl_0_t
Compiling module work.TopDeparser_t_EngineStage_0_Erro...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0
Compiling module work.TopDeparser_t_EngineStage_1_Erro...
Compiling module work.TopDeparser_t_act_sec_compute_co...
Compiling module work.TopDeparser_t_act_sec_compute_co...
Compiling module work.TopDeparser_t_act_sec
Compiling module work.TopDeparser_t_EngineStage_1
Compiling module work.TopDeparser_t_EngineStage_2_Erro...
Compiling module work.TopDeparser_t_emit_0_compute_con...
Compiling module work.TopDeparser_t_emit_0_compute__ST...
Compiling module work.TopDeparser_t_emit_0_compute__ST...
Compiling module work.TopDeparser_t_emit_0_compute__ST...
Compiling module work.TopDeparser_t_emit_0_compute_con...
Compiling module work.TopDeparser_t_emit_0_compute_con...
Compiling module work.TopDeparser_t_emit_0
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
Compiling module work.TopDeparser_t_EngineStage_2
Compiling module work.TopDeparser_t_Engine
Compiling module work.TopDeparser_t
Compiling module work.xpm_cdc_sync_rst(DEST_SYNC_FF=2,...
Compiling module work.xpm_fifo_rst(COMMON_CLOCK=0)
Compiling module work.xpm_fifo_reg_bit
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=8)
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=9)
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_BRIDGER_for_lookup_table_tuple...
Compiling module work.S_PROTOCOL_ADAPTER_INGRESS
Compiling module work.S_PROTOCOL_ADAPTER_EGRESS
Compiling module work.xpm_fifo_rst_default
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_TopParser
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_S_SYNCER_for_S_SYNC...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7...
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7...
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=7)
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_S_SYNCER_for_TopDep...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for_TopDeparser
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
Compiling module work.S_SYNCER_for__OUT_
Compiling module work.S_CONTROLLER_SimpleSumeSwitch
Compiling module work.SimpleSumeSwitch
Compiling module work.TB_System_Stim
Compiling module work.Check
Compiling module work.SimpleSumeSwitch_tb
Compiling module work.glbl
Built simulation snapshot work.SimpleSumeSwitch_tb#work.glbl
****** Webtalk v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Tue Jul 23 13:34:22 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2018.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Tue Jul 23 13:34:22 2019...
+ /opt/Xilinx/Vivado/2018.2/bin/xsim --runall SimpleSumeSwitch_tb#work.glbl
****** xsim v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsim_script.tcl
# xsim {work.SimpleSumeSwitch_tb#work.glbl} -autoloadwcfg -runall
Vivado Simulator 2018.2
Time resolution is 1 ps
run -all
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_681 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_681 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_681 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_681 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_681 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_lookup_table_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_lookup_table_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1386 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.arix9aot7gegngr0fzl0g3o9ojrbkm_1659.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/arix9aot7gegngr0fzl0g3o9ojrbkm_1659/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1479 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.m7fblj43fwn0mmlbh6w62_1382.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/m7fblj43fwn0mmlbh6w62_1382/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1509 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.pnt7hq0s0vodp95vyp1pk_486.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/pnt7hq0s0vodp95vyp1pk_486/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1573 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.r610hmassma9fxs2rmts3qh_2167.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/r610hmassma9fxs2rmts3qh_2167/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1657 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.t593jd0tw6srao8ip6_2149.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t593jd0tw6srao8ip6_2149/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1479 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.u4nwcivvve3l33fv9blhuke_486.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/u4nwcivvve3l33fv9blhuke_486/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1509 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.akvr55nrwhw17k4czgoih10kw0dp3g_493.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/akvr55nrwhw17k4czgoih10kw0dp3g_493/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1838 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.ta4deoe2y5kkgv4djga7nbas1vzmgwwd_1084.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ta4deoe2y5kkgv4djga7nbas1vzmgwwd_1084/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1922 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.hzgjabhaq0hra3fkatg83f00if_136.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/hzgjabhaq0hra3fkatg83f00if_136/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2006 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.tef5t32v13pt924fzp2a_1210.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/tef5t32v13pt924fzp2a_1210/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1573 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.fkwzgyfunskma5wx383kx84rvcz_59.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/fkwzgyfunskma5wx383kx84rvcz_59/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1657 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.uurdostp9qa04hlgrq_1883.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uurdostp9qa04hlgrq_1883/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2258 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.i52tymyxx50tvmap9erhb7ox0fvd4s_1764.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/i52tymyxx50tvmap9erhb7ox0fvd4s_1764/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1479 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.ad4fckvy2ariyubrin3lkp07_960.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/ad4fckvy2ariyubrin3lkp07_960/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1509 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.msctrvq72bfqx1vydaxy2xyl7lw9ykoo_1559.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/msctrvq72bfqx1vydaxy2xyl7lw9ykoo_1559/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2445 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.h4gvf1m6j684ttttmj2jsaz8w_785.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/h4gvf1m6j684ttttmj2jsaz8w_785/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2006 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.i01iotcgwxvfo7spewcl0dxp_202.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/i01iotcgwxvfo7spewcl0dxp_202/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1838 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.zykaqzx2g7ykocz0ne0er_1588.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/zykaqzx2g7ykocz0ne0er_1588/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2697 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.h7qoujd1vmc7es7xbtw9t9ixeu2y7vd_160.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/h7qoujd1vmc7es7xbtw9t9ixeu2y7vd_160/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1922 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.unb4oz5bcus7o09qruubef48jrt94wtf_226.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/unb4oz5bcus7o09qruubef48jrt94wtf_226/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1573 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.vyq7cnhzpv1c20f4rdxkloir7_605.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/vyq7cnhzpv1c20f4rdxkloir7_605/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2949 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.gcj45xtlvb5ykg9ot8_1110.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/gcj45xtlvb5ykg9ot8_1110/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1657 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.qkgmjxknpo5h234pmhk074y7n9wufer_30.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/qkgmjxknpo5h234pmhk074y7n9wufer_30/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2258 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.d2z8c9nxqdnp8fgsvw7ukt_804.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/d2z8c9nxqdnp8fgsvw7ukt_804/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1479 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.vw2e61ly3sang4uzsqnpyk2fnul73bc_92.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/vw2e61ly3sang4uzsqnpyk2fnul73bc_92/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1509 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.djg6mclub92h1mdquvqij2jpv_2229.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/djg6mclub92h1mdquvqij2jpv_2229/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1838 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.jgspwg4oavie7crwrw8fdli_1774.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/jgspwg4oavie7crwrw8fdli_1774/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1922 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.rqil1vcocag3cjbo0jfctlz8oee_214.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/rqil1vcocag3cjbo0jfctlz8oee_214/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2006 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.mgye1cg4gmhqoj8g34r_1441.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/mgye1cg4gmhqoj8g34r_1441/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1573 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.n56n0x8lh4cfry4t73_1106.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/n56n0x8lh4cfry4t73_1106/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1657 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.n3q7mx2r5rybugmp75okl42_2566.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/n3q7mx2r5rybugmp75okl42_2566/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2258 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.hon8ja6j7ph6cj60ur8gxx948hm_1645.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/hon8ja6j7ph6cj60ur8gxx948hm_1645/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_3803 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.qonv9bbfnh3qqzkc21a6yt_1168.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/qonv9bbfnh3qqzkc21a6yt_1168/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1509 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.jql4cs4njz02t1tu_2461.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/jql4cs4njz02t1tu_2461/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2006 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.zt9lwhcioap5pcp8y8g1cish2mu_2448.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/zt9lwhcioap5pcp8y8g1cish2mu_2448/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1573 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv
[SW] CAM_Init() - start
[SW] CAM_Init() - done
[SW] CAM_EnableDevice() - start
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_write_control()- start
[SW] CAM_EnableDevice() - done
SV_write_control()- done
[2280754] INFO: finished packet stimulus file
[2828868] INFO: packet 1 tuple OK < tuple_out_digest_data, tuple_out_standard_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
[2828868] INFO: packet 1 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208)
[2832200] INFO: packet 1 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000)
[2838864] INFO: packet 2 tuple OK < tuple_out_digest_data, tuple_out_standard_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001040000 >
[2838864] INFO: packet 2 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208)
[2842196] INFO: packet 2 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000)
[2848860] INFO: packet 3 tuple OK < tuple_out_digest_data, tuple_out_standard_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001100000 >
[2848860] INFO: packet 3 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208)
[2852192] INFO: packet 3 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000)
[2858856] INFO: packet 4 tuple OK < tuple_out_digest_data, tuple_out_standard_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001400000 >
[2858856] INFO: packet 4 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208)
[2862188] INFO: packet 4 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000)
[6197520] INFO: stopping simulation after 1000 idle cycles
[6197520] INFO: all expected data successfully received
[6197520] INFO: TEST PASSED
$finish called at time : 6197520 ps : File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" Line 207
exit
INFO: [Common 17-206] Exiting xsim at Tue Jul 23 13:34:33 2019...
+ grep ^expected /home/nico/master-thesis/netpfga/log/compile-2019-07-23-133337
+ sed -e s/.*= <// -e s/.*= (//
+ expected_line=
+ grep ^actual /home/nico/master-thesis/netpfga/log/compile-2019-07-23-133337
+ sed -e s/.*= <// -e s/.*= (//
+ actual_line=
+ [ != ]
+ date
Die Jul 23 13:34:33 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
+ make config_writes
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata
+ date
Die Jul 23 13:34:33 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
+ make uninstall_sdnet
rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip
+ make install_sdnet
rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip
cp -r nf_sume_sdnet_ip /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/
mkdir /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/hdl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper/
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/tcl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/Makefile /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
make -C /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip
vivado -mode batch -source nf_sume_sdnet.tcl
****** Vivado v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source nf_sume_sdnet.tcl
# set design nf_sume_sdnet
# set top nf_sume_sdnet
# set device xc7vx690t-3-ffg1761
# set proj_dir ./ip_proj
# set ip_version 1.00
# set lib_name NetFPGA
# create_project -name ${design} -force -dir "./${proj_dir}" -part ${device}
# set_property source_mgmt_mode All [current_project]
# set_property top ${top} [current_fileset]
# set_property ip_repo_paths $::env(SUME_FOLDER)/lib/hw/ [current_fileset]
# update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
# puts "nf_sume_sdnet"
nf_sume_sdnet
# read_verilog "./wrapper/sume_to_sdnet.v"
# read_verilog "./wrapper/nf_sume_sdnet.v"
# read_verilog "./wrapper/changeEndian.v"
# add_files -scan_for_includes ./SimpleSumeSwitch/
# import_files -force
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'
# update_compile_order -fileset sources_1
# update_compile_order -fileset sim_1
# ipx::package_project
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/wrapper/changeEndian.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM_INST0.h'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/dpi.h'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM.h'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.h'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_lookup_table_tuple_in_request.vp'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v'.
INFO: [IP_Flow 19-5169] Module 'nf_sume_sdnet' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'axis_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'S_AXI'.
INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'.
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'S_AXI_ARESETN'.
INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'axis_resetn'.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
# set_property name ${design} [ipx::current_core]
# set_property library ${lib_name} [ipx::current_core]
# set_property vendor_display_name {NetFPGA} [ipx::current_core]
# set_property company_url {http://www.netfpga.org} [ipx::current_core]
# set_property vendor {NetFPGA} [ipx::current_core]
# set_property supported_families {{virtex7} {Production}} [ipx::current_core]
# set_property taxonomy {{/NetFPGA/Generic}} [ipx::current_core]
# set_property version ${ip_version} [ipx::current_core]
# set_property display_name ${design} [ipx::current_core]
# set_property description ${design} [ipx::current_core]
# ipx::add_user_parameter {C_M_AXIS_DATA_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {C_M_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {256} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
# ipx::add_user_parameter {C_S_AXIS_DATA_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {C_S_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {256} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
# ipx::add_user_parameter {C_M_AXIS_TUSER_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {C_M_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {128} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
# ipx::add_user_parameter {C_S_AXIS_TUSER_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {C_S_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {128} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
# ipx::add_user_parameter {C_S_AXI_DATA_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {C_S_AXI_DATA_WIDTH} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {32} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
# ipx::add_user_parameter {C_S_AXI_ADDR_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {C_S_AXI_ADDR_WIDTH} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {12} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
# ipx::add_user_parameter {SDNET_ADDR_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {SDNET_ADDR_WIDTH} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {11} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagesynthesis -of_objects [ipx::current_core]]
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagebehavioralsimulation -of_objects [ipx::current_core]]
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects [ipx::current_core]]
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects [ipx::current_core]]
# update_ip_catalog -rebuild
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
# ipx::infer_user_parameters [ipx::current_core]
# ipx::check_integrity [ipx::current_core]
INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nf_sume_sdnet_v1_0.tcl" does not have the current IP <name>_v<version> format. If the IP name or version was changed recently, recreate this file to update the file format.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
# ipx::save_core [ipx::current_core]
# update_ip_catalog
# close_project
INFO: [Common 17-206] Exiting Vivado at Tue Jul 23 13:34:54 2019...
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
+ date
Die Jul 23 13:34:54 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default
+ make
rm -f config_writes.py*
rm -f *.pyc
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py ./
+ date
Die Jul 23 13:34:54 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA
+ ./tools/scripts/nf_test.py sim --major switch --minor default
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/connections': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/Makefile': No such file or directory
make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
make: *** No rule to make target 'reg'. Stop.
make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
make: *** No rule to make target 'sim'. Stop.
make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/Makefile': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_stim.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_expected.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_stim.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_expected.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_stim.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_expected.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_stim.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_expected.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_expected.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/Makefile': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.log': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_expect.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.axi': No such file or directory
NetFPGA environment:
Root dir: /home/nico/projects/P4-NetFPGA
Project name: simple_sume_switch
Project dir: /tmp/nico/test/simple_sume_switch
Work dir: /tmp/nico
512
=== Work directory is /tmp/nico/test/simple_sume_switch
=== Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default
=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
+ date
Die Jul 23 13:34:54 CEST 2019
+ [ = no ]
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch
+ make
make: *** No targets specified and no makefile found. Stop.